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Root/trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊
75#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊
76#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊
77#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊
78#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊
79␊
80extern uint32_t devices_number;␊
81␊
82const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
83const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
84const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
85const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
86const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
87const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
88const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
89const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
90const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
91␊
92static uint8_t default_NVCAP[]= {␊
93␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
94␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
95␉0x00, 0x00, 0x00, 0x00␊
96};␊
97␊
98#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
99␊
100static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
101static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
102␊
103#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
104#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
105␊
106static struct nv_chipsets_t NVKnownChipsets[] = {␊
107␉{ 0x00000000, "Unknown" },␊
108//========================================␊
109␉// 0040 - 004F␉␊
110␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
111␉{ 0x10DE0041, "GeForce 6800" },␊
112␉{ 0x10DE0042, "GeForce 6800 LE" },␊
113␉{ 0x10DE0043, "GeForce 6800 XE" },␊
114␉{ 0x10DE0044, "GeForce 6800 XT" },␊
115␉{ 0x10DE0045, "GeForce 6800 GT" },␊
116␉{ 0x10DE0046, "GeForce 6800 GT" },␊
117␉{ 0x10DE0047, "GeForce 6800 GS" },␊
118␉{ 0x10DE0048, "GeForce 6800 XT" },␊
119␉{ 0x10DE004D, "Quadro FX 3400" },␊
120␉{ 0x10DE004E, "Quadro FX 4000" },␊
121␉// 0050 - 005F␊
122␉// 0060 - 006F␉␊
123␉// 0070 - 007F␉␊
124␉// 0080 - 008F␉␊
125␉// 0090 - 009F␉␊
126␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
127␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
128␉{ 0x10DE0092, "GeForce 7800 GT" },␊
129␉{ 0x10DE0093, "GeForce 7800 GS" },␊
130␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
131␉{ 0x10DE0098, "GeForce Go 7800" },␊
132␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
133␉{ 0x10DE009D, "Quadro FX 4500" },␊
134␉// 00A0 - 00AF␉␊
135␉// 00B0 - 00BF␉␊
136␉// 00C0 - 00CF␉␊
137␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
138␉{ 0x10DE00C1, "GeForce 6800" },␊
139␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
140␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
141␉{ 0x10DE00C8, "GeForce Go 6800" },␊
142␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
143␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
144␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
145␉{ 0x10DE00CE, "Quadro FX 1400" },␊
146␉// 00D0 - 00DF␉␊
147␉// 00E0 - 00EF␉␊
148␉// 00F0 - 00FF␉␊
149␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
150␉{ 0x10DE00F2, "GeForce 6600" },␊
151␉{ 0x10DE00F3, "GeForce 6200" },␊
152␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
153␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
154␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
155␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
156␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
157␉// 0100 - 010F␉␊
158␉// 0110 - 011F␉␊
159␉// 0120 - 012F␉␊
160␉// 0130 - 013F␉␊
161␉// 0140 - 014F␉␊
162␉{ 0x10DE0140, "GeForce 6600 GT" },␊
163␉{ 0x10DE0141, "GeForce 6600" },␊
164␉{ 0x10DE0142, "GeForce 6600 LE" },␊
165␉{ 0x10DE0143, "GeForce 6600 VE" },␊
166␉{ 0x10DE0144, "GeForce Go 6600" },␊
167␉{ 0x10DE0145, "GeForce 6610 XL" },␊
168␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
169␉{ 0x10DE0147, "GeForce 6700 XL" },␊
170␉{ 0x10DE0148, "GeForce Go 6600" },␊
171␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
172␉{ 0x10DE014A, "Quadro NVS 440" },␊
173␉{ 0x10DE014C, "Quadro FX 550" },␊
174␉{ 0x10DE014D, "Quadro FX 550" },␊
175␉{ 0x10DE014E, "Quadro FX 540" },␊
176␉{ 0x10DE014F, "GeForce 6200" },␊
177␉// 0150 - 015F␉␊
178␉// 0160 - 016F␉␊
179␉{ 0x10DE0160, "GeForce 6500" },␊
180␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
181␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
182␉{ 0x10DE0163, "GeForce 6200 LE" },␊
183␉{ 0x10DE0164, "GeForce Go 6200" },␊
184␉{ 0x10DE0165, "Quadro NVS 285" },␊
185␉{ 0x10DE0166, "GeForce Go 6400" },␊
186␉{ 0x10DE0167, "GeForce Go 6200" },␊
187␉{ 0x10DE0168, "GeForce Go 6400" },␊
188␉{ 0x10DE0169, "GeForce 6250" },␊
189␉{ 0x10DE016A, "GeForce 7100 GS" },␊
190␉// 0170 - 017F␉␊
191␉// 0180 - 018F␉␊
192␉// 0190 - 019F␉␉␊
193␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
194␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
195␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
196␉{ 0x10DE0197, "Tesla C870" },␊
197␉{ 0x10DE019D, "Quadro FX 5600" },␊
198␉{ 0x10DE019E, "Quadro FX 4600" },␊
199␉// 01A0 - 01AF␉␊
200␉// 01B0 - 01BF␉␊
201␉// 01C0 - 01CF␉␊
202␉// 01D0 - 01DF␉␉␊
203␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
204␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
205␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
206␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
207␉{ 0x10DE01D6, "GeForce Go 7200" },␊
208␉{ 0x10DE01D7, "GeForce Go 7300" },␊
209␉{ 0x10DE01D8, "GeForce Go 7400" },␊
210␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
211␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
212␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
213␉{ 0x10DE01DC, "Quadro FX 350M" },␊
214␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
215␉{ 0x10DE01DE, "Quadro FX 350" },␊
216␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
217␉// 01E0 - 01EF␉␊
218␉// 01F0 - 01FF␊
219␉// 0200 - 020F␉␊
220␉// 0210 - 021F␉␊
221␉{ 0x10DE0211, "GeForce 6800" },␊
222␉{ 0x10DE0212, "GeForce 6800 LE" },␊
223␉{ 0x10DE0215, "GeForce 6800 GT" },␊
224␉{ 0x10DE0218, "GeForce 6800 XT" },␊
225␉// 0220 - 022F␉␊
226␉{ 0x10DE0221, "GeForce 6200" },␊
227␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
228␉// 0230 - 023F␉␊
229␉// 0240 - 024F␉␊
230␉{ 0x10DE0240, "GeForce 6150" },␊
231␉{ 0x10DE0241, "GeForce 6150 LE" },␊
232␉{ 0x10DE0242, "GeForce 6100" },␊
233␉{ 0x10DE0244, "GeForce Go 6150" },␊
234␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
235␉{ 0x10DE0247, "GeForce Go 6100" },␊
236␉// 0250 - 025F␉␊
237␉// 0260 - 026F␉␊
238␉// 0270 - 027F␉␊
239␉// 0280 - 028F␉␉␊
240␉// 0290 - 029F␉␊
241␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
242␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
243␉{ 0x10DE0292, "GeForce 7900 GS" },␊
244␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
245␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
246␉{ 0x10DE0295, "GeForce 7950 GT" },␊
247␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
248␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
249␉{ 0x10DE029A, "Quadro FX 2500M" },␊
250␉{ 0x10DE029B, "Quadro FX 1500M" },␊
251␉{ 0x10DE029C, "Quadro FX 5500" },␊
252␉{ 0x10DE029D, "Quadro FX 3500" },␊
253␉{ 0x10DE029E, "Quadro FX 1500" },␊
254␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
255␉// 02A0 - 02AF␉␊
256␉// 02B0 - 02BF␉␊
257␉// 02C0 - 02CF␉␊
258␉// 02D0 - 02DF␉␉␊
259␉// 02E0 - 02EF␉␉␊
260␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
261␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
262␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
263␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
264␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
265␉// 02F0 - 02FF␉␉␊
266␉// 0300 - 030F␉␉␊
267␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
268␉{ 0x10DE0302, "GeForce FX 5800" },␊
269␉{ 0x10DE0308, "Quadro FX 2000" },␊
270␉{ 0x10DE0309, "Quadro FX 1000" },␊
271␉// 0310 - 031F␉␉␊
272␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
273␉{ 0x10DE0312, "GeForce FX 5600" },␊
274␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
275␉{ 0x10DE031A, "GeForce FX Go5600" },␊
276␉{ 0x10DE031B, "GeForce FX Go5650" },␊
277␉{ 0x10DE031C, "Quadro FX Go700" },␊
278␉// 0320 - 032F␉␉␊
279␉{ 0x10DE0324, "GeForce FX Go5200" },␊
280␉{ 0x10DE0325, "GeForce FX Go5250" },␊
281␉{ 0x10DE0326, "GeForce FX 5500" },␊
282␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
283␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
284␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
285␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
286␉{ 0x10DE032D, "GeForce FX Go5100" },␊
287␉// 0330 - 033F␊
288␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
289␉{ 0x10DE0331, "GeForce FX 5900" },␊
290␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
291␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
292␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
293␉{ 0x10DE0338, "Quadro FX 3000" },␊
294␉{ 0x10DE033F, "Quadro FX 700" },␊
295␉// 0340 - 034F␊
296␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
297␉{ 0x10DE0342, "GeForce FX 5700" },␊
298␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
299␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
300␉{ 0x10DE0347, "GeForce FX Go5700" },␊
301␉{ 0x10DE0348, "GeForce FX Go5700" },␊
302␉{ 0x10DE034C, "Quadro FX Go1000" },␊
303␉{ 0x10DE034E, "Quadro FX 1100" },␊
304␉// 0350 - 035F␉␊
305␉// 0360 - 036F␉␊
306␉// 0370 - 037F␉␊
307␉// 0380 - 038F␉␉␉␊
308␉{ 0x10DE038B, "GeForce 7650 GS" },␊
309␉// 0390 - 039F␊
310␉{ 0x10DE0390, "GeForce 7650 GS" },␊
311␉{ 0x10DE0391, "GeForce 7600 GT" },␊
312␉{ 0x10DE0392, "GeForce 7600 GS" },␊
313␉{ 0x10DE0393, "GeForce 7300 GT" },␊
314␉{ 0x10DE0394, "GeForce 7600 LE" },␊
315␉{ 0x10DE0395, "GeForce 7300 GT" },␊
316␉{ 0x10DE0397, "GeForce Go 7700" },␊
317␉{ 0x10DE0398, "GeForce Go 7600" },␊
318␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
319␉{ 0x10DE039A, "Quadro NVS 300M" },␊
320␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
321␉{ 0x10DE039C, "Quadro FX 550M" },␊
322␉{ 0x10DE039E, "Quadro FX 560" },␊
323␉// 03A0 - 03AF␉␊
324␉// 03B0 - 03BF␉␊
325␉// 03C0 - 03CF␉␊
326␉// 03D0 - 03DF␉␉␉␊
327␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
328␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
329␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
330␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
331␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
332␉// 03E0 - 03EF␊
333␉// 03F0 - 03FF␊
334␉// 0400 - 040F␉␉␊
335␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
336␉{ 0x10DE0401, "GeForce 8600 GT" },␊
337␉{ 0x10DE0402, "GeForce 8600 GT" },␊
338␉{ 0x10DE0403, "GeForce 8600 GS" },␊
339␉{ 0x10DE0404, "GeForce 8400 GS" },␊
340␉{ 0x10DE0405, "GeForce 9500M GS" },␊
341␉{ 0x10DE0406, "GeForce 8300 GS" },␊
342␉{ 0x10DE0407, "GeForce 8600M GT" },␊
343␉{ 0x10DE0408, "GeForce 9650M GS" },␊
344␉{ 0x10DE0409, "GeForce 8700M GT" },␊
345␉{ 0x10DE040A, "Quadro FX 370" },␊
346␉{ 0x10DE040B, "Quadro NVS 320M" },␊
347␉{ 0x10DE040C, "Quadro FX 570M" },␊
348␉{ 0x10DE040D, "Quadro FX 1600M" },␊
349␉{ 0x10DE040E, "Quadro FX 570" },␊
350␉{ 0x10DE040F, "Quadro FX 1700" },␊
351␉// 0410 - 041F␉␊
352␉{ 0x10DE0410, "GeForce GT 330" },␊
353␉// 0420 - 042F␉␊
354␉{ 0x10DE0420, "GeForce 8400 SE" },␊
355␉{ 0x10DE0421, "GeForce 8500 GT" },␊
356␉{ 0x10DE0422, "GeForce 8400 GS" },␊
357␉{ 0x10DE0423, "GeForce 8300 GS" },␊
358␉{ 0x10DE0424, "GeForce 8400 GS" },␊
359␉{ 0x10DE0425, "GeForce 8600M GS" },␊
360␉{ 0x10DE0426, "GeForce 8400M GT" },␊
361␉{ 0x10DE0427, "GeForce 8400M GS" },␊
362␉{ 0x10DE0428, "GeForce 8400M G" },␊
363␉{ 0x10DE0429, "Quadro NVS 140M" },␊
364␉{ 0x10DE042A, "Quadro NVS 130M" },␊
365␉{ 0x10DE042B, "Quadro NVS 135M" },␊
366␉{ 0x10DE042C, "GeForce 9400 GT" },␊
367␉{ 0x10DE042D, "Quadro FX 360M" },␊
368␉{ 0x10DE042E, "GeForce 9300M G" },␊
369␉{ 0x10DE042F, "Quadro NVS 290" },␊
370␉// 0430 - 043F␊
371␉// 0440 - 044F␊
372␉// 0450 - 045F␊
373␉// 0460 - 046F␊
374␉// 0470 - 047F␊
375␉// 0480 - 048F␊
376␉// 0490 - 049F␊
377␉// 04A0 - 04AF␊
378␉// 04B0 - 04BF␊
379␉// 04C0 - 04CF␊
380␉// 04D0 - 04DF␊
381␉// 04E0 - 04EF␊
382␉// 04F0 - 04FF␊
383␉// 0500 - 050F␉␊
384␉// 0510 - 051F␉␊
385␉// 0520 - 052F␉␊
386␉// 0530 - 053F␉␊
387␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
388␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
389␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
390␉// 0540 - 054F␊
391␉// 0550 - 055F␊
392␉// 0560 - 056F␊
393␉// 0570 - 057F␊
394␉// 0580 - 058F␊
395␉// 0590 - 059F␊
396␉// 05A0 - 05AF␊
397␉// 05B0 - 05BF␊
398␉// 05C0 - 05CF␊
399␉// 05D0 - 05DF␊
400␉// 05E0 - 05EF␉␊
401␉{ 0x10DE05E0, "GeForce GTX 295" },␊
402␉{ 0x10DE05E1, "GeForce GTX 280" },␊
403␉{ 0x10DE05E2, "GeForce GTX 260" },␊
404␉{ 0x10DE05E3, "GeForce GTX 285" },␊
405␉{ 0x10DE05E6, "GeForce GTX 275" },␊
406␉{ 0x10DE05E7, "Tesla C1060" }, ␊
407␉{ 0x10DE05EA, "GeForce GTX 260" },␊
408␉{ 0x10DE05EB, "GeForce GTX 295" },␊
409␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
410␉// 05F0 - 05FF␉␉␊
411␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
412␉{ 0x10DE05F9, "Quadro CX" },␊
413␉{ 0x10DE05FD, "Quadro FX 5800" },␊
414␉{ 0x10DE05FE, "Quadro FX 4800" },␊
415␉{ 0x10DE05FF, "Quadro FX 3800" },␊
416␉// 0600 - 060F␉␊
417␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
418␉{ 0x10DE0601, "GeForce 9800 GT" },␊
419␉{ 0x10DE0602, "GeForce 8800 GT" },␊
420␉{ 0x10DE0603, "GeForce GT 230" },␊
421␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
422␉{ 0x10DE0605, "GeForce 9800 GT" },␊
423␉{ 0x10DE0606, "GeForce 8800 GS" },␊
424␉{ 0x10DE0607, "GeForce GTS 240" },␊
425␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
426␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
427␉{ 0x10DE060A, "GeForce GTX 280M" },␊
428␉{ 0x10DE060B, "GeForce 9800M GT" },␊
429␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
430␉{ 0x10DE060D, "GeForce 8800 GS" },␊
431␉{ 0x10DE060F, "GeForce GTX 285M" },␊
432␉// 0610 - 061F␉␊
433␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
434␉{ 0x10DE0611, "GeForce 8800 GT" },␊
435␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
436␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
437␉{ 0x10DE0614, "GeForce 9800 GT" },␊
438␉{ 0x10DE0615, "GeForce GTS 250" },␊
439␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
440␉{ 0x10DE0618, "GeForce GTX 260M" },␊
441␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
442␉{ 0x10DE061A, "Quadro FX 3700" },␊
443␉{ 0x10DE061B, "Quadro VX 200" },␊
444␉{ 0x10DE061C, "Quadro FX 3600M" },␊
445␉{ 0x10DE061D, "Quadro FX 2800M" },␊
446␉{ 0x10DE061E, "Quadro FX 3700M" }, ␊
447␉{ 0x10DE061F, "Quadro FX 3800M" },␊
448␉// 0620 - 062F␉␊
449␉{ 0x10DE0621, "GeForce GT 230" }, ␊
450␉{ 0x10DE0622, "GeForce 9600 GT" },␊
451␉{ 0x10DE0623, "GeForce 9600 GS" },␊
452␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
453␉{ 0x10DE0626, "GeForce GT 130" },␊
454␉{ 0x10DE0627, "GeForce GT 140" },␊
455␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
456␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
457␉{ 0x10DE062B, "GeForce 9800M GS" }, ␊
458␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
459␉{ 0x10DE062D, "GeForce 9600 GT" },␊
460␉{ 0x10DE062E, "GeForce 9600 GT" },␊
461␉// 0630 - 063F␉␊
462␉{ 0x10DE0631, "GeForce GTS 160M" },␊
463␉{ 0x10DE0632, "GeForce GTS 150M" },␊
464␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
465␉{ 0x10DE0637, "GeForce 9600 GT" },␊
466␉{ 0x10DE0638, "Quadro FX 1800" },␊
467␉{ 0x10DE063A, "Quadro FX 2700M" },␊
468␉// 0640 - 064F␉␊
469␉{ 0x10DE0640, "GeForce 9500 GT" },␊
470␉{ 0x10DE0641, "GeForce 9400 GT" },␊
471␉{ 0x10DE0642, "GeForce 8400 GS" },␊
472␉{ 0x10DE0643, "GeForce 9500 GT" },␊
473␉{ 0x10DE0644, "GeForce 9500 GS" },␊
474␉{ 0x10DE0645, "GeForce 9500 GS" },␊
475␉{ 0x10DE0646, "GeForce GT 120" },␊
476␉{ 0x10DE0647, "GeForce 9600M GT" },␊
477␉{ 0x10DE0648, "GeForce 9600M GS" },␊
478␉{ 0x10DE0649, "GeForce 9600M GT" },␊
479␉{ 0x10DE064A, "GeForce 9700M GT" },␊
480␉{ 0x10DE064B, "GeForce 9500M G" },␊
481␉{ 0x10DE064C, "GeForce 9650M GT" },␊
482␉// 0650 - 065F␉␉␊
483␉{ 0x10DE0651, "GeForce G 110M" },␊
484␉{ 0x10DE0652, "GeForce GT 130M" },␊
485␉{ 0x10DE0653, "GeForce GT 120M" },␊
486␉{ 0x10DE0654, "GeForce GT 220M" },␊
487␉{ 0x10DE0655, "GeForce GT 120" }, ␊
488␉{ 0x10DE0656, "GeForce 9650 S" },␊
489␉{ 0x10DE0658, "Quadro FX 380" },␊
490␉{ 0x10DE0659, "Quadro FX 580" },␊
491␉{ 0x10DE065A, "Quadro FX 1700M" },␊
492␉{ 0x10DE065B, "GeForce 9400 GT" },␊
493␉{ 0x10DE065C, "Quadro FX 770M" },␊
494␉{ 0x10DE065F, "GeForce G210" },␊
495␉// 0660 - 066F␊
496␉// 0670 - 067F␊
497␉// 0680 - 068F␊
498␉// 0690 - 069F␊
499␉// 06A0 - 06AF␊
500␉// 06B0 - 06BF␊
501␉// 06C0 - 06CF␊
502␉{ 0x10DE06C0, "GeForce GTX 480" },␊
503␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
504␉{ 0x10DE06C4, "GeForce GTX 465" },␊
505␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
506␉{ 0x10DE06CD, "GeForce GTX 470" },␊
507␉// 06D0 - 06DF␊
508␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
509␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
510␉{ 0x10DE06D2, "Tesla M2070" },␊
511␉{ 0x10DE06D8, "Quadro 6000" },␊
512␉{ 0x10DE06D9, "Quadro 5000" },␊
513␉{ 0x10DE06DA, "Quadro 5000M" },␊
514␉{ 0x10DE06DC, "Quadro 6000" },␊
515␉{ 0x10DE06DD, "Quadro 4000" },␊
516␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
517␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
518␉{ 0x10DE06DF, "Tesla M2070-Q" }, ␊
519␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
520␉// 06E0 - 06EF␉␊
521␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
522␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
523␉{ 0x10DE06E2, "GeForce 8400" },␊
524␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
525␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
526␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
527␉{ 0x10DE06E6, "GeForce G100" },␊
528␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
529␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
530␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
531␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
532␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
533␉{ 0x10DE06EC, "GeForce G 105M" },␊
534␉{ 0x10DE06EF, "GeForce G 103M" },␊
535␉// 06F0 - 06FF␉␊
536␉{ 0x10DE06F1, "GeForce G105M" }, ␊
537␉{ 0x10DE06F8, "Quadro NVS 420" },␊
538␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
539␉{ 0x10DE06FA, "Quadro NVS 450" },␊
540␉{ 0x10DE06FB, "Quadro FX 370M" },␊
541␉{ 0x10DE06FD, "Quadro NVS 295" },␊
542␉{ 0x10DE06FF, "HICx16 + Graphics" }, ␊
543␉// 0700 - 070F␊
544␉// 0710 - 071F␊
545␉// 0720 - 072F␊
546␉// 0730 - 073F␊
547␉// 0740 - 074F␊
548␉// 0750 - 075F␊
549␉// 0760 - 076F␊
550␉// 0770 - 077F␊
551␉// 0780 - 078F␊
552␉// 0790 - 079F␊
553␉// 07A0 - 07AF␊
554␉// 07B0 - 07BF␊
555␉// 07C0 - 07CF␊
556␉// 07D0 - 07DF␉␊
557␉// 07E0 - 07EF␉␉␊
558␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
559␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
560␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
561␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
562␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
563␉// 07F0 - 07FF␉␊
564␉// 0800 - 080F␊
565␉// 0810 - 081F␊
566␉// 0820 - 082F␊
567␉// 0830 - 083F␊
568␉// 0840 - 084F␊
569␉{ 0x10DE0840, "GeForce 8200M" }, ␊
570␉{ 0x10DE0844, "GeForce 9100M G" },␊
571␉{ 0x10DE0845, "GeForce 8200M G" },␊
572␉{ 0x10DE0846, "GeForce 9200" },␊
573␉{ 0x10DE0847, "GeForce 9100" },␊
574␉{ 0x10DE0848, "GeForce 8300" },␊
575␉{ 0x10DE0849, "GeForce 8200" },␊
576␉{ 0x10DE084A, "nForce 730a" },␊
577␉{ 0x10DE084B, "GeForce 9200" },␊
578␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
579␉{ 0x10DE084D, "nForce 750a SLI" },␊
580␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
581␉// 0850 - 085F␊
582␉// 0860 - 086F␉␊
583␉{ 0x10DE0860, "GeForce 9400" },␊
584␉{ 0x10DE0861, "GeForce 9400" },␊
585␉{ 0x10DE0862, "GeForce 9400M G" },␊
586␉{ 0x10DE0863, "GeForce 9400M" },␊
587␉{ 0x10DE0864, "GeForce 9300" },␊
588␉{ 0x10DE0865, "ION" },␊
589␉{ 0x10DE0866, "GeForce 9400M G" },␊
590␉{ 0x10DE0867, "GeForce 9400" },␊
591␉{ 0x10DE0868, "nForce 760i SLI" },␊
592␉{ 0x10DE0869, "GeForce 9400" }, ␊
593␉{ 0x10DE086A, "GeForce 9400" },␊
594␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
595␉{ 0x10DE086D, "GeForce 9200" },␊
596␉{ 0x10DE086E, "GeForce 9100M G" },␊
597␉{ 0x10DE086F, "GeForce 8200M G" },␊
598␉// 0870 - 087F␉␊
599␉{ 0x10DE0870, "GeForce 9400M" },␊
600␉{ 0x10DE0871, "GeForce 9200" },␊
601␉{ 0x10DE0872, "GeForce G102M" },␊
602␉{ 0x10DE0873, "GeForce G102M" },␊
603␉{ 0x10DE0874, "ION 9300M" },␉␊
604␉{ 0x10DE0876, "ION" },␊
605␉{ 0x10DE087A, "GeForce 9400" },␊
606␉{ 0x10DE087D, "ION 9400M" },␊
607␉{ 0x10DE087E, "ION LE" },␊
608␉{ 0x10DE087F, "ION LE" },␊
609␉// 0880 - 088F␊
610␉// 0890 - 089F␊
611␉// 08A0 - 08AF␊
612␉{ 0x10DE08A0, "GeForce 320M" }, ␊
613␉{ 0x10DE08A4, "GeForce 320M" }, ␊
614␉// 08B0 - 08BF␊
615␉// 08C0 - 08CF␊
616␉// 08D0 - 08DF␉␊
617␉// 08E0 - 08EF␉␉␉␊
618␉// 08F0 - 08FF␊
619␉// 0900 - 090F␊
620␉// 0910 - 091F␊
621␉// 0920 - 092F␊
622␉// 0930 - 093F␊
623␉// 0940 - 094F␊
624␉// 0950 - 095F␊
625␉// 0960 - 096F␊
626␉// 0970 - 097F␊
627␉// 0980 - 098F␊
628␉// 0990 - 099F␊
629␉// 09A0 - 09AF␊
630␉// 09B0 - 09BF␊
631␉// 09C0 - 09CF␊
632␉// 09D0 - 09DF␉␊
633␉// 09E0 - 09EF␊
634␉// 09F0 - 09FF␊
635␉// 0A00 - 0A0F␊
636␉// 0A10 - 0A1F␊
637␉// 0A20 - 0A2F␊
638␉{ 0x10DE0A20, "GeForce GT220" },␊
639␉{ 0x10DE0A22, "GeForce 315" },␊
640␉{ 0x10DE0A23, "GeForce 210" },␊
641␉{ 0x10DE0A26, "GeForce 405" }, ␊
642␉{ 0x10DE0A27, "GeForce 405" }, ␊
643␉{ 0x10DE0A28, "GeForce GT 230M" },␊
644␉{ 0x10DE0A29, "GeForce GT 330M" },␊
645␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
646␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
647␉{ 0x10DE0A2C, "NVS 5100M" },␊
648␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
649␉// 0A30 - 0A3F␉␊
650␉{ 0x10DE0A34, "GeForce GT 240M" },␊
651␉{ 0x10DE0A35, "GeForce GT 325M" },␊
652␉{ 0x10DE0A38, "Quadro 400" }, ␊
653␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
654␉// 0A40 - 0A4F␊
655␉// 0A50 - 0A5F␊
656␉// 0A60 - 0A6F␊
657␉{ 0x10DE0A60, "GeForce G210" },␊
658␉{ 0x10DE0A62, "GeForce 205" },␊
659␉{ 0x10DE0A63, "GeForce 310" },␊
660␉{ 0x10DE0A64, "ION" },␊
661␉{ 0x10DE0A65, "GeForce 210" },␊
662␉{ 0x10DE0A66, "GeForce 310" },␊
663␉{ 0x10DE0A67, "GeForce 315" },␊
664␉{ 0x10DE0A68, "GeForce G105M" },␊
665␉{ 0x10DE0A69, "GeForce G105M" },␊
666␉{ 0x10DE0A6A, "NVS 2100M" },␊
667␉{ 0x10DE0A6C, "NVS 3100M" },␊
668␉{ 0x10DE0A6E, "GeForce 305M" },␊
669␉{ 0x10DE0A6F, "ION" },␉␊
670␉// 0A70 - 0A7F␊
671␉{ 0x10DE0A70, "GeForce 310M" },␊
672␉{ 0x10DE0A71, "GeForce 305M" },␊
673␉{ 0x10DE0A72, "GeForce 310M" },␊
674␉{ 0x10DE0A73, "GeForce 305M" },␊
675␉{ 0x10DE0A74, "GeForce G210M" },␊
676␉{ 0x10DE0A75, "GeForce G310M" },␊
677␉{ 0x10DE0A76, "ION" }, ␊
678␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
679␉{ 0x10DE0A7A, "GeForce 315M" }, ␊
680␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
681␉// 0A80 - 0A8F␊
682␉// 0A90 - 0A9F␊
683␉// 0AA0 - 0AAF␊
684␉// 0AB0 - 0ABF␊
685␉// 0AC0 - 0ACF␊
686␉// 0AD0 - 0ADF␉␊
687␉// 0AE0 - 0AEF␊
688␉// 0AF0 - 0AFF␊
689␉// 0B00 - 0B0F␊
690␉// 0B10 - 0B1F␊
691␉// 0B20 - 0B2F␊
692␉// 0B30 - 0B3F␊
693␉// 0B40 - 0B4F␊
694␉// 0B50 - 0B5F␊
695␉// 0B60 - 0B6F␊
696␉// 0B70 - 0B7F␊
697␉// 0B80 - 0B8F␊
698␉// 0B90 - 0B9F␊
699␉// 0BA0 - 0BAF␊
700␉// 0BB0 - 0BBF␊
701␉// 0BC0 - 0BCF␊
702␉// 0BD0 - 0BDF␉␊
703␉// 0BE0 - 0BEF␊
704␉// 0BF0 - 0BFF␊
705␉// 0C00 - 0C0F␊
706␉// 0C10 - 0C1F␊
707␉// 0C20 - 0C2F␊
708␉// 0C30 - 0C3F␊
709␉// 0C40 - 0C4F␊
710␉// 0C50 - 0C5F␊
711␉// 0C60 - 0C6F␊
712␉// 0C70 - 0C7F␊
713␉// 0C80 - 0C8F␊
714␉// 0C90 - 0C9F␊
715␉// 0CA0 - 0CAF␊
716␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
717␉{ 0x10DE0CA2, "GeForce GT 320" },␊
718␉{ 0x10DE0CA3, "GeForce GT 240" },␊
719␉{ 0x10DE0CA4, "GeForce GT 340" },␊
720␉{ 0x10DE0CA5, "GeForce GT 220" }, ␊
721␉{ 0x10DE0CA7, "GeForce GT 330" },␊
722␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
723␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
724␉{ 0x10DE0CAC, "GeForce GT 220" }, ␊
725␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
726␉// 0CB0 - 0CBF␉␊
727␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
728␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
729␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
730␉// 0CC0 - 0CCF␊
731␉// 0CD0 - 0CDF␉␊
732␉// 0CE0 - 0CEF␊
733␉// 0CF0 - 0CFF␊
734␉// 0D00 - 0D0F␊
735␉// 0D10 - 0D1F␊
736␉// 0D20 - 0D2F␊
737␉// 0D30 - 0D3F␊
738␉// 0D40 - 0D4F␊
739␉// 0D50 - 0D5F␊
740␉// 0D60 - 0D6F␊
741␉// 0D70 - 0D7F␊
742␉// 0D80 - 0D8F␊
743␉// 0D90 - 0D9F␊
744␉// 0DA0 - 0DAF␉␊
745␉// 0DB0 - 0DBF␊
746␉// 0DC0 - 0DCF␊
747␉{ 0x10DE0DC0, "GeForce GT 440" },␊
748␉{ 0x10DE0DC1, "D12-P1-35" },␊
749␉{ 0x10DE0DC2, "D12-P1-35" },␊
750␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
751␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
752␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
753␉{ 0x10DE0DCA, "GF10x" },␊
754␉{ 0x10DE0DCD, "GeForce GT 555M" }, ␊
755␉{ 0x10DE0DCE, "GeForce GT 555M" }, ␊
756␉// 0DD0 - 0DDF␉␊
757␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
758␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
759␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
760␉{ 0x10DE0DD6, "GeForce GT 550M" }, ␊
761␉{ 0x10DE0DD8, "Quadro 2000" },␊
762␉{ 0x10DE0DDA, "Quadro 2000M" }, ␊
763␉{ 0x10DE0DDE, "GF106-ES" },␊
764␉{ 0x10DE0DDF, "GF106-INT" },␊
765␉// 0DE0 - 0DEF␉␊
766␉{ 0x10DE0DE0, "GeForce GT 440" },␊
767␉{ 0x10DE0DE1, "GeForce GT 430" },␊
768␉{ 0x10DE0DE2, "GeForce GT 420" },␊
769␉{ 0x10DE0DE5, "GeForce GT 530" },␊
770␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
771␉{ 0x10DE0DEC, "GeForce GT 525M" }, ␊
772␉{ 0x10DE0DED, "GeForce GT 520M" }, ␊
773␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
774␉// 0DF0 - 0DFF␉␊
775␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
776␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
777␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
778␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
779␉{ 0x10DE0DF4, "GeForce GT 540M" }, ␊
780␉{ 0x10DE0DF5, "GeForce GT 525M" }, ␊
781␉{ 0x10DE0DF6, "GeForce GT 550M" }, ␊
782␉{ 0x10DE0DF7, "GeForce GT 520M" }, ␊
783␉{ 0x10DE0DF8, "Quadro 600" },␊
784␉{ 0x10DE0DFA, "Quadro 1000M" }, ␊
785␉{ 0x10DE0DFE, "GF108 ES" },␊
786␉{ 0x10DE0DFF, "GF108 INT" },␊
787␉// 0E00 - 0E0F␊
788␉// 0E10 - 0E1F␊
789␉// 0E20 - 0E2F␊
790␉{ 0x10DE0E21, "D12U-25" },␊
791␉{ 0x10DE0E22, "GeForce GTX 460" },␊
792␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
793␉{ 0x10DE0E24, "GeForce GTX 460" },␊
794␉{ 0x10DE0E25, "D12U-50" },␊
795␉// 0E30 - 0E3F␉␊
796␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
797␉{ 0x10DE0E31, "GeForce GTX 485M" }, ␊
798␉{ 0x10DE0E38, "GF104GL" },␊
799␉{ 0x10DE0E3A, "Quadro 3000M" }, ␊
800␉{ 0x10DE0E3B, "Quadro 4000M" }, ␊
801␉{ 0x10DE0E3E, "GF104-ES" },␊
802␉{ 0x10DE0E3F, "GF104-INT" },␊
803␉// 0E40 - 0E4F␉␊
804␉// 0E50 - 0E5F␊
805␉// 0E60 - 0E6F␊
806␉// 0E70 - 0E7F␊
807␉// 0E80 - 0E8F␊
808␉// 0E90 - 0E9F␊
809␉// 0EA0 - 0EAF␊
810␉// 0EB0 - 0EBF␊
811␉// 0EC0 - 0ECF␊
812␉// 0ED0 - 0EDF␉␊
813␉// 0EE0 - 0EEF␊
814␉// 0EF0 - 0EFF␊
815␉// 0F00 - 0F0F␊
816␉// 0F10 - 0F1F␊
817␉// 0F20 - 0F2F␊
818␉// 0F30 - 0F3F␊
819␉// 0F40 - 0F4F␊
820␉// 0F50 - 0F5F␊
821␉// 0F60 - 0F6F␊
822␉// 0F70 - 0F7F␊
823␉// 0F80 - 0F8F␊
824␉// 0F90 - 0F9F␊
825␉// 0FA0 - 0FAF␊
826␉// 0FB0 - 0FBF␊
827␉// 0FC0 - 0FCF␊
828␉// 0FD0 - 0FDF␊
829␉// 0FE0 - 0FEF␊
830␉// 0FF0 - 0FFF␊
831␉// 1000 - 100F␊
832␉// 1010 - 101F␊
833␉// 1020 - 102F␊
834␉// 1030 - 103F␊
835␉// 1040 - 104F␊
836␉{ 0x10DE1040, "GeForce GT 520" },␊
837␉// 1050 - 105F␊
838␉{ 0x10DE1050, "GeForce GT 520M" },␊
839␉{ 0x10DE1051, "GeForce GT 520MX" },␊
840␉{ 0x10DE1054, "GeForce GT 410M" }, ␊
841␉{ 0x10DE1056, "NVS 4200M" }, ␊
842␉{ 0x10DE1057, "NVS 4200M" }, ␊
843␉// 1060 - 106F␊
844␉// 1070 - 107F␊
845␉{ 0x10DE107F, "NVIDIA GF119-ES" }, ␊
846␉// 1080 - 108F␊
847␉{ 0x10DE1080, "GeForce GTX 580" },␊
848␉{ 0x10DE1081, "GeForce GTX 570" },␊
849␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
850␉{ 0x10DE1083, "D13U" },␊
851␉{ 0x10DE1084, "GeForce GTX 560" }, ␊
852␉{ 0x10DE1086, "GeForce GTX 570" }, ␊
853␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" }, ␊
854␉{ 0x10DE1088, "GeForce GTX 590" },␊
855␉{ 0x10DE1089, "GeForce GTX 580" }, ␊
856␉{ 0x10DE108B, "GeForce GTX 590" }, ␊
857␉// 1090 - 109F␉␊
858␉{ 0x10DE1091, "Tesla M2090" }, ␊
859␉{ 0x10DE1098, "D13U" },␊
860␉{ 0x10DE109A, "Quadro 5010M" }, ␊
861␉{ 0x10DE109B, "Quadro 7000" }, ␊
862␉// 10A0 - 10AF␊
863␉// 10B0 - 10BF␊
864␉// 10C0 - 10CF␊
865␉{ 0x10DE10C0, "GeForce 9300 GS" }, ␊
866␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
867␉{ 0x10DE10C5, "GeForce 405" }, ␊
868␉// 10D0 - 10DF␊
869␉{ 0x10DE10D8, "NVS 300" }, ␊
870␉// 1200 - ␊
871␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
872␉{ 0x10DE1201, "GeForce GTX 560" }, ␊
873␉{ 0x10DE1241, "GeForce GT 545" }, ␊
874␉{ 0x10DE1243, "GeForce GT 545" }, ␊
875␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
876␉{ 0x10DE1245, "GeForce GTS 450" },␊
877␉{ 0x10DE1251, "GeForce GTX 560M" }, ␊
878};␊
879␊
880␊
881␊
882static int patch_nvidia_rom(uint8_t *rom)␊
883{␊
884␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
885␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
886␉␉return PATCH_ROM_FAILED;␊
887␉}␊
888␉␊
889␉uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);␊
890␊
891␉if (!dcbptr) {␊
892␉␉printf("no dcb table found\n");␊
893␉␉return PATCH_ROM_FAILED;␊
894␉}␊
895//␉else␊
896//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
897␉ ␊
898␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
899␉uint8_t dcbtable_version = dcbtable[0];␊
900␉uint8_t headerlength␉ = 0;␊
901␉uint8_t numentries␉␉ = 0;␊
902␉uint8_t recordlength␉ = 0;␊
903␉␊
904␉if (dcbtable_version >= 0x20)␊
905␉{␊
906␉␉uint32_t sig;␊
907␉␉␊
908␉␉if (dcbtable_version >= 0x30)␊
909␉␉{␊
910␉␉␉headerlength = dcbtable[1];␊
911␉␉␉numentries␉ = dcbtable[2];␊
912␉␉␉recordlength = dcbtable[3];␊
913␊
914␉␉␉sig = READ_LE_INT(dcbtable, 6);␊
915␉␉}␊
916␉␉else␊
917␉␉{␊
918␉␉␉sig = READ_LE_INT(dcbtable, 4);␊
919␉␉␉headerlength = 8;␊
920␉␉}␊
921␉␉␊
922␉␉if (sig != 0x4edcbdcb)␊
923␉␉{␊
924␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
925␉␉␉return PATCH_ROM_FAILED;␊
926␉␉}␊
927␉}␊
928␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
929␉{␊
930␉␉char sig[8] = { 0 };␊
931␉␉␊
932␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
933␉␉recordlength = 10;␊
934␉␉␊
935␉␉if (strcmp(sig, "DEV_REC"))␊
936␉␉{␊
937␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
938␉␉␉return PATCH_ROM_FAILED;␊
939␉␉}␊
940␉}␊
941␉else␊
942␉{␊
943␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
944␉␉return PATCH_ROM_FAILED;␊
945␉}␊
946␉␊
947␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
948␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
949␉␊
950␉uint8_t num_outputs = 0, i = 0;␊
951␉␊
952␉struct dcbentry␊
953␉{␊
954␉␉uint8_t type;␊
955␉␉uint8_t index;␊
956␉␉uint8_t *heads;␊
957␉} entries[numentries];␊
958␉␊
959␉for (i = 0; i < numentries; i++)␊
960␉{␊
961␉␉uint32_t connection;␊
962␉␉connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);␊
963␊
964␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
965␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
966␉␉␉continue;␊
967␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
968␉␉␉continue;␊
969␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
970␉␉␉continue;␊
971␉␉␊
972␉␉entries[num_outputs].type = connection & 0xf;␊
973␉␉entries[num_outputs].index = num_outputs;␊
974␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
975␉}␊
976␉␊
977␉int has_lvds = false;␊
978␉uint8_t channel1 = 0, channel2 = 0;␊
979␉␊
980␉for (i = 0; i < num_outputs; i++)␊
981␉{␊
982␉␉if (entries[i].type == 3)␊
983␉␉{␊
984␉␉␉has_lvds = true;␊
985␉␉␉//printf("found LVDS\n");␊
986␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
987␉␉␉entries[i].type = TYPE_GROUPED;␊
988␉␉}␊
989␉}␊
990␉␊
991␉// if we have a LVDS output, we group the rest to the second channel␊
992␉if (has_lvds)␊
993␉{␊
994␉␉for (i = 0; i < num_outputs; i++)␊
995␉␉{␊
996␉␉␉if (entries[i].type == TYPE_GROUPED)␊
997␉␉␉␉continue;␊
998␉␉␉␊
999␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1000␉␉␉entries[i].type = TYPE_GROUPED;␊
1001␉␉}␊
1002␉}␊
1003␉else␊
1004␉{␊
1005␉␉int x;␊
1006␉␉// we loop twice as we need to generate two channels␊
1007␉␉for (x = 0; x <= 1; x++)␊
1008␉␉{␊
1009␉␉␉for (i=0; i<num_outputs; i++)␊
1010␉␉␉{␊
1011␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1012␉␉␉␉␉continue;␊
1013␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1014␉␉␉␉// we always group ANALOG and TMDS␊
1015␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1016␉␉␉␉if (i && entries[i].type == 0x2)␊
1017␉␉␉␉{␊
1018␉␉␉␉␉switch (x)␊
1019␉␉␉␉␉{␊
1020␉␉␉␉␉␉case 0:␊
1021␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1022␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1023␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1024␉␉␉␉␉␉␉␊
1025␉␉␉␉␉␉␉if ( entries[i-1].type == 0x0 )␊
1026␉␉␉␉␉␉␉{␊
1027␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1028␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1029␉␉␉␉␉␉␉}␊
1030␉␉␉␉␉␉␉// group TV as well if there is one␊
1031␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1032␉␉␉␉␉␉␉{␊
1033␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1034␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1035␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1036␉␉␉␉␉␉␉}␊
1037␉␉␉␉␉␉␉break;␊
1038␉␉␉␉␉␉␊
1039␉␉␉␉␉␉case 1:␊
1040␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1041␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1042␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1043␉␉␉␉␉␉␉␊
1044␉␉␉␉␉␉␉if ( entries[i - 1].type == 0x0 )␊
1045␉␉␉␉␉␉␉{␊
1046␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1047␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1048␉␉␉␉␉␉␉}␊
1049␉␉␉␉␉␉␉// group TV as well if there is one␊
1050␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1051␉␉␉␉␉␉␉{␊
1052␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1053␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1054␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1055␉␉␉␉␉␉␉}␊
1056␉␉␉␉␉␉␉break;␊
1057␉␉␉␉␉}␊
1058␉␉␉␉␉break;␊
1059␉␉␉␉}␊
1060␉␉␉}␊
1061␉␉}␊
1062␉}␊
1063␉␊
1064␉// if we have left ungrouped outputs merge them to the empty channel␊
1065␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1066␉togroup = &channel2;␊
1067␉␊
1068␉for (i = 0; i < num_outputs; i++)␊
1069␉{␊
1070␉␉if (entries[i].type != TYPE_GROUPED)␊
1071␉␉{␊
1072␉␉␉//printf("%d not grouped\n", i);␊
1073␉␉␉if (togroup)␊
1074␉␉␉{␊
1075␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1076␉␉␉}␊
1077␉␉␉entries[i].type = TYPE_GROUPED;␊
1078␉␉}␊
1079␉}␊
1080␉␊
1081␉if (channel1 > channel2)␊
1082␉{␊
1083␉␉uint8_t buff = channel1;␊
1084␉␉channel1 = channel2;␊
1085␉␉channel2 = buff;␊
1086␉}␊
1087␉␊
1088␉default_NVCAP[6] = channel1;␊
1089␉default_NVCAP[8] = channel2;␊
1090␉␊
1091␉// patching HEADS␊
1092␉for (i = 0; i < num_outputs; i++)␊
1093␉{␊
1094␉␉if (channel1 & (1 << i))␊
1095␉␉{␊
1096␉␉␉*entries[i].heads = 1;␊
1097␉␉}␊
1098␉␉else if(channel2 & (1 << i))␊
1099␉␉{␊
1100␉␉␉*entries[i].heads = 2;␊
1101␉␉}␊
1102␉}␊
1103␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1104}␊
1105␊
1106static char *get_nvidia_model(uint32_t id)␊
1107{␊
1108␉int i;␊
1109␉␊
1110␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1111␉␉if (NVKnownChipsets[i].device == id)␊
1112␉␉{␊
1113␉␉␉return NVKnownChipsets[i].name;␊
1114␉␉}␊
1115␉}␊
1116␉return NVKnownChipsets[0].name;␊
1117}␊
1118␊
1119static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1120{␊
1121␉int fd;␊
1122␉int size;␊
1123␉␊
1124␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1125␉{␊
1126␉␉return 0;␊
1127␉}␊
1128␉␊
1129␉size = file_size(fd);␊
1130␉␊
1131␉if (size > bufsize)␊
1132␉{␊
1133␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1134␉␉␉␉filename, bufsize);␊
1135␉␉size = bufsize;␊
1136␉}␊
1137␉size = read(fd, (char *)buf, size);␊
1138␉close(fd);␊
1139␉␊
1140␉return size > 0 ? size : 0;␊
1141}␊
1142␊
1143␊
1144static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1145{␊
1146␉char tmp[16];␊
1147␉␊
1148␉if (!device)␊
1149␉␉return 0;␊
1150␉␊
1151␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1152␉␉return 0;␊
1153␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1154␉␉return 0;␊
1155␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1156␉␉return 0;␊
1157␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1158␉␉return 0;␊
1159␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1160␉␉return 0;␊
1161␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1162␉␉return 0;␊
1163␉if (devices_number == 1)␊
1164␉{␊
1165␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1166␉␉ return 0;␊
1167␉}␊
1168␉else␊
1169␉{␊
1170␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1171␉␉ return 0;␊
1172␉}␊
1173␉␊
1174␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1175␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1176␉sprintf(tmp, "Slot-%x",devices_number);␊
1177␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1178␉devices_number++;␊
1179␉␊
1180␉return 1;␊
1181}␊
1182␊
1183int hex2bin(const char *hex, uint8_t *bin, int len)␊
1184{␊
1185␉char␉*p;␊
1186␉int␉␉i;␊
1187␉char␉buf[3];␊
1188␉␊
1189␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1190␉␉printf("[ERROR] bin2hex input error\n");␊
1191␉␉return -1;␊
1192␉}␊
1193␉␊
1194␉buf[2] = '\0';␊
1195␉p = (char *) hex;␊
1196␉␊
1197␉for (i = 0; i < len; i++)␊
1198␉{␊
1199␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1200␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1201␉␉␉return -2;␊
1202␉␉}␊
1203␉␉buf[0] = *p++;␊
1204␉␉buf[1] = *p++;␊
1205␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1206␉}␊
1207␉return 0;␊
1208}␊
1209␊
1210unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1211{␊
1212␉unsigned long long vram_size = 0;␊
1213␉␊
1214␉if (nvCardType < NV_ARCH_50)␊
1215␉{␊
1216␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1217␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1218␉}␊
1219␉else if (nvCardType < NV_ARCH_C0)␊
1220␉{␊
1221␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1222␉␉vram_size |= (vram_size & 0xff) << 32;␊
1223␉␉vram_size &= 0xffffffff00ll;␊
1224␉}␊
1225␉else // >= NV_ARCH_C0␊
1226␉{␊
1227␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1228␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1229␉}␊
1230␉␊
1231␉// Workaround for 9600M GT, GT 420/430/440 & GT 525M␊
1232␉switch (nvda_dev->device_id)␊
1233␉{␊
1234 // 9600M GT␊
1235␉␉case 0x0649:␊
1236 case 0x0647:␊
1237 vram_size = 512*1024*1024;␊
1238 break;␊
1239␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1240␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1241␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1242␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1243␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1244␉␉default: break;␊
1245␉}␊
1246␉␊
1247␉return vram_size;␊
1248}␊
1249␊
1250static bool checkNvRomSig(uint8_t * aRom){␊
1251 return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊
1252}␊
1253␊
1254bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1255{␊
1256␉struct DevPropDevice␉*device;␊
1257␉char␉␉␉␉␉*devicepath;␊
1258␉option_rom_pci_header_t *rom_pci_header;␊
1259␉volatile uint8_t␉␉*regs;␊
1260␉uint8_t␉␉␉␉␉*rom;␊
1261␉uint8_t␉␉␉␉␉*nvRom;␊
1262␉uint8_t␉␉␉␉␉nvCardType;␊
1263␉unsigned long long␉␉videoRam;␊
1264␉uint32_t␉␉␉␉nvBiosOveride;␊
1265␉uint32_t␉␉␉␉bar[7];␊
1266␉uint32_t␉␉␉␉boot_display;␊
1267␉int␉␉␉␉␉␉nvPatch;␊
1268␉int␉␉␉␉␉␉len;␊
1269␉char␉␉␉␉␉biosVersion[32];␊
1270␉char␉␉␉␉␉nvFilename[32];␊
1271␉char␉␉␉␉␉kNVCAP[12];␊
1272␉char␉␉␉␉␉*model;␊
1273␉const char␉␉␉␉*value;␊
1274␉bool␉␉␉␉␉doit;␊
1275␉␊
1276␉devicepath = get_pci_dev_path(nvda_dev);␊
1277␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1278␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1279␉␊
1280␉// get card type␊
1281␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1282␉␊
1283␉// Amount of VRAM in kilobytes␊
1284␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1285␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1286␉␊
1287 verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s device number: %d\n",␊
1288 model, (uint32_t)(videoRam / 1024 / 1024),␊
1289 (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1290 ␉␉␉devicepath, devices_number);␊
1291␉␊
1292␉rom = malloc(NVIDIA_ROM_SIZE);␊
1293␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1294␉␉␉(uint16_t)nvda_dev->device_id);␊
1295␉␊
1296␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1297␉{␊
1298␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1299␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1300␉␉␊
1301␉␉if (nvBiosOveride > 0)␊
1302␉␉{␊
1303␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1304␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1305␉␉}␊
1306␉␉else␊
1307␉␉{␊
1308␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1309␉␉␉return false;␊
1310␉␉}␊
1311␉}␊
1312␉else␊
1313␉{␊
1314␉␉// Otherwise read bios from card␊
1315␉␉nvBiosOveride = 0;␊
1316␉␉␊
1317 // PROM first␊
1318 // Enable PROM access␊
1319 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1320 nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1321 ␊
1322 // Valid Signature ?␊
1323␉␉if (checkNvRomSig(nvRom))␊
1324␉␉{␊
1325 bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1326 DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1327 }␊
1328 else␊
1329 {␊
1330␊
1331 // disable PROM access␊
1332 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1333 ␊
1334␉␉ //PRAM next␊
1335 nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1336 ␊
1337 if(checkNvRomSig(nvRom))␊
1338 {␊
1339 bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1340 DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1341 }␊
1342 else␊
1343 ␉␉{␊
1344␉␉␉␉// 0xC0000 last␊
1345␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1346␉␉␉␉␊
1347␉␉␉␉// Valid Signature ?␊
1348␉␉␉␉if (!checkNvRomSig(rom))␊
1349␉␉␉␉{␊
1350␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1351␉␉␉␉␉return false;␊
1352␉␉␉␉}␊
1353 else␊
1354 {␊
1355 DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1356 }␊
1357 ␊
1358␉␉␉}//end PRAM check␊
1359 ␊
1360 }//end PROM check␊
1361 ␊
1362␉}//end load rom from bios␊
1363␉␊
1364␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1365␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1366␉␉//return false;␊
1367␉}␊
1368␉␊
1369␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1370␉␊
1371␉// check for 'PCIR' sig␊
1372␉if (rom_pci_header->signature == 0x50434952)␊
1373␉{␊
1374␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1375␉␉{␊
1376␉␉␉// Get Model from the OpROM␊
1377␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1378␉␉}␊
1379␉␉else␊
1380␉␉{␊
1381␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1382␉␉}␊
1383␉}␊
1384␉␊
1385␉if (!string) {␊
1386␉␉string = devprop_create_string();␊
1387␉}␊
1388␉device = devprop_add_device(string, devicepath);␊
1389␉␊
1390␉/* FIXME: for primary graphics card only */␊
1391␉boot_display = 1;␊
1392␉if (devices_number == 1)␊
1393␉{␊
1394␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1395␉}␊
1396␉␊
1397␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1398␉␉uint8_t built_in = 0x01;␊
1399␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1400␉}␊
1401␊
1402␉// get bios version␊
1403␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1404␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1405␉␊
1406␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1407␉␊
1408␉int i, version_start;␊
1409␉int crlf_count = 0;␊
1410␉␊
1411␉// only search the first 384 bytes␊
1412␉for (i = 0; i < 0x180; i++)␊
1413␉{␊
1414␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1415␉␉{␊
1416␉␉␉crlf_count++;␊
1417␉␉␉// second 0x0D0A was found, extract bios version␊
1418␉␉␉if (crlf_count == 2)␊
1419␉␉␉{␊
1420␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1421␉␉␉␉␊
1422␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1423␉␉␉␉{␊
1424␉␉␉␉␉// find start␊
1425␉␉␉␉␉if (rom[version_start] == 0x00)␊
1426␉␉␉␉␉{␊
1427␉␉␉␉␉␉version_start++;␊
1428␉␉␉␉␉␉␊
1429␉␉␉␉␉␉// strip "Version "␊
1430␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1431␉␉␉␉␉␉{␊
1432␉␉␉␉␉␉␉version_start += 8;␊
1433␉␉␉␉␉␉}␊
1434␉␉␉␉␉␉␊
1435␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1436␉␉␉␉␉␉break;␊
1437␉␉␉␉␉}␊
1438␉␉␉␉}␊
1439␉␉␉␉break;␊
1440␉␉␉}␊
1441␉␉}␊
1442␉}␊
1443␉␊
1444␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1445␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1446␉␊
1447␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1448␉{␊
1449␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1450␉␉␊
1451␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1452␉␉{␊
1453␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1454␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1455␉␉}␊
1456␉}␊
1457␉␊
1458␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1459␉{␊
1460␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1461␉␉␊
1462␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1463␉␉{␊
1464␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1465␉␉␉␊
1466␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1467␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1468␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1469␉␉}␊
1470␉}␊
1471␉␊
1472␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1473␉{␊
1474␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1475␉␉␊
1476␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1477␉␉{␊
1478␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1479␉␉␉␊
1480␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1481␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1482␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1483␉␉}␊
1484␉}␊
1485␉␊
1486#if DEBUG_NVCAP␊
1487␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1488␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1489␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1490␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1491␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1492␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1493#endif␊
1494␉␊
1495␉devprop_add_nvidia_template(device);␊
1496␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1497␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1498␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1499␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1500␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1501␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1502␉␊
1503␉//add HDMI Audio back to nvidia␊
1504␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1505//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1506//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1507␉//end Nvidia HDMI Audio␊
1508␉␊
1509␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1510␉{␊
1511␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1512␉}␊
1513␉␊
1514␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1515␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1516␉stringlength = string->length;␊
1517␉␊
1518␉return true;␊
1519}␊
1520

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