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Root/trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊
75#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊
76#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊
77#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊
78#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊
79␊
80extern uint32_t devices_number;␊
81␊
82const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
83const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
84const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
85const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
86const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
87const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
88const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
89const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
90const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
91␊
92static uint8_t default_NVCAP[]= {␊
93␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
94␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
95␉0x00, 0x00, 0x00, 0x00␊
96};␊
97␊
98#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
99␊
100static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
101static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
102␊
103#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
104#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
105␊
106static uint8_t default_NVPM[]= {␊
107 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
109 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
110 0x00, 0x00, 0x00, 0x00␊
111};␊
112␊
113#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊
114␊
115static struct nv_chipsets_t NVKnownChipsets[] = {␊
116␉{ 0x00000000, "Unknown" },␊
117//========================================␊
118␉// 0040 - 004F␉␊
119␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
120␉{ 0x10DE0041, "GeForce 6800" },␊
121␉{ 0x10DE0042, "GeForce 6800 LE" },␊
122␉{ 0x10DE0043, "GeForce 6800 XE" },␊
123␉{ 0x10DE0044, "GeForce 6800 XT" },␊
124␉{ 0x10DE0045, "GeForce 6800 GT" },␊
125␉{ 0x10DE0046, "GeForce 6800 GT" },␊
126␉{ 0x10DE0047, "GeForce 6800 GS" },␊
127␉{ 0x10DE0048, "GeForce 6800 XT" },␊
128␉{ 0x10DE004D, "Quadro FX 3400" },␊
129␉{ 0x10DE004E, "Quadro FX 4000" },␊
130␉// 0050 - 005F␊
131␉// 0060 - 006F␉␊
132␉// 0070 - 007F␉␊
133␉// 0080 - 008F␉␊
134␉// 0090 - 009F␉␊
135␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
136␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
137␉{ 0x10DE0092, "GeForce 7800 GT" },␊
138␉{ 0x10DE0093, "GeForce 7800 GS" },␊
139␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
140␉{ 0x10DE0098, "GeForce Go 7800" },␊
141␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
142␉{ 0x10DE009D, "Quadro FX 4500" },␊
143␉// 00A0 - 00AF␉␊
144␉// 00B0 - 00BF␉␊
145␉// 00C0 - 00CF␉␊
146␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
147␉{ 0x10DE00C1, "GeForce 6800" },␊
148␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
149␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
150␉{ 0x10DE00C8, "GeForce Go 6800" },␊
151␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
152␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
153␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
154␉{ 0x10DE00CE, "Quadro FX 1400" },␊
155␉// 00D0 - 00DF␉␊
156␉// 00E0 - 00EF␉␊
157␉// 00F0 - 00FF␉␊
158␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
159␉{ 0x10DE00F2, "GeForce 6600" },␊
160␉{ 0x10DE00F3, "GeForce 6200" },␊
161␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
162␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
163␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
164␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
165␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
166␉// 0100 - 010F␉␊
167␉// 0110 - 011F␉␊
168␉// 0120 - 012F␉␊
169␉// 0130 - 013F␉␊
170␉// 0140 - 014F␉␊
171␉{ 0x10DE0140, "GeForce 6600 GT" },␊
172␉{ 0x10DE0141, "GeForce 6600" },␊
173␉{ 0x10DE0142, "GeForce 6600 LE" },␊
174␉{ 0x10DE0143, "GeForce 6600 VE" },␊
175␉{ 0x10DE0144, "GeForce Go 6600" },␊
176␉{ 0x10DE0145, "GeForce 6610 XL" },␊
177␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
178␉{ 0x10DE0147, "GeForce 6700 XL" },␊
179␉{ 0x10DE0148, "GeForce Go 6600" },␊
180␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
181␉{ 0x10DE014A, "Quadro NVS 440" },␊
182␉{ 0x10DE014C, "Quadro FX 550" },␊
183␉{ 0x10DE014D, "Quadro FX 550" },␊
184␉{ 0x10DE014E, "Quadro FX 540" },␊
185␉{ 0x10DE014F, "GeForce 6200" },␊
186␉// 0150 - 015F␉␊
187␉// 0160 - 016F␉␊
188␉{ 0x10DE0160, "GeForce 6500" },␊
189␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
190␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
191␉{ 0x10DE0163, "GeForce 6200 LE" },␊
192␉{ 0x10DE0164, "GeForce Go 6200" },␊
193␉{ 0x10DE0165, "Quadro NVS 285" },␊
194␉{ 0x10DE0166, "GeForce Go 6400" },␊
195␉{ 0x10DE0167, "GeForce Go 6200" },␊
196␉{ 0x10DE0168, "GeForce Go 6400" },␊
197␉{ 0x10DE0169, "GeForce 6250" },␊
198␉{ 0x10DE016A, "GeForce 7100 GS" },␊
199␉// 0170 - 017F␉␊
200␉// 0180 - 018F␉␊
201␉// 0190 - 019F␉␉␊
202␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
203␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
204␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
205␉{ 0x10DE0197, "Tesla C870" },␊
206␉{ 0x10DE019D, "Quadro FX 5600" },␊
207␉{ 0x10DE019E, "Quadro FX 4600" },␊
208␉// 01A0 - 01AF␉␊
209␉// 01B0 - 01BF␉␊
210␉// 01C0 - 01CF␉␊
211␉// 01D0 - 01DF␉␉␊
212␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
213␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
214␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
215␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
216␉{ 0x10DE01D6, "GeForce Go 7200" },␊
217␉{ 0x10DE01D7, "GeForce Go 7300" },␊
218␉{ 0x10DE01D8, "GeForce Go 7400" },␊
219␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
220␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
221␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
222␉{ 0x10DE01DC, "Quadro FX 350M" },␊
223␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
224␉{ 0x10DE01DE, "Quadro FX 350" },␊
225␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
226␉// 01E0 - 01EF␉␊
227␉// 01F0 - 01FF␊
228 { 0x10DE01F0,␉"GeForce4 MX" },␊
229␉// 0200 - 020F␉␊
230␉// 0210 - 021F␉␊
231␉{ 0x10DE0211, "GeForce 6800" },␊
232␉{ 0x10DE0212, "GeForce 6800 LE" },␊
233␉{ 0x10DE0215, "GeForce 6800 GT" },␊
234␉{ 0x10DE0218, "GeForce 6800 XT" },␊
235␉// 0220 - 022F␉␊
236␉{ 0x10DE0221, "GeForce 6200" },␊
237␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
238 { 0x10DE0228,␉"NVIDIA NV44M" },␊
239␉// 0230 - 023F␉␊
240␉// 0240 - 024F␉␊
241␉{ 0x10DE0240, "GeForce 6150" },␊
242␉{ 0x10DE0241, "GeForce 6150 LE" },␊
243␉{ 0x10DE0242, "GeForce 6100" },␊
244 ␉{ 0x10DE0243,␉"NVIDIA C51" },␊
245␉{ 0x10DE0244, "GeForce Go 6150" },␊
246␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
247␉{ 0x10DE0247, "GeForce Go 6100" },␊
248␉// 0250 - 025F␉␊
249␉// 0260 - 026F␉␊
250␉// 0270 - 027F␉␊
251␉// 0280 - 028F␉␉␊
252␉// 0290 - 029F␉␊
253␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
254␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
255␉{ 0x10DE0292, "GeForce 7900 GS" },␊
256␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
257␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
258␉{ 0x10DE0295, "GeForce 7950 GT" },␊
259␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
260␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
261␉{ 0x10DE029A, "Quadro FX 2500M" },␊
262␉{ 0x10DE029B, "Quadro FX 1500M" },␊
263␉{ 0x10DE029C, "Quadro FX 5500" },␊
264␉{ 0x10DE029D, "Quadro FX 3500" },␊
265␉{ 0x10DE029E, "Quadro FX 1500" },␊
266␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
267␉// 02A0 - 02AF␉␊
268␉// 02B0 - 02BF␉␊
269␉// 02C0 - 02CF␉␊
270␉// 02D0 - 02DF␉␉␊
271␉// 02E0 - 02EF␉␉␊
272␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
273␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
274␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
275␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
276␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
277␉// 02F0 - 02FF␉␉␊
278␉// 0300 - 030F␉␉␊
279␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
280␉{ 0x10DE0302, "GeForce FX 5800" },␊
281␉{ 0x10DE0308, "Quadro FX 2000" },␊
282␉{ 0x10DE0309, "Quadro FX 1000" },␊
283␉// 0310 - 031F␉␉␊
284␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
285␉{ 0x10DE0312, "GeForce FX 5600" },␊
286␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
287␉{ 0x10DE031A, "GeForce FX Go5600" },␊
288␉{ 0x10DE031B, "GeForce FX Go5650" },␊
289␉{ 0x10DE031C, "Quadro FX Go700" },␊
290␉// 0320 - 032F␊
291 { 0x10DE0320, "GeForce FX 5200" },␊
292␉{ 0x10DE0321, "GeForce FX 5200 Ultra" },␊
293␉{ 0x10DE0322, "GeForce FX 5200" },␊
294␉{ 0x10DE0323, "GeForce FX 5200 LE" },␊
295␉{ 0x10DE0324, "GeForce FX Go5200" },␊
296␉{ 0x10DE0325, "GeForce FX Go5250" },␊
297␉{ 0x10DE0326, "GeForce FX 5500" },␊
298␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
299 ␉{ 0x10DE0329, "GeForce FX Go5200" },␊
300␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
301␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
302␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
303␉{ 0x10DE032D, "GeForce FX Go5100" },␊
304␉// 0330 - 033F␊
305␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
306␉{ 0x10DE0331, "GeForce FX 5900" },␊
307␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
308␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
309␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
310␉{ 0x10DE0338, "Quadro FX 3000" },␊
311␉{ 0x10DE033F, "Quadro FX 700" },␊
312␉// 0340 - 034F␊
313␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
314␉{ 0x10DE0342, "GeForce FX 5700" },␊
315␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
316␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
317␉{ 0x10DE0347, "GeForce FX Go5700" },␊
318␉{ 0x10DE0348, "GeForce FX Go5700" },␊
319␉{ 0x10DE034C, "Quadro FX Go1000" },␊
320␉{ 0x10DE034E, "Quadro FX 1100" },␊
321␉// 0350 - 035F␉␊
322␉// 0360 - 036F␉␊
323␉// 0370 - 037F␉␊
324␉// 0380 - 038F␉␉␉␊
325␉{ 0x10DE038B, "GeForce 7650 GS" },␊
326␉// 0390 - 039F␊
327␉{ 0x10DE0390, "GeForce 7650 GS" },␊
328␉{ 0x10DE0391, "GeForce 7600 GT" },␊
329␉{ 0x10DE0392, "GeForce 7600 GS" },␊
330␉{ 0x10DE0393, "GeForce 7300 GT" },␊
331␉{ 0x10DE0394, "GeForce 7600 LE" },␊
332␉{ 0x10DE0395, "GeForce 7300 GT" },␊
333␉{ 0x10DE0397, "GeForce Go 7700" },␊
334␉{ 0x10DE0398, "GeForce Go 7600" },␊
335␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
336␉{ 0x10DE039A, "Quadro NVS 300M" },␊
337␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
338␉{ 0x10DE039C, "Quadro FX 550M" },␊
339␉{ 0x10DE039E, "Quadro FX 560" },␊
340␉// 03A0 - 03AF␉␊
341␉// 03B0 - 03BF␉␊
342␉// 03C0 - 03CF␉␊
343␉// 03D0 - 03DF␉␉␉␊
344␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
345␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
346␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
347␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
348␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
349␉// 03E0 - 03EF␊
350␉// 03F0 - 03FF␊
351␉// 0400 - 040F␉␉␊
352␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
353␉{ 0x10DE0401, "GeForce 8600 GT" },␊
354␉{ 0x10DE0402, "GeForce 8600 GT" },␊
355␉{ 0x10DE0403, "GeForce 8600 GS" },␊
356␉{ 0x10DE0404, "GeForce 8400 GS" },␊
357␉{ 0x10DE0405, "GeForce 9500M GS" },␊
358␉{ 0x10DE0406, "GeForce 8300 GS" },␊
359␉{ 0x10DE0407, "GeForce 8600M GT" },␊
360␉{ 0x10DE0408, "GeForce 9650M GS" },␊
361␉{ 0x10DE0409, "GeForce 8700M GT" },␊
362␉{ 0x10DE040A, "Quadro FX 370" },␊
363␉{ 0x10DE040B, "Quadro NVS 320M" },␊
364␉{ 0x10DE040C, "Quadro FX 570M" },␊
365␉{ 0x10DE040D, "Quadro FX 1600M" },␊
366␉{ 0x10DE040E, "Quadro FX 570" },␊
367␉{ 0x10DE040F, "Quadro FX 1700" },␊
368␉// 0410 - 041F␉␊
369␉{ 0x10DE0410, "GeForce GT 330" },␊
370␉// 0420 - 042F␉␊
371␉{ 0x10DE0420, "GeForce 8400 SE" },␊
372␉{ 0x10DE0421, "GeForce 8500 GT" },␊
373␉{ 0x10DE0422, "GeForce 8400 GS" },␊
374␉{ 0x10DE0423, "GeForce 8300 GS" },␊
375␉{ 0x10DE0424, "GeForce 8400 GS" },␊
376␉{ 0x10DE0425, "GeForce 8600M GS" },␊
377␉{ 0x10DE0426, "GeForce 8400M GT" },␊
378␉{ 0x10DE0427, "GeForce 8400M GS" },␊
379␉{ 0x10DE0428, "GeForce 8400M G" },␊
380␉{ 0x10DE0429, "Quadro NVS 140M" },␊
381␉{ 0x10DE042A, "Quadro NVS 130M" },␊
382␉{ 0x10DE042B, "Quadro NVS 135M" },␊
383␉{ 0x10DE042C, "GeForce 9400 GT" },␊
384␉{ 0x10DE042D, "Quadro FX 360M" },␊
385␉{ 0x10DE042E, "GeForce 9300M G" },␊
386␉{ 0x10DE042F, "Quadro NVS 290" },␊
387␉// 0430 - 043F␊
388␉// 0440 - 044F␊
389␉// 0450 - 045F␊
390␉// 0460 - 046F␊
391␉// 0470 - 047F␊
392␉// 0480 - 048F␊
393␉// 0490 - 049F␊
394␉// 04A0 - 04AF␊
395␉// 04B0 - 04BF␊
396␉// 04C0 - 04CF␊
397 { 0x10DE04C0,␉"NVIDIA G78" },␊
398␉{ 0x10DE04C1,␉"NVIDIA G78" },␊
399␉{ 0x10DE04C2,␉"NVIDIA G78" },␊
400␉{ 0x10DE04C3,␉"NVIDIA G78" },␊
401␉{ 0x10DE04C4,␉"NVIDIA G78" },␊
402␉{ 0x10DE04C5,␉"NVIDIA G78" },␊
403␉{ 0x10DE04C6,␉"NVIDIA G78" },␊
404␉{ 0x10DE04C7,␉"NVIDIA G78" },␊
405␉{ 0x10DE04C8,␉"NVIDIA G78" },␊
406␉{ 0x10DE04C9,␉"NVIDIA G78" },␊
407␉{ 0x10DE04CA,␉"NVIDIA G78" },␊
408␉{ 0x10DE04CB,␉"NVIDIA G78" },␊
409␉{ 0x10DE04CC,␉"NVIDIA G78" },␊
410␉{ 0x10DE04CD,␉"NVIDIA G78" },␊
411␉{ 0x10DE04CE,␉"NVIDIA G78" },␊
412␉{ 0x10DE04CF,␉"NVIDIA G78" },␊
413␉// 04D0 - 04DF␊
414␉// 04E0 - 04EF␊
415␉// 04F0 - 04FF␊
416␉// 0500 - 050F␉␊
417␉// 0510 - 051F␉␊
418␉// 0520 - 052F␉␊
419␉// 0530 - 053F␉␊
420␉{ 0x10DE0530,␉"GeForce 7190M / nForce 650M" },␊
421␉{ 0x10DE0531,␉"GeForce 7150M / nForce 630M" },␊
422␉{ 0x10DE0533,␉"GeForce 7000M / nForce 610M" },␊
423␉{ 0x10DE053A,␉"GeForce 7050 PV / nForce 630a" },␊
424␉{ 0x10DE053B,␉"GeForce 7050 PV / nForce 630a" },␊
425␉{ 0x10DE053E,␉"GeForce 7025 / nForce 630a" },␊
426␉// 0540 - 054F␊
427␉// 0550 - 055F␊
428␉// 0560 - 056F␊
429␉// 0570 - 057F␊
430␉// 0580 - 058F␊
431␉// 0590 - 059F␊
432␉// 05A0 - 05AF␊
433␉// 05B0 - 05BF␊
434␉// 05C0 - 05CF␊
435␉// 05D0 - 05DF␊
436␉// 05E0 - 05EF␉␊
437␉{ 0x10DE05E0,␉"GeForce GTX 295" },␊
438␉{ 0x10DE05E1,␉"GeForce GTX 280" },␊
439␉{ 0x10DE05E2,␉"GeForce GTX 260" },␊
440␉{ 0x10DE05E3,␉"GeForce GTX 285" },␊
441␉{ 0x10DE05E4,␉"NVIDIA GT200" },␊
442␉{ 0x10DE05E5,␉"NVIDIA GT200" },␊
443␉{ 0x10DE05E6,␉"GeForce GTX 275" },␊
444␉{ 0x10DE05E7,␉"Tesla C1060" },␊
445␉{ 0x10DE05E8,␉"NVIDIA GT200" },␊
446␉{ 0x10DE05E9,␉"NVIDIA GT200" },␊
447␉{ 0x10DE05EA,␉"GeForce GTX 260" },␊
448␉{ 0x10DE05EB,␉"GeForce GTX 295" },␊
449␉{ 0x10DE05EC,␉"NVIDIA GT200" },␊
450␉{ 0x10DE05ED,␉"Quadroplex 2200 D2" },␊
451␉{ 0x10DE05EE,␉"NVIDIA GT200" },␊
452␉{ 0x10DE05EF,␉"NVIDIA GT200" },␊
453␉// 05F0 - 05FF␉␉␊
454␉{ 0x10DE05F0,␉"NVIDIA GT200" },␊
455␉{ 0x10DE05F1,␉"NVIDIA GT200" },␊
456␉{ 0x10DE05F2,␉"NVIDIA GT200" },␊
457␉{ 0x10DE05F3,␉"NVIDIA GT200" },␊
458␉{ 0x10DE05F4,␉"NVIDIA GT200" },␊
459␉{ 0x10DE05F5,␉"NVIDIA GT200" },␊
460␉{ 0x10DE05F6,␉"NVIDIA GT200" },␊
461␉{ 0x10DE05F7,␉"NVIDIA GT200" },␊
462␉{ 0x10DE05F8,␉"Quadroplex 2200 S4" },␊
463␉{ 0x10DE05F9,␉"Quadro CX" },␊
464␉{ 0x10DE05FA,␉"NVIDIA GT200" },␊
465␉{ 0x10DE05FB,␉"NVIDIA GT200" },␊
466␉{ 0x10DE05FC,␉"NVIDIA GT200" },␊
467␉{ 0x10DE05FD,␉"Quadro FX 5800" },␊
468␉{ 0x10DE05FE,␉"Quadro FX 4800" },␊
469␉{ 0x10DE05FF,␉"Quadro FX 3800" },␊
470␉// 0600 - 060F␉␊
471␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
472␉{ 0x10DE0601, "GeForce 9800 GT" },␊
473␉{ 0x10DE0602, "GeForce 8800 GT" },␊
474␉{ 0x10DE0603, "GeForce GT 230" },␊
475␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
476␉{ 0x10DE0605, "GeForce 9800 GT" },␊
477␉{ 0x10DE0606, "GeForce 8800 GS" },␊
478␉{ 0x10DE0607, "GeForce GTS 240" },␊
479␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
480␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
481␉{ 0x10DE060A, "GeForce GTX 280M" },␊
482␉{ 0x10DE060B, "GeForce 9800M GT" },␊
483␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
484␉{ 0x10DE060D, "GeForce 8800 GS" },␊
485␉{ 0x10DE060F, "GeForce GTX 285M" },␊
486␉// 0610 - 061F␉␊
487␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
488␉{ 0x10DE0611, "GeForce 8800 GT" },␊
489␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
490␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
491␉{ 0x10DE0614, "GeForce 9800 GT" },␊
492␉{ 0x10DE0615, "GeForce GTS 250" },␊
493␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
494␉{ 0x10DE0618, "GeForce GTX 260M" },␊
495␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
496␉{ 0x10DE061A, "Quadro FX 3700" },␊
497␉{ 0x10DE061B, "Quadro VX 200" },␊
498␉{ 0x10DE061C, "Quadro FX 3600M" },␊
499␉{ 0x10DE061D, "Quadro FX 2800M" },␊
500␉{ 0x10DE061E, "Quadro FX 3700M" }, ␊
501␉{ 0x10DE061F, "Quadro FX 3800M" },␊
502␉// 0620 - 062F␉␊
503␉{ 0x10DE0620,␉"NVIDIA G94" }, // GeForce 8100/8200/8300␊
504␉{ 0x10DE0621,␉"GeForce GT 230" },␊
505␉{ 0x10DE0622,␉"GeForce 9600 GT" },␊
506␉{ 0x10DE0623,␉"GeForce 9600 GS" },␊
507␉{ 0x10DE0624,␉"NVIDIA G94" },␊
508␉{ 0x10DE0625,␉"GeForce 9600 GSO 512"},␊
509␉{ 0x10DE0626,␉"GeForce GT 130" },␊
510␉{ 0x10DE0627,␉"GeForce GT 140" },␊
511␉{ 0x10DE0628,␉"GeForce 9800M GTS" },␊
512␉{ 0x10DE0629,␉"NVIDIA G94" },␊
513␉{ 0x10DE062A,␉"GeForce 9700M GTS" },␊
514␉{ 0x10DE062B,␉"GeForce 9800M GS" },␊
515␉{ 0x10DE062C,␉"GeForce 9800M GTS" },␊
516␉{ 0x10DE062D,␉"GeForce 9600 GT" },␊
517␉{ 0x10DE062E,␉"GeForce 9600 GT" },␊
518␉{ 0x10DE062F,␉"GeForce 9800 S" },␊
519␉// 0630 - 063F␉␊
520␉{ 0x10DE0630,␉"NVIDIA G94" },␊
521␉{ 0x10DE0631,␉"GeForce GTS 160M" },␊
522␉{ 0x10DE0632,␉"GeForce GTS 150M" },␊
523␉{ 0x10DE0633,␉"NVIDIA G94" },␊
524␉{ 0x10DE0634,␉"NVIDIA G94" },␊
525␉{ 0x10DE0635,␉"GeForce 9600 GSO" },␊
526␉{ 0x10DE0636,␉"NVIDIA G94" },␊
527␉{ 0x10DE0637,␉"GeForce 9600 GT" },␊
528␉{ 0x10DE0638,␉"Quadro FX 1800" },␊
529␉{ 0x10DE0639,␉"NVIDIA G94" },␊
530␉{ 0x10DE063A,␉"Quadro FX 2700M" },␊
531␉{ 0x10DE063B,␉"NVIDIA G94" },␊
532␉{ 0x10DE063C,␉"NVIDIA G94" },␊
533␉{ 0x10DE063D,␉"NVIDIA G94" },␊
534␉{ 0x10DE063E,␉"NVIDIA G94" },␊
535␉{ 0x10DE063F,␉"NVIDIA G94" },␊
536␉// 0640 - 064F␉␊
537␉{ 0x10DE0640, "GeForce 9500 GT" },␊
538␉{ 0x10DE0641, "GeForce 9400 GT" },␊
539␉{ 0x10DE0642, "GeForce 8400 GS" },␊
540␉{ 0x10DE0643, "GeForce 9500 GT" },␊
541␉{ 0x10DE0644, "GeForce 9500 GS" },␊
542␉{ 0x10DE0645, "GeForce 9500 GS" },␊
543␉{ 0x10DE0646, "GeForce GT 120" },␊
544␉{ 0x10DE0647, "GeForce 9600M GT" },␊
545␉{ 0x10DE0648, "GeForce 9600M GS" },␊
546␉{ 0x10DE0649, "GeForce 9600M GT" },␊
547␉{ 0x10DE064A, "GeForce 9700M GT" },␊
548␉{ 0x10DE064B, "GeForce 9500M G" },␊
549␉{ 0x10DE064C, "GeForce 9650M GT" },␊
550␉// 0650 - 065F␉␉␊
551␉{ 0x10DE0650,␉"NVIDIA G96-825" },␊
552␉{ 0x10DE0651,␉"GeForce G 110M" },␊
553␉{ 0x10DE0652,␉"GeForce GT 130M" },␊
554␉{ 0x10DE0653,␉"GeForce GT 120M" },␊
555␉{ 0x10DE0654,␉"GeForce GT 220M" },␊
556␉{ 0x10DE0655,␉"GeForce GT 120" },␊
557␉{ 0x10DE0656,␉"GeForce 9650 S" },␊
558␉{ 0x10DE0657,␉"NVIDIA G96" },␊
559␉{ 0x10DE0658,␉"Quadro FX 380" },␊
560␉{ 0x10DE0659,␉"Quadro FX 580" },␊
561␉{ 0x10DE065A,␉"Quadro FX 1700M" },␊
562␉{ 0x10DE065B,␉"GeForce 9400 GT" },␊
563␉{ 0x10DE065C,␉"Quadro FX 770M" },␊
564␉{ 0x10DE065D,␉"NVIDIA G96" },␊
565␉{ 0x10DE065E,␉"NVIDIA G96" },␊
566␉{ 0x10DE065F,␉"GeForce G210" },␊
567␉// 0660 - 066F␊
568␉// 0670 - 067F␊
569␉// 0680 - 068F␊
570␉// 0690 - 069F␊
571␉// 06A0 - 06AF␊
572␉{ 0x10DE06A0,␉"NVIDIA GT214" },␊
573␉// 06B0 - 06BF␊
574␉{ 0x10DE06B0,␉"NVIDIA GT214" },␊
575␉// 06C0 - 06CF␊
576␉{ 0x10DE06C0, "GeForce GTX 480" },␊
577␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
578␉{ 0x10DE06C4, "GeForce GTX 465" },␊
579␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
580␉{ 0x10DE06CD, "GeForce GTX 470" },␊
581␉// 06D0 - 06DF␊
582␉{ 0x10DE06D1,␉"Tesla C2050 / C2070" },␊
583␉// { 0x10DE06D1,␉0x10DE0771,␉"Tesla C2050" },␊
584␉// { 0x10DE06D1,␉0x10DE0772,␉"Tesla C2070" },␊
585␉{ 0x10DE06D2,␉"Tesla M2070 / X2070" },␊
586␉{ 0x10DE06D8, "Quadro 6000" },␊
587␉{ 0x10DE06D9, "Quadro 5000" },␊
588␉{ 0x10DE06DA, "Quadro 5000M" },␊
589␉{ 0x10DE06DC, "Quadro 6000" },␊
590␉{ 0x10DE06DD, "Quadro 4000" },␊
591␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
592␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
593␉{ 0x10DE06DF, "Tesla M2070-Q" }, ␊
594␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
595␉// 06E0 - 06EF␉␊
596␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
597␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
598␉{ 0x10DE06E2, "GeForce 8400" },␊
599␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
600␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
601␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
602␉{ 0x10DE06E6, "GeForce G100" },␊
603␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
604␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
605␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
606␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
607␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
608␉{ 0x10DE06EC, "GeForce G 105M" },␊
609␉{ 0x10DE06EF, "GeForce G 103M" },␊
610␉// 06F0 - 06FF␉␊
611␉{ 0x10DE06F0,␉"NVIDIA G98" },␊
612␉{ 0x10DE06F1,␉"GeForce G105M" },␊
613␉{ 0x10DE06F2,␉"NVIDIA G98" },␊
614␉{ 0x10DE06F3,␉"NVIDIA G98" },␊
615␉{ 0x10DE06F4,␉"NVIDIA G98" },␊
616␉{ 0x10DE06F5,␉"NVIDIA G98" },␊
617␉{ 0x10DE06F6,␉"NVIDIA G98" },␊
618␉{ 0x10DE06F7,␉"NVIDIA G98" },␊
619␉{ 0x10DE06F8,␉"Quadro NVS 420" },␊
620␉{ 0x10DE06F9,␉"Quadro FX 370 LP" },␊
621␉{ 0x10DE06FA,␉"Quadro NVS 450" },␊
622␉{ 0x10DE06FB,␉"Quadro FX 370M" },␊
623␉{ 0x10DE06FC,␉"NVIDIA G98" },␊
624␉{ 0x10DE06FD,␉"Quadro NVS 295" },␊
625␉{ 0x10DE06FE,␉"NVIDIA G98" },␊
626␉{ 0x10DE06FF,␉"HICx16 + Graphics" },␊
627␉// 0700 - 070F␊
628␉// 0710 - 071F␊
629␉// 0720 - 072F␊
630␉// 0730 - 073F␊
631␉// 0740 - 074F␊
632␉// 0750 - 075F␊
633␉// 0760 - 076F␊
634␉// 0770 - 077F␊
635␉// 0780 - 078F␊
636␉// 0790 - 079F␊
637␉// 07A0 - 07AF␊
638␉// 07B0 - 07BF␊
639␉// 07C0 - 07CF␊
640␉// 07D0 - 07DF␉␊
641␉// 07E0 - 07EF␉␉␊
642␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
643␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
644␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
645␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
646␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
647␉// 07F0 - 07FF␉␊
648␉// 0800 - 080F␊
649␉// 0810 - 081F␊
650␉// 0820 - 082F␊
651␉// 0830 - 083F␊
652␉// 0840 - 084F␊
653␉{ 0x10DE0840, "GeForce 8200M" }, ␊
654␉{ 0x10DE0844, "GeForce 9100M G" },␊
655␉{ 0x10DE0845, "GeForce 8200M G" },␊
656␉{ 0x10DE0846, "GeForce 9200" },␊
657␉{ 0x10DE0847, "GeForce 9100" },␊
658␉{ 0x10DE0848, "GeForce 8300" },␊
659␉{ 0x10DE0849, "GeForce 8200" },␊
660␉{ 0x10DE084A, "nForce 730a" },␊
661␉{ 0x10DE084B, "GeForce 9200" },␊
662␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
663␉{ 0x10DE084D, "nForce 750a SLI" },␊
664␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
665␉// 0850 - 085F␊
666␉// 0860 - 086F␉␊
667␉{ 0x10DE0860, "GeForce 9400" },␊
668␉{ 0x10DE0861, "GeForce 9400" },␊
669␉{ 0x10DE0862, "GeForce 9400M G" },␊
670␉{ 0x10DE0863, "GeForce 9400M" },␊
671␉{ 0x10DE0864, "GeForce 9300" },␊
672␉{ 0x10DE0865, "ION" },␊
673␉{ 0x10DE0866, "GeForce 9400M G" },␊
674␉{ 0x10DE0867, "GeForce 9400" },␊
675␉{ 0x10DE0868, "nForce 760i SLI" },␊
676␉{ 0x10DE0869, "GeForce 9400" }, ␊
677␉{ 0x10DE086A, "GeForce 9400" },␊
678␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
679␉{ 0x10DE086D, "GeForce 9200" },␊
680␉{ 0x10DE086E, "GeForce 9100M G" },␊
681␉{ 0x10DE086F, "GeForce 8200M G" },␊
682␉// 0870 - 087F␉␊
683␉{ 0x10DE0870, "GeForce 9400M" },␊
684␉{ 0x10DE0871, "GeForce 9200" },␊
685␉{ 0x10DE0872, "GeForce G102M" },␊
686␉{ 0x10DE0873, "GeForce G102M" },␊
687␉{ 0x10DE0874, "ION 9300M" },␉␊
688␉{ 0x10DE0876, "ION" },␊
689␉{ 0x10DE087A, "GeForce 9400" },␊
690␉{ 0x10DE087D, "ION 9400M" },␊
691␉{ 0x10DE087E, "ION LE" },␊
692␉{ 0x10DE087F, "ION LE" },␊
693␉// 0880 - 088F␊
694␉// 0890 - 089F␊
695␉// 08A0 - 08AF␊
696␉{ 0x10DE08A0,␉"GeForce 320M" },␊
697␉{ 0x10DE08A3,␉"GeForce 320M" },␊
698␉{ 0x10DE08A4,␉"GeForce 320M" },␊
699␉{ 0x10DE08A5,␉"GeForce 320M" },␊
700␉// 08B0 - 08BF␊
701␉{ 0x10DE08B1,␉"GeForce 300M" },␊
702␉// 08C0 - 08CF␊
703␉// 08D0 - 08DF␉␊
704␉// 08E0 - 08EF␉␉␉␊
705␉// 08F0 - 08FF␊
706␉// 0900 - 090F␊
707␉// 0910 - 091F␊
708␉// 0920 - 092F␊
709␉// 0930 - 093F␊
710␉// 0940 - 094F␊
711␉// 0950 - 095F␊
712␉// 0960 - 096F␊
713␉// 0970 - 097F␊
714␉// 0980 - 098F␊
715␉// 0990 - 099F␊
716␉// 09A0 - 09AF␊
717␉// 09B0 - 09BF␊
718␉// 09C0 - 09CF␊
719␉// 09D0 - 09DF␉␊
720␉// 09E0 - 09EF␊
721␉// 09F0 - 09FF␊
722␉// 0A00 - 0A0F␊
723␉// 0A10 - 0A1F␊
724␉// 0A20 - 0A2F␊
725␉{ 0x10DE0A20, "GeForce GT220" },␊
726␉{ 0x10DE0A22, "GeForce 315" },␊
727␉{ 0x10DE0A23, "GeForce 210" },␊
728␉{ 0x10DE0A26, "GeForce 405" }, ␊
729␉{ 0x10DE0A27, "GeForce 405" }, ␊
730␉{ 0x10DE0A28, "GeForce GT 230M" },␊
731␉{ 0x10DE0A29, "GeForce GT 330M" },␊
732␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
733␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
734␉{ 0x10DE0A2C, "NVS 5100M" },␊
735␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
736␉// 0A30 - 0A3F␉␊
737␉{ 0x10DE0A32,␉"GeForce GT 415" },␊
738␉{ 0x10DE0A34,␉"GeForce GT 240M" },␊
739␉{ 0x10DE0A35,␉"GeForce GT 325M" },␊
740␉{ 0x10DE0A38,␉"Quadro 400" },␊
741␉{ 0x10DE0A3C,␉"Quadro FX 880M" },␊
742␉// 0A40 - 0A4F␊
743␉// 0A50 - 0A5F␊
744␉// 0A60 - 0A6F␊
745␉{ 0x10DE0A60, "GeForce G210" },␊
746␉{ 0x10DE0A62, "GeForce 205" },␊
747␉{ 0x10DE0A63, "GeForce 310" },␊
748␉{ 0x10DE0A64, "ION" },␊
749␉{ 0x10DE0A65, "GeForce 210" },␊
750␉{ 0x10DE0A66, "GeForce 310" },␊
751␉{ 0x10DE0A67, "GeForce 315" },␊
752␉{ 0x10DE0A68, "GeForce G105M" },␊
753␉{ 0x10DE0A69, "GeForce G105M" },␊
754␉{ 0x10DE0A6A, "NVS 2100M" },␊
755␉{ 0x10DE0A6C, "NVS 3100M" },␊
756␉{ 0x10DE0A6E, "GeForce 305M" },␊
757␉{ 0x10DE0A6F, "ION" },␉␊
758␉// 0A70 - 0A7F␊
759␉{ 0x10DE0A70, "GeForce 310M" },␊
760␉{ 0x10DE0A71, "GeForce 305M" },␊
761␉{ 0x10DE0A72, "GeForce 310M" },␊
762␉{ 0x10DE0A73, "GeForce 305M" },␊
763␉{ 0x10DE0A74, "GeForce G210M" },␊
764␉{ 0x10DE0A75, "GeForce G310M" },␊
765␉{ 0x10DE0A76, "ION" }, ␊
766␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
767␉{ 0x10DE0A7A, "GeForce 315M" },␊
768 ␉{ 0x10DE0A7B,␉"GeForce 505" },␊
769␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
770␉// 0A80 - 0A8F␊
771␉// 0A90 - 0A9F␊
772␉// 0AA0 - 0AAF␊
773␉// 0AB0 - 0ABF␊
774␉// 0AC0 - 0ACF␊
775␉// 0AD0 - 0ADF␉␊
776␉// 0AE0 - 0AEF␊
777␉// 0AF0 - 0AFF␊
778␉// 0B00 - 0B0F␊
779␉// 0B10 - 0B1F␊
780␉// 0B20 - 0B2F␊
781␉// 0B30 - 0B3F␊
782␉// 0B40 - 0B4F␊
783␉// 0B50 - 0B5F␊
784␉// 0B60 - 0B6F␊
785␉// 0B70 - 0B7F␊
786␉// 0B80 - 0B8F␊
787␉// 0B90 - 0B9F␊
788␉// 0BA0 - 0BAF␊
789␉// 0BB0 - 0BBF␊
790␉// 0BC0 - 0BCF␊
791␉// 0BD0 - 0BDF␉␊
792␉// 0BE0 - 0BEF␊
793␉// 0BF0 - 0BFF␊
794␉// 0C00 - 0C0F␊
795␉// 0C10 - 0C1F␊
796␉// 0C20 - 0C2F␊
797␉// 0C30 - 0C3F␊
798␉// 0C40 - 0C4F␊
799␉// 0C50 - 0C5F␊
800␉// 0C60 - 0C6F␊
801␉// 0C70 - 0C7F␊
802␉// 0C80 - 0C8F␊
803␉// 0C90 - 0C9F␊
804␉// 0CA0 - 0CAF␊
805␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
806␉{ 0x10DE0CA2, "GeForce GT 320" },␊
807␉{ 0x10DE0CA3, "GeForce GT 240" },␊
808␉{ 0x10DE0CA4, "GeForce GT 340" },␊
809␉{ 0x10DE0CA5, "GeForce GT 220" }, ␊
810␉{ 0x10DE0CA7, "GeForce GT 330" },␊
811␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
812␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
813␉{ 0x10DE0CAC, "GeForce GT 220" }, ␊
814␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
815␉// 0CB0 - 0CBF␉␊
816␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
817␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
818␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
819␉// 0CC0 - 0CCF␊
820␉// 0CD0 - 0CDF␉␊
821␉// 0CE0 - 0CEF␊
822␉// 0CF0 - 0CFF␊
823␉// 0D00 - 0D0F␊
824␉// 0D10 - 0D1F␊
825␉// 0D20 - 0D2F␊
826␉// 0D30 - 0D3F␊
827␉// 0D40 - 0D4F␊
828␉// 0D50 - 0D5F␊
829␉// 0D60 - 0D6F␊
830␉// 0D70 - 0D7F␊
831␉// 0D80 - 0D8F␊
832␉// 0D90 - 0D9F␊
833␉// 0DA0 - 0DAF␉␊
834␉// 0DB0 - 0DBF␊
835␉// 0DC0 - 0DCF␊
836␉{ 0x10DE0DC0, "GeForce GT 440" },␊
837␉{ 0x10DE0DC1, "D12-P1-35" },␊
838␉{ 0x10DE0DC2, "D12-P1-35" },␊
839␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
840␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
841␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
842␉{ 0x10DE0DCA, "GF10x" },␊
843␉{ 0x10DE0DCD, "GeForce GT 555M" }, ␊
844␉{ 0x10DE0DCE, "GeForce GT 555M" }, ␊
845␉// 0DD0 - 0DDF␉␊
846␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
847␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
848␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
849␉{ 0x10DE0DD6, "GeForce GT 550M" }, ␊
850␉{ 0x10DE0DD8, "Quadro 2000" },␊
851␉{ 0x10DE0DDA, "Quadro 2000M" }, ␊
852␉{ 0x10DE0DDE, "GF106-ES" },␊
853␉{ 0x10DE0DDF, "GF106-INT" },␊
854␉// 0DE0 - 0DEF␉␊
855␉{ 0x10DE0DE0,␉"GeForce GT 440" },␊
856␉{ 0x10DE0DE1,␉"GeForce GT 430" },␊
857␉{ 0x10DE0DE2,␉"GeForce GT 420" },␊
858␉{ 0x10DE0DE4,␉"GeForce GT 520" },␊
859␉{ 0x10DE0DE5,␉"GeForce GT 530" },␊
860␉{ 0x10DE0DE8,␉"GeForce GT 620M" },␊
861␉{ 0x10DE0DE9,␉"GeForce GT 630M" },␊
862␉{ 0x10DE0DEA,␉"GeForce GT 610M" },␊
863␉{ 0x10DE0DEB,␉"GeForce GT 555M" },␊
864␉{ 0x10DE0DEC,␉"GeForce GT 525M" },␊
865␉{ 0x10DE0DED,␉"GeForce GT 520M" },␊
866␉{ 0x10DE0DEE,␉"GeForce GT 415M" },␊
867␊
868␉// 0DF0 - 0DFF␉␊
869␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
870␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
871␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
872␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
873␉{ 0x10DE0DF4, "GeForce GT 540M" }, ␊
874␉{ 0x10DE0DF5, "GeForce GT 525M" }, ␊
875␉{ 0x10DE0DF6, "GeForce GT 550M" }, ␊
876␉{ 0x10DE0DF7, "GeForce GT 520M" }, ␊
877␉{ 0x10DE0DF8, "Quadro 600" },␊
878 ␉{ 0x10DE0DF9,␉"Quadro 500M" },␊
879␉{ 0x10DE0DFA, "Quadro 1000M" }, ␊
880␉{ 0x10DE0DFE, "GF108 ES" },␊
881␉{ 0x10DE0DFF, "GF108 INT" },␊
882␉// 0E00 - 0E0F␊
883␉// 0E10 - 0E1F␊
884␉// 0E20 - 0E2F␊
885␉{ 0x10DE0E21, "D12U-25" },␊
886␉{ 0x10DE0E22, "GeForce GTX 460" },␊
887␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
888␉{ 0x10DE0E24, "GeForce GTX 460" },␊
889␉{ 0x10DE0E25, "D12U-50" },␊
890 ␉{ 0x10DE0E28,␉"GeForce GTX 460" },␊
891␉// 0E30 - 0E3F␉␊
892␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
893␉{ 0x10DE0E31, "GeForce GTX 485M" }, ␊
894␉{ 0x10DE0E38, "GF104GL" },␊
895␉{ 0x10DE0E3A, "Quadro 3000M" }, ␊
896␉{ 0x10DE0E3B, "Quadro 4000M" }, ␊
897␉{ 0x10DE0E3E, "GF104-ES" },␊
898␉{ 0x10DE0E3F, "GF104-INT" },␊
899␉// 0E40 - 0E4F␉␊
900␉// 0E50 - 0E5F␊
901␉// 0E60 - 0E6F␊
902␉// 0E70 - 0E7F␊
903␉// 0E80 - 0E8F␊
904␉// 0E90 - 0E9F␊
905␉// 0EA0 - 0EAF␊
906␉// 0EB0 - 0EBF␊
907␉// 0EC0 - 0ECF␊
908␉// 0ED0 - 0EDF␉␊
909␉// 0EE0 - 0EEF␊
910␉// 0EF0 - 0EFF␊
911␉// 0F00 - 0F0F␊
912␉// 0F10 - 0F1F␊
913␉// 0F20 - 0F2F␊
914␉// 0F30 - 0F3F␊
915␉// 0F40 - 0F4F␊
916␉// 0F50 - 0F5F␊
917␉// 0F60 - 0F6F␊
918␉// 0F70 - 0F7F␊
919␉// 0F80 - 0F8F␊
920␉// 0F90 - 0F9F␊
921␉// 0FA0 - 0FAF␊
922␉// 0FB0 - 0FBF␊
923␉// 0FC0 - 0FCF␊
924␉// 0FD0 - 0FDF␊
925 { 0x10DE0FD1,␉"GeForce GT 650M" },␊
926␉{ 0x10DE0FD2,␉"GeForce GT 640M" },␊
927␉{ 0x10DE0FD4,␉"GeForce GTX 660M" },␊
928␉// 0FE0 - 0FEF␊
929␉// 0FF0 - 0FFF␊
930␉// 1000 - 100F␊
931␉// 1010 - 101F␊
932␉// 1020 - 102F␊
933␉// 1030 - 103F␊
934␉// 1040 - 104F␊
935␉{ 0x10DE1040, "GeForce GT 520" },␊
936 { 0x10DE1042,␉"GeForce 510" },␊
937␉{ 0x10DE1048,␉"GeForce 605" },␊
938␉{ 0x10DE1049,␉"GeForce GT 620" },␊
939␉// 1050 - 105F␊
940␉{ 0x10DE1050,␉"GeForce GT 520M" },␊
941␉{ 0x10DE1051,␉"GeForce GT 520MX" },␊
942␉{ 0x10DE1052,␉"GeForce GT 520M" },␊
943␉{ 0x10DE1054,␉"GeForce GT 410M" },␊
944␉{ 0x10DE1055,␉"GeForce 410M" },␊
945␉{ 0x10DE1056,␉"Quadro NVS 4200M" },␊
946␉{ 0x10DE1057,␉"Quadro NVS 4200M" },␊
947␉{ 0x10DE1058,␉"GeForce 610M" },␊
948␉{ 0x10DE1059,␉"GeForce 610M" },␊
949␉{ 0x10DE105A,␉"GeForce 610M" },␊
950␉// 1060 - 106F␊
951␉// 1070 - 107F␊
952␉{ 0x10DE107F, "NVIDIA GF119-ES" }, ␊
953␉// 1080 - 108F␊
954␉{ 0x10DE1080, "GeForce GTX 580" },␊
955␉{ 0x10DE1081, "GeForce GTX 570" },␊
956␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
957␉{ 0x10DE1083, "D13U" },␊
958␉{ 0x10DE1084, "GeForce GTX 560" }, ␊
959␉{ 0x10DE1086, "GeForce GTX 570" }, ␊
960␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" }, ␊
961␉{ 0x10DE1088, "GeForce GTX 590" },␊
962␉{ 0x10DE1089, "GeForce GTX 580" }, ␊
963␉{ 0x10DE108B, "GeForce GTX 590" },␊
964 ␉{ 0x10DE108E,␉"Tesla C2090" },␊
965␉// 1090 - 109F␉␊
966␉{ 0x10DE1091, "Tesla M2090" },␊
967 { 0x10DE1094,␉"Tesla M2075 Dual-Slot Computing Processor Module" },␊
968␉{ 0x10DE1096,␉"Tesla C2075" },␊
969␉{ 0x10DE1098, "D13U" },␊
970␉{ 0x10DE109A, "Quadro 5010M" }, ␊
971␉{ 0x10DE109B, "Quadro 7000" }, ␊
972␉// 10A0 - 10AF␊
973␉// 10B0 - 10BF␊
974␉// 10C0 - 10CF␊
975␉{ 0x10DE10C0, "GeForce 9300 GS" }, ␊
976␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
977 ␉{ 0x10DE10C4,␉"NVIDIA ION" },␊
978␉{ 0x10DE10C5, "GeForce 405" }, ␊
979␉// 10D0 - 10DF␊
980␉{ 0x10DE10D8, "NVS 300" },␊
981 // 10E0 - 10EF␊
982␉// 10F0 - 10FF␊
983␉// 1100 - 110F␊
984␉// 1110 - 111F␊
985␉// 1120 - 112F␊
986␉// 1130 - 113F␊
987␉// 1140 - 114F␊
988␉// { 0x10DE1140,␉"GF117" },␊
989␉{ 0x10DE1141,␉"GeForce 610M" },␊
990␉{ 0x10DE1142,␉"GeForce 620M" },␊
991␉// { 0x10DE1143,␉"N13P-GV" },␊
992␉// { 0x10DE1144,␉"GF117" },␊
993␉// { 0x10DE1145,␉"GF117" },␊
994␉// { 0x10DE1146,␉"GF117" },␊
995␉// { 0x10DE1147,␉"GF117" },␊
996␉// { 0x10DE1149,␉"GF117-ES" },␊
997␉// { 0x10DE114A,␉"GF117-INT" },␊
998␉// { 0x10DE114B,␉"PCI-GEN3-B" },␊
999␉// 1150 - 115F␊
1000␉// 1160 - 116F␊
1001␉// 1170 - 117F␊
1002␉// 1180 - 118F␊
1003␉{ 0x10DE1180,␉"GeForce GTX 680" },␊
1004␉{ 0x10DE1188,␉"GeForce GTX 690" },␊
1005␉{ 0x10DE1189,␉"GeForce GTX 670" },␊
1006␉// 1190 - 119F␊
1007␉// 11A0 - 11AF␊
1008␉// 11B0 - 11BF␊
1009␉// 11C0 - 11CF␊
1010␉// 11D0 - 11DF␊
1011␉// 11E0 - 11EF␊
1012␉// 11F0 - 11FF␊
1013␉// 1200 - 120F␊
1014␉{ 0x10DE1200,␉"GeForce GTX 560 Ti" },␊
1015␉{ 0x10DE1201,␉"GeForce GTX 560" },␊
1016␉{ 0x10DE1202,␉"GeForce GTX 560 Ti" },␊
1017␉{ 0x10DE1203,␉"GeForce GTX 460 SE v2" },␊
1018␉{ 0x10DE1205,␉"GeForce GTX 460 v2" },␊
1019␉{ 0x10DE1206,␉"GeForce GTX 555" },␊
1020␉{ 0x10DE1208,␉"GeForce GTX 560 SE" },␊
1021␉{ 0x10DE1210,␉"GeForce GTX 570M" },␊
1022␉{ 0x10DE1211,␉"GeForce GTX 580M" },␊
1023␉{ 0x10DE1212,␉"GeForce GTX 675M" },␊
1024␉{ 0x10DE1213,␉"GeForce GTX 670M" },␊
1025␉{ 0x10DE1240,␉"GeForce GT 620M" },␊
1026␉{ 0x10DE1241,␉"GeForce GT 545" },␊
1027␉{ 0x10DE1243,␉"GeForce GT 545" },␊
1028␉{ 0x10DE1244,␉"GeForce GTX 550 Ti" },␊
1029␉{ 0x10DE1245,␉"GeForce GTS 450" },␊
1030␉{ 0x10DE1246,␉"GeForce GTX 550M" },␊
1031␉{ 0x10DE1247,␉"GeForce GT 635M" }, // Subsystem Id: 1043 212C Asus GeForce GT 635M␊
1032␉{ 0x10DE1248,␉"GeForce GTX 555M" },␊
1033␉{ 0x10DE124B,␉"GeForce GT 640" },␊
1034␉{ 0x10DE124D,␉"GeForce GTX 555M" },␊
1035␉// { 0x10DE1250,␉"GF116-INT" },␊
1036␉{ 0x10DE1251,␉"GeForce GTX 560M" },␊
1037␉// 1260 - 126F␊
1038␉// 1270 - 127F␊
1039␉// 1280 - 128F␊
1040␉// 1290 - 129F␊
1041␉// 12A0 - 12AF␊
1042␉// 12B0 - 12BF␊
1043␉// 12C0 - 12CF␊
1044␉// 12D0 - 12DF␊
1045␉// 12E0 - 12EF␊
1046␉// 12F0 - 12FF␊
1047␊
1048};␊
1049␊
1050␊
1051␊
1052static int patch_nvidia_rom(uint8_t *rom)␊
1053{␊
1054␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1055␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1056␉␉return PATCH_ROM_FAILED;␊
1057␉}␊
1058␉␊
1059␉uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);␊
1060␊
1061␉if (!dcbptr) {␊
1062␉␉printf("no dcb table found\n");␊
1063␉␉return PATCH_ROM_FAILED;␊
1064␉}␊
1065//␉else␊
1066//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1067␉ ␊
1068␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1069␉uint8_t dcbtable_version = dcbtable[0];␊
1070␉uint8_t headerlength␉ = 0;␊
1071␉uint8_t numentries␉␉ = 0;␊
1072␉uint8_t recordlength␉ = 0;␊
1073␉␊
1074␉if (dcbtable_version >= 0x20)␊
1075␉{␊
1076␉␉uint32_t sig;␊
1077␉␉␊
1078␉␉if (dcbtable_version >= 0x30)␊
1079␉␉{␊
1080␉␉␉headerlength = dcbtable[1];␊
1081␉␉␉numentries␉ = dcbtable[2];␊
1082␉␉␉recordlength = dcbtable[3];␊
1083␊
1084␉␉␉sig = READ_LE_INT(dcbtable, 6);␊
1085␉␉}␊
1086␉␉else␊
1087␉␉{␊
1088␉␉␉sig = READ_LE_INT(dcbtable, 4);␊
1089␉␉␉headerlength = 8;␊
1090␉␉}␊
1091␉␉␊
1092␉␉if (sig != 0x4edcbdcb)␊
1093␉␉{␊
1094␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1095␉␉␉return PATCH_ROM_FAILED;␊
1096␉␉}␊
1097␉}␊
1098␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1099␉{␊
1100␉␉char sig[8] = { 0 };␊
1101␉␉␊
1102␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1103␉␉recordlength = 10;␊
1104␉␉␊
1105␉␉if (strcmp(sig, "DEV_REC"))␊
1106␉␉{␊
1107␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1108␉␉␉return PATCH_ROM_FAILED;␊
1109␉␉}␊
1110␉}␊
1111␉else␊
1112␉{␊
1113␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1114␉␉return PATCH_ROM_FAILED;␊
1115␉}␊
1116␉␊
1117␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1118␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1119␉␊
1120␉uint8_t num_outputs = 0, i = 0;␊
1121␉␊
1122␉struct dcbentry␊
1123␉{␊
1124␉␉uint8_t type;␊
1125␉␉uint8_t index;␊
1126␉␉uint8_t *heads;␊
1127␉} entries[numentries];␊
1128␉␊
1129␉for (i = 0; i < numentries; i++)␊
1130␉{␊
1131␉␉uint32_t connection;␊
1132␉␉connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);␊
1133␊
1134␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1135␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1136␉␉␉continue;␊
1137␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1138␉␉␉continue;␊
1139␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1140␉␉␉continue;␊
1141␉␉␊
1142␉␉entries[num_outputs].type = connection & 0xf;␊
1143␉␉entries[num_outputs].index = num_outputs;␊
1144␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1145␉}␊
1146␉␊
1147␉int has_lvds = false;␊
1148␉uint8_t channel1 = 0, channel2 = 0;␊
1149␉␊
1150␉for (i = 0; i < num_outputs; i++)␊
1151␉{␊
1152␉␉if (entries[i].type == 3)␊
1153␉␉{␊
1154␉␉␉has_lvds = true;␊
1155␉␉␉//printf("found LVDS\n");␊
1156␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1157␉␉␉entries[i].type = TYPE_GROUPED;␊
1158␉␉}␊
1159␉}␊
1160␉␊
1161␉// if we have a LVDS output, we group the rest to the second channel␊
1162␉if (has_lvds)␊
1163␉{␊
1164␉␉for (i = 0; i < num_outputs; i++)␊
1165␉␉{␊
1166␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1167␉␉␉␉continue;␊
1168␉␉␉␊
1169␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1170␉␉␉entries[i].type = TYPE_GROUPED;␊
1171␉␉}␊
1172␉}␊
1173␉else␊
1174␉{␊
1175␉␉int x;␊
1176␉␉// we loop twice as we need to generate two channels␊
1177␉␉for (x = 0; x <= 1; x++)␊
1178␉␉{␊
1179␉␉␉for (i=0; i<num_outputs; i++)␊
1180␉␉␉{␊
1181␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1182␉␉␉␉␉continue;␊
1183␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1184␉␉␉␉// we always group ANALOG and TMDS␊
1185␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1186␉␉␉␉if (i && entries[i].type == 0x2)␊
1187␉␉␉␉{␊
1188␉␉␉␉␉switch (x)␊
1189␉␉␉␉␉{␊
1190␉␉␉␉␉␉case 0:␊
1191␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1192␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1193␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1194␉␉␉␉␉␉␉␊
1195␉␉␉␉␉␉␉if ( entries[i-1].type == 0x0 )␊
1196␉␉␉␉␉␉␉{␊
1197␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1198␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1199␉␉␉␉␉␉␉}␊
1200␉␉␉␉␉␉␉// group TV as well if there is one␊
1201␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1202␉␉␉␉␉␉␉{␊
1203␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1204␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1205␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1206␉␉␉␉␉␉␉}␊
1207␉␉␉␉␉␉␉break;␊
1208␉␉␉␉␉␉␊
1209␉␉␉␉␉␉case 1:␊
1210␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1211␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1212␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1213␉␉␉␉␉␉␉␊
1214␉␉␉␉␉␉␉if ( entries[i - 1].type == 0x0 )␊
1215␉␉␉␉␉␉␉{␊
1216␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1217␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1218␉␉␉␉␉␉␉}␊
1219␉␉␉␉␉␉␉// group TV as well if there is one␊
1220␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1221␉␉␉␉␉␉␉{␊
1222␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1223␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1224␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1225␉␉␉␉␉␉␉}␊
1226␉␉␉␉␉␉␉break;␊
1227␉␉␉␉␉}␊
1228␉␉␉␉␉break;␊
1229␉␉␉␉}␊
1230␉␉␉}␊
1231␉␉}␊
1232␉}␊
1233␉␊
1234␉// if we have left ungrouped outputs merge them to the empty channel␊
1235␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1236␉togroup = &channel2;␊
1237␉␊
1238␉for (i = 0; i < num_outputs; i++)␊
1239␉{␊
1240␉␉if (entries[i].type != TYPE_GROUPED)␊
1241␉␉{␊
1242␉␉␉//printf("%d not grouped\n", i);␊
1243␉␉␉if (togroup)␊
1244␉␉␉{␊
1245␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1246␉␉␉}␊
1247␉␉␉entries[i].type = TYPE_GROUPED;␊
1248␉␉}␊
1249␉}␊
1250␉␊
1251␉if (channel1 > channel2)␊
1252␉{␊
1253␉␉uint8_t buff = channel1;␊
1254␉␉channel1 = channel2;␊
1255␉␉channel2 = buff;␊
1256␉}␊
1257␉␊
1258␉default_NVCAP[6] = channel1;␊
1259␉default_NVCAP[8] = channel2;␊
1260␉␊
1261␉// patching HEADS␊
1262␉for (i = 0; i < num_outputs; i++)␊
1263␉{␊
1264␉␉if (channel1 & (1 << i))␊
1265␉␉{␊
1266␉␉␉*entries[i].heads = 1;␊
1267␉␉}␊
1268␉␉else if(channel2 & (1 << i))␊
1269␉␉{␊
1270␉␉␉*entries[i].heads = 2;␊
1271␉␉}␊
1272␉}␊
1273␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1274}␊
1275␊
1276static char *get_nvidia_model(uint32_t id)␊
1277{␊
1278␉int i;␊
1279␉␊
1280␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1281␉␉if (NVKnownChipsets[i].device == id)␊
1282␉␉{␊
1283␉␉␉return NVKnownChipsets[i].name;␊
1284␉␉}␊
1285␉}␊
1286␉return NVKnownChipsets[0].name;␊
1287}␊
1288␊
1289static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1290{␊
1291␉int fd;␊
1292␉int size;␊
1293␉␊
1294␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1295␉{␊
1296␉␉return 0;␊
1297␉}␊
1298␉␊
1299␉size = file_size(fd);␊
1300␉␊
1301␉if (size > bufsize)␊
1302␉{␊
1303␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1304␉␉␉␉filename, bufsize);␊
1305␉␉size = bufsize;␊
1306␉}␊
1307␉size = read(fd, (char *)buf, size);␊
1308␉close(fd);␊
1309␉␊
1310␉return size > 0 ? size : 0;␊
1311}␊
1312␊
1313␊
1314static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1315{␊
1316␉char tmp[16];␊
1317␉␊
1318␉if (!device)␊
1319␉␉return 0;␊
1320␉␊
1321␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1322␉␉return 0;␊
1323␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1324␉␉return 0;␊
1325␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1326␉␉return 0;␊
1327␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1328␉␉return 0;␊
1329␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1330␉␉return 0;␊
1331␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1332␉␉return 0;␊
1333␉if (devices_number == 1)␊
1334␉{␊
1335␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1336␉␉ return 0;␊
1337␉}␊
1338␉else␊
1339␉{␊
1340␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1341␉␉ return 0;␊
1342␉}␊
1343␉␊
1344␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1345␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1346␉sprintf(tmp, "Slot-%x",devices_number);␊
1347␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1348␉devices_number++;␊
1349␉␊
1350␉return 1;␊
1351}␊
1352␊
1353int hex2bin(const char *hex, uint8_t *bin, int len)␊
1354{␊
1355␉char␉*p;␊
1356␉int␉␉i;␊
1357␉char␉buf[3];␊
1358␉␊
1359␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1360␉␉printf("[ERROR] bin2hex input error\n");␊
1361␉␉return -1;␊
1362␉}␊
1363␉␊
1364␉buf[2] = '\0';␊
1365␉p = (char *) hex;␊
1366␉␊
1367␉for (i = 0; i < len; i++)␊
1368␉{␊
1369␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1370␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1371␉␉␉return -2;␊
1372␉␉}␊
1373␉␉buf[0] = *p++;␊
1374␉␉buf[1] = *p++;␊
1375␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1376␉}␊
1377␉return 0;␊
1378}␊
1379␊
1380unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1381{␊
1382␉unsigned long long vram_size = 0;␊
1383␉␊
1384␉if (nvCardType < NV_ARCH_50)␊
1385␉{␊
1386␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1387␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1388␉}␊
1389␉else if (nvCardType < NV_ARCH_C0)␊
1390␉{␊
1391␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1392␉␉vram_size |= (vram_size & 0xff) << 32;␊
1393␉␉vram_size &= 0xffffffff00ll;␊
1394␉}␊
1395␉else // >= NV_ARCH_C0␊
1396␉{␊
1397␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1398␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1399␉}␊
1400␉␊
1401␉// Workaround for 9600M GT, GT 420/430/440 & GT 525M␊
1402␉switch (nvda_dev->device_id)␊
1403␉{␊
1404 // 9600M GT␊
1405␉␉case 0x0649:␊
1406 case 0x0647:␊
1407 vram_size = 512*1024*1024;␊
1408 break;␊
1409 case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊
1410␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1411␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1412␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1413␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1414␉␉case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M␊
1415␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1416␉␉case 0x1251: vram_size = 1536*1024*1024; break; // GTX 560M␊
1417␉␉default: break;␊
1418␉}␊
1419␉␊
1420␉return vram_size;␊
1421}␊
1422␊
1423static bool checkNvRomSig(uint8_t * aRom){␊
1424 return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊
1425}␊
1426␊
1427bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1428{␊
1429␉struct DevPropDevice␉*device;␊
1430␉char␉␉␉␉␉*devicepath;␊
1431␉option_rom_pci_header_t *rom_pci_header;␊
1432␉volatile uint8_t␉␉*regs;␊
1433␉uint8_t␉␉␉␉␉*rom;␊
1434␉uint8_t␉␉␉␉␉*nvRom;␊
1435␉uint8_t␉␉␉␉␉nvCardType;␊
1436␉unsigned long long␉␉videoRam;␊
1437␉uint32_t␉␉␉␉nvBiosOveride;␊
1438␉uint32_t␉␉␉␉bar[7];␊
1439␉uint32_t␉␉␉␉boot_display;␊
1440␉int␉␉␉␉␉␉nvPatch;␊
1441␉int␉␉␉␉␉␉len;␊
1442␉char␉␉␉␉␉biosVersion[32];␊
1443␉char␉␉␉␉␉nvFilename[32];␊
1444␉char␉␉␉␉␉kNVCAP[12];␊
1445␉char␉␉␉␉␉*model;␊
1446␉const char␉␉␉␉*value;␊
1447␉bool␉␉␉␉␉doit;␊
1448␉␊
1449␉devicepath = get_pci_dev_path(nvda_dev);␊
1450␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1451␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1452␉␊
1453␉// get card type␊
1454␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1455␉␊
1456␉// Amount of VRAM in kilobytes␊
1457␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1458␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1459␉␊
1460 verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s device number: %d\n",␊
1461 model, (uint32_t)(videoRam / 1024 / 1024),␊
1462 (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1463 ␉␉␉devicepath, devices_number);␊
1464␉␊
1465␉rom = malloc(NVIDIA_ROM_SIZE);␊
1466␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1467␉␉␉(uint16_t)nvda_dev->device_id);␊
1468␉␊
1469␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1470␉{␊
1471␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1472␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1473␉␉␊
1474␉␉if (nvBiosOveride > 0)␊
1475␉␉{␊
1476␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1477␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1478␉␉}␊
1479␉␉else␊
1480␉␉{␊
1481␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1482␉␉␉return false;␊
1483␉␉}␊
1484␉}␊
1485␉else␊
1486␉{␊
1487␉␉// Otherwise read bios from card␊
1488␉␉nvBiosOveride = 0;␊
1489␉␉␊
1490 // PROM first␊
1491 // Enable PROM access␊
1492 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1493 nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1494 ␊
1495 // Valid Signature ?␊
1496␉␉if (checkNvRomSig(nvRom))␊
1497␉␉{␊
1498 bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1499 DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1500 }␊
1501 else␊
1502 {␊
1503␊
1504 // disable PROM access␊
1505 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1506 ␊
1507␉␉ //PRAM next␊
1508 nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1509 ␊
1510 if(checkNvRomSig(nvRom))␊
1511 {␊
1512 bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1513 DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1514 }␊
1515 else␊
1516 ␉␉{␊
1517␉␉␉␉// 0xC0000 last␊
1518␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1519␉␉␉␉␊
1520␉␉␉␉// Valid Signature ?␊
1521␉␉␉␉if (!checkNvRomSig(rom))␊
1522␉␉␉␉{␊
1523␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1524␉␉␉␉␉return false;␊
1525␉␉␉␉}␊
1526 else␊
1527 {␊
1528 DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1529 }␊
1530 ␊
1531␉␉␉}//end PRAM check␊
1532 ␊
1533 }//end PROM check␊
1534 ␊
1535␉}//end load rom from bios␊
1536␉␊
1537␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1538␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1539␉␉//return false;␊
1540␉}␊
1541␉␊
1542␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1543␉␊
1544␉// check for 'PCIR' sig␊
1545␉if (rom_pci_header->signature == 0x50434952)␊
1546␉{␊
1547␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1548␉␉{␊
1549␉␉␉// Get Model from the OpROM␊
1550␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1551␉␉}␊
1552␉␉else␊
1553␉␉{␊
1554␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1555␉␉}␊
1556␉}␊
1557␉␊
1558␉if (!string) {␊
1559␉␉string = devprop_create_string();␊
1560␉}␊
1561␉device = devprop_add_device(string, devicepath);␊
1562␉␊
1563␉/* FIXME: for primary graphics card only */␊
1564␉boot_display = 1;␊
1565␉if (devices_number == 1)␊
1566␉{␊
1567␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1568␉}␊
1569␉␊
1570␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1571␉␉uint8_t built_in = 0x01;␊
1572␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1573␉}␊
1574␊
1575␉// get bios version␊
1576␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1577␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1578␉␊
1579␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1580␉␊
1581␉int i, version_start;␊
1582␉int crlf_count = 0;␊
1583␉␊
1584␉// only search the first 384 bytes␊
1585␉for (i = 0; i < 0x180; i++)␊
1586␉{␊
1587␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1588␉␉{␊
1589␉␉␉crlf_count++;␊
1590␉␉␉// second 0x0D0A was found, extract bios version␊
1591␉␉␉if (crlf_count == 2)␊
1592␉␉␉{␊
1593␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1594␉␉␉␉␊
1595␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1596␉␉␉␉{␊
1597␉␉␉␉␉// find start␊
1598␉␉␉␉␉if (rom[version_start] == 0x00)␊
1599␉␉␉␉␉{␊
1600␉␉␉␉␉␉version_start++;␊
1601␉␉␉␉␉␉␊
1602␉␉␉␉␉␉// strip "Version "␊
1603␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1604␉␉␉␉␉␉{␊
1605␉␉␉␉␉␉␉version_start += 8;␊
1606␉␉␉␉␉␉}␊
1607␉␉␉␉␉␉␊
1608␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1609␉␉␉␉␉␉break;␊
1610␉␉␉␉␉}␊
1611␉␉␉␉}␊
1612␉␉␉␉break;␊
1613␉␉␉}␊
1614␉␉}␊
1615␉}␊
1616␉␊
1617␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1618␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1619␉␊
1620␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1621␉{␊
1622␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1623␉␉␊
1624␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1625␉␉{␊
1626␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1627␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1628␉␉}␊
1629␉}␊
1630␉␊
1631␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1632␉{␊
1633␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1634␉␉␊
1635␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1636␉␉{␊
1637␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1638␉␉␉␊
1639␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1640␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1641␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1642␉␉}␊
1643␉}␊
1644␉␊
1645␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1646␉{␊
1647␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1648␉␉␊
1649␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1650␉␉{␊
1651␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1652␉␉␉␊
1653␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1654␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1655␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1656␉␉}␊
1657␉}␊
1658␉␊
1659#if DEBUG_NVCAP␊
1660␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1661␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1662␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1663␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1664␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1665␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1666#endif␊
1667␉␊
1668␉devprop_add_nvidia_template(device);␊
1669␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1670␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
1671␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1672␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1673␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1674␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1675␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1676␉␊
1677␊
1678␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1679␉{␊
1680␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1681␉}␊
1682␉␊
1683␉//add HDMI Audio back to nvidia␊
1684␉doit = false;␊
1685␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1686␉if(getBoolForKey(kEnableHDMIAudio, &doit, &bootInfo->chameleonConfig) && doit){␊
1687␉␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1688␉␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1689␉}␊
1690␉//end Nvidia HDMI Audio␊
1691␉␊
1692␉␊
1693␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1694␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1695␉stringlength = string->length;␊
1696␉␊
1697␉return true;␊
1698}␊
1699

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