Chameleon

Chameleon Svn Source Tree

Root/branches/ErmaC/Trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊
75#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊
76#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊
77#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊
78#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊
79␊
80extern uint32_t devices_number;␊
81␊
82const char *nvidia_compatible_0[] =␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
83const char *nvidia_compatible_1[] =␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
84const char *nvidia_device_type_0[] =␉{ "@0,device_type", "display"␉␉ };␊
85const char *nvidia_device_type_1[] =␉{ "@1,device_type", "display"␉␉ };␊
86const char *nvidia_device_type[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊
87const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
88const char *nvidia_name_0[] =␉{ "@0,name",␉␉"NVDA,Display-A" };␊
89const char *nvidia_name_1[] =␉{ "@1,name",␉␉"NVDA,Display-B" };␊
90const char *nvidia_slot_name[] =␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
91␊
92static uint8_t default_NVCAP[]= {␊
93␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
94␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
95␉0x00, 0x00, 0x00, 0x00␊
96};␊
97␊
98#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
99␊
100static uint8_t default_dcfg_0[]␉␉=␉{0x03, 0x01, 0x03, 0x00};␊
101static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0x00, 0x01};␊
102␊
103// uint8_t connector_type_1[]␉␉=␉{0x00, 0x08, 0x00, 0x00};␊
104␊
105#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
106#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
107␊
108static uint8_t default_NVPM[]= {␊
109 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
112 0x00, 0x00, 0x00, 0x00␊
113};␊
114␊
115#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊
116␊
117static struct nv_chipsets_t NVKnownChipsets[] = {␊
118␉{ 0x00000000,␉"Unknown" },␊
119//========================================␊
120␉// 0000 - 0040␉␊
121␉// 0040 - 004F␉␊
122␉{ 0x10DE0040,␉"GeForce 6800 Ultra" },␊
123␉{ 0x10DE0041,␉"GeForce 6800" },␊
124␉{ 0x10DE0042,␉"GeForce 6800 LE" },␊
125␉{ 0x10DE0043,␉"GeForce 6800 XE" },␊
126␉{ 0x10DE0044,␉"GeForce 6800 XT" },␊
127␉{ 0x10DE0045,␉"GeForce 6800 GT" },␊
128␉{ 0x10DE0046,␉"GeForce 6800 GT" },␊
129␉{ 0x10DE0047,␉"GeForce 6800 GS" },␊
130␉{ 0x10DE0048,␉"GeForce 6800 XT" },␊
131␉{ 0x10DE004D,␉"Quadro FX 3400" },␊
132␉{ 0x10DE004E,␉"Quadro FX 4000" },␊
133␉// 0050 - 005F␊
134␉// 0060 - 006F␊
135␉// 0070 - 007F␊
136␉// 0080 - 008F␊
137␉// 0090 - 009F␊
138␉{ 0x10DE0090,␉"GeForce 7800 GTX" },␊
139␉{ 0x10DE0091,␉"GeForce 7800 GTX" },␊
140␉{ 0x10DE0092,␉"GeForce 7800 GT" },␊
141␉{ 0x10DE0093,␉"GeForce 7800 GS" },␊
142␉{ 0x10DE0095,␉"GeForce 7800 SLI" },␊
143␉{ 0x10DE0098,␉"GeForce Go 7800" },␊
144␉{ 0x10DE0099,␉"GeForce Go 7800 GTX" },␊
145␉{ 0x10DE009D,␉"Quadro FX 4500" },␊
146␉// 00A0 - 00AF␉␊
147␉// 00B0 - 00BF␉␊
148␉// 00C0 - 00CF␉␊
149␉{ 0x10DE00C0,␉"GeForce 6800 GS" },␊
150␉{ 0x10DE00C1,␉"GeForce 6800" },␊
151␉{ 0x10DE00C2,␉"GeForce 6800 LE" },␊
152␉{ 0x10DE00C3,␉"GeForce 6800 XT" },␊
153␉{ 0x10DE00C8,␉"GeForce Go 6800" },␊
154␉{ 0x10DE00C9,␉"GeForce Go 6800 Ultra" },␊
155␉{ 0x10DE00CC,␉"Quadro FX Go1400" },␊
156␉{ 0x10DE00CD,␉"Quadro FX 3450/4000 SDI" },␊
157␉{ 0x10DE00CE,␉"Quadro FX 1400" },␊
158␉// 00D0 - 00DF␉␊
159␉// 00E0 - 00EF␉␊
160␉// 00F0 - 00FF␉␊
161␉{ 0x10DE00F1,␉"GeForce 6600 GT" },␊
162␉{ 0x10DE00F2,␉"GeForce 6600" },␊
163␉{ 0x10DE00F3,␉"GeForce 6200" },␊
164␉{ 0x10DE00F4,␉"GeForce 6600 LE" },␊
165␉{ 0x10DE00F5,␉"GeForce 7800 GS" },␊
166␉{ 0x10DE00F6,␉"GeForce 6800 GS/XT" },␊
167␉{ 0x10DE00F8,␉"Quadro FX 3400/4400" },␊
168␉{ 0x10DE00F9,␉"GeForce 6800 Series GPU" },␊
169␉// 0100 - 010F␉␊
170␉// 0110 - 011F␉␊
171␉// 0120 - 012F␉␊
172␉// 0130 - 013F␉␊
173␉// 0140 - 014F␉␊
174␉{ 0x10DE0140,␉"GeForce 6600 GT" },␊
175␉{ 0x10DE0141,␉"GeForce 6600" },␊
176␉{ 0x10DE0142,␉"GeForce 6600 LE" },␊
177␉{ 0x10DE0143,␉"GeForce 6600 VE" },␊
178␉{ 0x10DE0144,␉"GeForce Go 6600" },␊
179␉{ 0x10DE0145,␉"GeForce 6610 XL" },␊
180␉{ 0x10DE0146,␉"GeForce Go 6600 TE/6200 TE" },␊
181␉{ 0x10DE0147,␉"GeForce 6700 XL" },␊
182␉{ 0x10DE0148,␉"GeForce Go 6600" },␊
183␉{ 0x10DE0149,␉"GeForce Go 6600 GT" },␊
184␉{ 0x10DE014A,␉"Quadro NVS 440" },␊
185␉{ 0x10DE014C,␉"Quadro FX 550" },␊
186␉{ 0x10DE014D,␉"Quadro FX 550" },␊
187␉{ 0x10DE014E,␉"Quadro FX 540" },␊
188␉{ 0x10DE014F,␉"GeForce 6200" },␊
189␉// 0150 - 015F␉␊
190␉// 0160 - 016F␉␊
191␉{ 0x10DE0160,␉"GeForce 6500" },␊
192␉{ 0x10DE0161,␉"GeForce 6200 TurboCache(TM)" },␊
193␉{ 0x10DE0162,␉"GeForce 6200SE TurboCache(TM)" },␊
194␉{ 0x10DE0163,␉"GeForce 6200 LE" },␊
195␉{ 0x10DE0164,␉"GeForce Go 6200" },␊
196␉{ 0x10DE0165,␉"Quadro NVS 285" },␊
197␉{ 0x10DE0166,␉"GeForce Go 6400" },␊
198␉{ 0x10DE0167,␉"GeForce Go 6200" },␊
199␉{ 0x10DE0168,␉"GeForce Go 6400" },␊
200␉{ 0x10DE0169,␉"GeForce 6250" },␊
201␉{ 0x10DE016A,␉"GeForce 7100 GS" },␊
202␉{ 0x10DE016C,␉"NVIDIA NV44GLM" },␊
203␉{ 0x10DE016D,␉"NVIDIA NV44GLM" },␊
204␉// 0170 - 017F␉␊
205␉// 0180 - 018F␉␊
206␉// 0190 - 019F␉␉␊
207␉{ 0x10DE0191,␉"GeForce 8800 GTX" },␊
208␉{ 0x10DE0193,␉"GeForce 8800 GTS" },␊
209␉{ 0x10DE0194,␉"GeForce 8800 Ultra" },␊
210␉{ 0x10DE0197,␉"Tesla C870" },␊
211␉{ 0x10DE019D,␉"Quadro FX 5600" },␊
212␉{ 0x10DE019E,␉"Quadro FX 4600" },␊
213␉// 01A0 - 01AF␊
214␉// 01B0 - 01BF␊
215␉// 01C0 - 01CF␊
216␉// 01D0 - 01DF␊
217␉{ 0x10DE01D0,␉"GeForce 7350 LE" },␊
218␉{ 0x10DE01D1,␉"GeForce 7300 LE" },␊
219␉{ 0x10DE01D2,␉"GeForce 7550 LE" },␊
220␉{ 0x10DE01D3,␉"GeForce 7300 SE/7200 GS" },␊
221␉{ 0x10DE01D6,␉"GeForce Go 7200" },␊
222␉{ 0x10DE01D7,␉"GeForce Go 7300" },␊
223␉{ 0x10DE01D8,␉"GeForce Go 7400" },␊
224␉{ 0x10DE01D9,␉"GeForce Go 7400 GS" },␊
225␉{ 0x10DE01DA,␉"Quadro NVS 110M" },␊
226␉{ 0x10DE01DB,␉"Quadro NVS 120M" },␊
227␉{ 0x10DE01DC,␉"Quadro FX 350M" },␊
228␉{ 0x10DE01DD,␉"GeForce 7500 LE" },␊
229␉{ 0x10DE01DE,␉"Quadro FX 350" },␊
230␉{ 0x10DE01DF,␉"GeForce 7300 GS" },␊
231␉// 01E0 - 01EF␉␊
232␉// 01F0 - 01FF␊
233␉{ 0x10DE01F0,␉"GeForce4 MX" },␊
234␉// 0200 - 020F␉␊
235␉// 0210 - 021F␉␊
236␉{ 0x10DE0211,␉"GeForce 6800" },␊
237␉{ 0x10DE0212,␉"GeForce 6800 LE" },␊
238␉{ 0x10DE0215,␉"GeForce 6800 GT" },␊
239␉{ 0x10DE0218,␉"GeForce 6800 XT" },␊
240␉// 0220 - 022F␊
241␉{ 0x10DE0221,␉"GeForce 6200" },␊
242␉{ 0x10DE0222,␉"GeForce 6200 A-LE" },␊
243␉{ 0x10DE0228,␉"NVIDIA NV44M" },␊
244␉// 0230 - 023F␊
245␉// 0240 - 024F␊
246␉{ 0x10DE0240,␉"GeForce 6150" },␊
247␉{ 0x10DE0241,␉"GeForce 6150 LE" },␊
248␉{ 0x10DE0242,␉"GeForce 6100" },␊
249␉{ 0x10DE0243,␉"NVIDIA C51" },␊
250␉{ 0x10DE0244,␉"GeForce Go 6150" },␊
251␉{ 0x10DE0245,␉"Quadro NVS 210S / GeForce 6150LE" },␊
252␉{ 0x10DE0247,␉"GeForce Go 6100" },␊
253␉// 0250 - 025F␊
254␉{ 0x10DE025B,␉"Quadro4 700 XGL" },␊
255␉// 0260 - 026F␊
256␉// 0270 - 027F␊
257␉// 0280 - 028F␊
258␉// 0290 - 029F␊
259␉{ 0x10DE0290,␉"GeForce 7900 GTX" },␊
260␉{ 0x10DE0291,␉"GeForce 7900 GT/GTO" },␊
261␉{ 0x10DE0292,␉"GeForce 7900 GS" },␊
262␉{ 0x10DE0293,␉"GeForce 7950 GX2" },␊
263␉{ 0x10DE0294,␉"GeForce 7950 GX2" },␊
264␉{ 0x10DE0295,␉"GeForce 7950 GT" },␊
265␉{ 0x10DE0298,␉"GeForce Go 7900 GS" },␊
266␉{ 0x10DE0299,␉"GeForce Go 7900 GTX" },␊
267␉{ 0x10DE029A,␉"Quadro FX 2500M" },␊
268␉{ 0x10DE029B,␉"Quadro FX 1500M" },␊
269␉{ 0x10DE029C,␉"Quadro FX 5500" },␊
270␉{ 0x10DE029D,␉"Quadro FX 3500" },␊
271␉{ 0x10DE029E,␉"Quadro FX 1500" },␊
272␉{ 0x10DE029F,␉"Quadro FX 4500 X2" },␊
273␉// 02A0 - 02AF␊
274␉// 02B0 - 02BF␊
275␉// 02C0 - 02CF␊
276␉// 02D0 - 02DF␊
277␉// 02E0 - 02EF␊
278␉{ 0x10DE02E0,␉"GeForce 7600 GT" },␊
279␉{ 0x10DE02E1,␉"GeForce 7600 GS" },␊
280␉{ 0x10DE02E2,␉"GeForce 7300 GT" },␊
281␉{ 0x10DE02E3,␉"GeForce 7900 GS" },␊
282␉{ 0x10DE02E4,␉"GeForce 7950 GT" },␊
283␉// 02F0 - 02FF␊
284␉// 0300 - 030F␊
285␉{ 0x10DE0301,␉"GeForce FX 5800 Ultra" },␊
286␉{ 0x10DE0302,␉"GeForce FX 5800" },␊
287␉{ 0x10DE0308,␉"Quadro FX 2000" },␊
288␉{ 0x10DE0309,␉"Quadro FX 1000" },␊
289␉// 0310 - 031F␊
290␉{ 0x10DE0311,␉"GeForce FX 5600 Ultra" },␊
291␉{ 0x10DE0312,␉"GeForce FX 5600" },␊
292␉{ 0x10DE0314,␉"GeForce FX 5600XT" },␊
293␉{ 0x10DE031A,␉"GeForce FX Go5600" },␊
294␉{ 0x10DE031B,␉"GeForce FX Go5650" },␊
295␉{ 0x10DE031C,␉"Quadro FX Go700" },␊
296␉// 0320 - 032F␊
297␉{ 0x10DE0320,␉"GeForce FX 5200" },␊
298␉{ 0x10DE0321,␉"GeForce FX 5200 Ultra" },␊
299␉{ 0x10DE0322,␉"GeForce FX 5200" },␊
300␉{ 0x10DE0323,␉"GeForce FX 5200 LE" },␊
301␉{ 0x10DE0324,␉"GeForce FX Go5200" },␊
302␉{ 0x10DE0325,␉"GeForce FX Go5250" },␊
303␉{ 0x10DE0326,␉"GeForce FX 5500" },␊
304␉{ 0x10DE0328,␉"GeForce FX Go5200 32M/64M" },␊
305␉{ 0x10DE0329,␉"GeForce FX Go5200" },␊
306␉{ 0x10DE032A,␉"Quadro NVS 55/280 PCI" },␊
307␉{ 0x10DE032B,␉"Quadro FX 500/600 PCI" },␊
308␉{ 0x10DE032C,␉"GeForce FX Go53xx Series" },␊
309␉{ 0x10DE032D,␉"GeForce FX Go5100" },␊
310␉// { 0x10DE032F,␉"NVIDIA NV34GL" },␊
311␉// 0330 - 033F␊
312␉{ 0x10DE0330,␉"GeForce FX 5900 Ultra" },␊
313␉{ 0x10DE0331,␉"GeForce FX 5900" },␊
314␉{ 0x10DE0332,␉"GeForce FX 5900XT" },␊
315␉{ 0x10DE0333,␉"GeForce FX 5950 Ultra" },␊
316␉{ 0x10DE0334,␉"GeForce FX 5900ZT" },␊
317␉{ 0x10DE0338,␉"Quadro FX 3000" },␊
318␉{ 0x10DE033F,␉"Quadro FX 700" },␊
319␉// 0340 - 034F␊
320␉{ 0x10DE0341,␉"GeForce FX 5700 Ultra" },␊
321␉{ 0x10DE0342,␉"GeForce FX 5700" },␊
322␉{ 0x10DE0343,␉"GeForce FX 5700LE" },␊
323␉{ 0x10DE0344,␉"GeForce FX 5700VE" },␊
324␉// { 0x10DE0345,␉"NVIDIA NV36.5" },␊
325␉{ 0x10DE0347,␉"GeForce FX Go5700" },␊
326␉{ 0x10DE0348,␉"GeForce FX Go5700" },␊
327␉// { 0x10DE0349,␉"NVIDIA NV36M Pro" },␊
328␉// { 0x10DE034B,␉"NVIDIA NV36MAP" },␊
329␉{ 0x10DE034C,␉"Quadro FX Go1000" },␊
330␉{ 0x10DE034E,␉"Quadro FX 1100" },␊
331␉// { 0x10DE034F,␉"NVIDIA NV36GL" },␊
332␉// 0350 - 035F␊
333␉// 0360 - 036F␊
334␉// 0370 - 037F␊
335␉// 0380 - 038F␊
336␉{ 0x10DE038B,␉"GeForce 7650 GS" },␊
337␉// 0390 - 039F␊
338␉{ 0x10DE0390,␉"GeForce 7650 GS" },␊
339␉{ 0x10DE0391,␉"GeForce 7600 GT" },␊
340␉{ 0x10DE0392,␉"GeForce 7600 GS" },␊
341␉{ 0x10DE0393,␉"GeForce 7300 GT" },␊
342␉{ 0x10DE0394,␉"GeForce 7600 LE" },␊
343␉{ 0x10DE0395,␉"GeForce 7300 GT" },␊
344␉{ 0x10DE0397,␉"GeForce Go 7700" },␊
345␉{ 0x10DE0398,␉"GeForce Go 7600" },␊
346␉{ 0x10DE0399,␉"GeForce Go 7600 GT"},␊
347␉{ 0x10DE039A,␉"Quadro NVS 300M" },␊
348␉{ 0x10DE039B,␉"GeForce Go 7900 SE" },␊
349␉{ 0x10DE039C,␉"Quadro FX 560M" },␊
350␉{ 0x10DE039E,␉"Quadro FX 560" },␊
351␉// 03A0 - 03AF␊
352␉// 03B0 - 03BF␊
353␉// 03C0 - 03CF␊
354␉// 03D0 - 03DF␊
355␉{ 0x10DE03D0,␉"GeForce 6150SE nForce 430" },␊
356␉{ 0x10DE03D1,␉"GeForce 6100 nForce 405" },␊
357␉{ 0x10DE03D2,␉"GeForce 6100 nForce 400" },␊
358␉{ 0x10DE03D5,␉"GeForce 6100 nForce 420" },␊
359␉{ 0x10DE03D6,␉"GeForce 7025 / nForce 630a" },␊
360␉// 03E0 - 03EF␊
361␉// 03F0 - 03FF␊
362␉// 0400 - 040F␊
363␉{ 0x10DE0400,␉"GeForce 8600 GTS" },␊
364␉{ 0x10DE0401,␉"GeForce 8600 GT" },␊
365␉{ 0x10DE0402,␉"GeForce 8600 GT" },␊
366␉{ 0x10DE0403,␉"GeForce 8600 GS" },␊
367␉{ 0x10DE0404,␉"GeForce 8400 GS" },␊
368␉{ 0x10DE0405,␉"GeForce 9500M GS" },␊
369␉{ 0x10DE0406,␉"GeForce 8300 GS" },␊
370␉{ 0x10DE0407,␉"GeForce 8600M GT" },␊
371␉{ 0x10DE0408,␉"GeForce 9650M GS" },␊
372␉{ 0x10DE0409,␉"GeForce 8700M GT" },␊
373␉{ 0x10DE040A,␉"Quadro FX 370" },␊
374␉{ 0x10DE040B,␉"Quadro NVS 320M" },␊
375␉{ 0x10DE040C,␉"Quadro FX 570M" },␊
376␉{ 0x10DE040D,␉"Quadro FX 1600M" },␊
377␉{ 0x10DE040E,␉"Quadro FX 570" },␊
378␉{ 0x10DE040F,␉"Quadro FX 1700" },␊
379␉// 0410 - 041F␊
380␉{ 0x10DE0410,␉"GeForce GT 330" },␊
381␉// 0420 - 042F␊
382␉{ 0x10DE0420,␉"GeForce 8400 SE" },␊
383␉{ 0x10DE0421,␉"GeForce 8500 GT" },␊
384␉{ 0x10DE0422,␉"GeForce 8400 GS" },␊
385␉{ 0x10DE0423,␉"GeForce 8300 GS" },␊
386␉{ 0x10DE0424,␉"GeForce 8400 GS" },␊
387␉{ 0x10DE0425,␉"GeForce 8600M GS" },␊
388␉{ 0x10DE0426,␉"GeForce 8400M GT" },␊
389␉{ 0x10DE0427,␉"GeForce 8400M GS" },␊
390␉{ 0x10DE0428,␉"GeForce 8400M G" },␊
391␉{ 0x10DE0429,␉"Quadro NVS 140M" },␊
392␉{ 0x10DE042A,␉"Quadro NVS 130M" },␊
393␉{ 0x10DE042B,␉"Quadro NVS 135M" },␊
394␉{ 0x10DE042C,␉"GeForce 9400 GT" },␊
395␉{ 0x10DE042D,␉"Quadro FX 360M" },␊
396␉{ 0x10DE042E,␉"GeForce 9300M G" },␊
397␉{ 0x10DE042F,␉"Quadro NVS 290" },␊
398␉// 0430 - 043F␊
399␉// 0440 - 044F␊
400␉// 0450 - 045F␊
401␉// 0460 - 046F␊
402␉// 0470 - 047F␊
403␉// 0480 - 048F␊
404␉// 0490 - 049F␊
405␉// 04A0 - 04AF␊
406␉// 04B0 - 04BF␊
407␉// 04C0 - 04CF␊
408␉{ 0x10DE04C0,␉"NVIDIA G78" },␊
409␉{ 0x10DE04C1,␉"NVIDIA G78" },␊
410␉{ 0x10DE04C2,␉"NVIDIA G78" },␊
411␉{ 0x10DE04C3,␉"NVIDIA G78" },␊
412␉{ 0x10DE04C4,␉"NVIDIA G78" },␊
413␉{ 0x10DE04C5,␉"NVIDIA G78" },␊
414␉{ 0x10DE04C6,␉"NVIDIA G78" },␊
415␉{ 0x10DE04C7,␉"NVIDIA G78" },␊
416␉{ 0x10DE04C8,␉"NVIDIA G78" },␊
417␉{ 0x10DE04C9,␉"NVIDIA G78" },␊
418␉{ 0x10DE04CA,␉"NVIDIA G78" },␊
419␉{ 0x10DE04CB,␉"NVIDIA G78" },␊
420␉{ 0x10DE04CC,␉"NVIDIA G78" },␊
421␉{ 0x10DE04CD,␉"NVIDIA G78" },␊
422␉{ 0x10DE04CE,␉"NVIDIA G78" },␊
423␉{ 0x10DE04CF,␉"NVIDIA G78" },␊
424␉// 04D0 - 04DF␊
425␉// 04E0 - 04EF␊
426␉// 04F0 - 04FF␊
427␉// 0500 - 050F␊
428␉// 0510 - 051F␊
429␉// 0520 - 052F␊
430␉// 0530 - 053F␊
431␉{ 0x10DE0530,␉"GeForce 7190M / nForce 650M" },␊
432␉{ 0x10DE0531,␉"GeForce 7150M / nForce 630M" },␊
433␉{ 0x10DE0533,␉"GeForce 7000M / nForce 610M" },␊
434␉{ 0x10DE053A,␉"GeForce 7050 PV / nForce 630a" },␊
435␉{ 0x10DE053B,␉"GeForce 7050 PV / nForce 630a" },␊
436␉{ 0x10DE053E,␉"GeForce 7025 / nForce 630a" },␊
437␉// 0540 - 054F␊
438␉// 0550 - 055F␊
439␉// 0560 - 056F␊
440␉// 0570 - 057F␊
441␉// 0580 - 058F␊
442␉// 0590 - 059F␊
443␉// 05A0 - 05AF␊
444␉// 05B0 - 05BF␊
445␉// 05C0 - 05CF␊
446␉// 05D0 - 05DF␊
447␉// 05E0 - 05EF␊
448␉{ 0x10DE05E0,␉"GeForce GTX 295" },␊
449␉{ 0x10DE05E1,␉"GeForce GTX 280" },␊
450␉{ 0x10DE05E2,␉"GeForce GTX 260" },␊
451␉{ 0x10DE05E3,␉"GeForce GTX 285" },␊
452␉{ 0x10DE05E4,␉"NVIDIA GT200" },␊
453␉{ 0x10DE05E5,␉"NVIDIA GT200" },␊
454␉{ 0x10DE05E6,␉"GeForce GTX 275" },␊
455␉{ 0x10DE05E7,␉"Tesla C1060" },␊
456␉{ 0x10DE05E8,␉"NVIDIA GT200" },␊
457␉{ 0x10DE05E9,␉"NVIDIA GT200" },␊
458␉{ 0x10DE05EA,␉"GeForce GTX 260" },␊
459␉{ 0x10DE05EB,␉"GeForce GTX 295" },␊
460␉{ 0x10DE05EC,␉"NVIDIA GT200" },␊
461␉{ 0x10DE05ED,␉"Quadroplex 2200 D2" },␊
462␉{ 0x10DE05EE,␉"NVIDIA GT200" },␊
463␉{ 0x10DE05EF,␉"NVIDIA GT200" },␊
464␉// 05F0 - 05FF␊
465␉{ 0x10DE05F0,␉"NVIDIA GT200" },␊
466␉{ 0x10DE05F1,␉"NVIDIA GT200" },␊
467␉{ 0x10DE05F2,␉"NVIDIA GT200" },␊
468␉{ 0x10DE05F3,␉"NVIDIA GT200" },␊
469␉{ 0x10DE05F4,␉"NVIDIA GT200" },␊
470␉{ 0x10DE05F5,␉"NVIDIA GT200" },␊
471␉{ 0x10DE05F6,␉"NVIDIA GT200" },␊
472␉{ 0x10DE05F7,␉"NVIDIA GT200" },␊
473␉{ 0x10DE05F8,␉"Quadroplex 2200 S4" },␊
474␉{ 0x10DE05F9,␉"Quadro CX" },␊
475␉{ 0x10DE05FA,␉"NVIDIA GT200" },␊
476␉{ 0x10DE05FB,␉"NVIDIA GT200" },␊
477␉{ 0x10DE05FC,␉"NVIDIA GT200" },␊
478␉{ 0x10DE05FD,␉"Quadro FX 5800" },␊
479␉{ 0x10DE05FE,␉"Quadro FX 4800" },␊
480␉{ 0x10DE05FF,␉"Quadro FX 3800" },␊
481␉// 0600 - 060F␊
482␉{ 0x10DE0600,␉"GeForce 8800 GTS 512" },␊
483␉{ 0x10DE0601,␉"GeForce 9800 GT" },␊
484␉{ 0x10DE0602,␉"GeForce 8800 GT" },␊
485␉{ 0x10DE0603,␉"GeForce GT 230" },␊
486␉{ 0x10DE0604,␉"GeForce 9800 GX2" },␊
487␉{ 0x10DE0605,␉"GeForce 9800 GT" },␊
488␉{ 0x10DE0606,␉"GeForce 8800 GS" },␊
489␉{ 0x10DE0607,␉"GeForce GTS 240" },␊
490␉{ 0x10DE0608,␉"GeForce 9800M GTX" },␊
491␉{ 0x10DE0609,␉"GeForce 8800M GTS" },␊
492␉{ 0x10DE060A,␉"GeForce GTX 280M" },␊
493␉{ 0x10DE060B,␉"GeForce 9800M GT" },␊
494␉{ 0x10DE060C,␉"GeForce 8800M GTX" },␊
495␉{ 0x10DE060D,␉"GeForce 8800 GS" },␊
496␉{ 0x10DE060F,␉"GeForce GTX 285M" },␊
497␉// 0610 - 061F␊
498␉{ 0x10DE0610,␉"GeForce 9600 GSO" },␊
499␉{ 0x10DE0611,␉"GeForce 8800 GT" },␊
500␉{ 0x10DE0612,␉"GeForce 9800 GTX" },␊
501␉{ 0x10DE0613,␉"GeForce 9800 GTX+" },␊
502␉{ 0x10DE0614,␉"GeForce 9800 GT" },␊
503␉{ 0x10DE0615,␉"GeForce GTS 250" },␊
504␉{ 0x10DE0617,␉"GeForce 9800M GTX" },␊
505␉/* START */␊
506␉{ 0x10DE0618,␉"GeForce GTX 260M" },␊
507␉// { 0x10DE0618,␉0x1025028E,␉"GeForce GTX 260M" },␊
508␉// { 0x10DE0618,␉0x102802A1,␉"GeForce GTX 260M" },␊
509␉// { 0x10DE0618,␉0x102802A2,␉"GeForce GTX 260M" },␊
510␉// { 0x10DE0618,␉0x10431A52,␉"GeForce GTX 260M" },␊
511␉// { 0x10DE0618,␉0x10432028,␉"GeForce GTX 260M" },␊
512␉// { 0x10DE0618,␉0x1043202B,␉"Asus GTX 680" }, // Subsystem Id: 1043 202B Asus GTX 680␊
513␉// { 0x10DE0618,␉0x10432033,␉"GeForce GTX 260M" },␊
514␉// { 0x10DE0618,␉0x15580481,␉"GeForce GTX 260M" },␊
515␉// { 0x10DE0618,␉0x15580577,␉"GeForce GTX 260M" },␊
516␉// { 0x10DE0618,␉0x15580860,␉"GeForce GTX 260M" },␊
517␉/* END */␊
518␉{ 0x10DE0619,␉"Quadro FX 4700 X2" },␊
519␉{ 0x10DE061A,␉"Quadro FX 3700" },␊
520␉{ 0x10DE061B,␉"Quadro VX 200" },␊
521␉{ 0x10DE061C,␉"Quadro FX 3600M" },␊
522␉{ 0x10DE061D,␉"Quadro FX 2800M" },␊
523␉{ 0x10DE061E,␉"Quadro FX 3700M" },␊
524␉{ 0x10DE061F,␉"Quadro FX 3800M" },␊
525␉// 0620 - 062F␊
526␉{ 0x10DE0620,␉"NVIDIA G94" }, // GeForce 8100/8200/8300␊
527␉{ 0x10DE0621,␉"GeForce GT 230" },␊
528␉{ 0x10DE0622,␉"GeForce 9600 GT" },␊
529␉{ 0x10DE0623,␉"GeForce 9600 GS" },␊
530␉{ 0x10DE0624,␉"NVIDIA G94" },␊
531␉{ 0x10DE0625,␉"GeForce 9600 GSO 512"},␊
532␉{ 0x10DE0626,␉"GeForce GT 130" },␊
533␉{ 0x10DE0627,␉"GeForce GT 140" },␊
534␉{ 0x10DE0628,␉"GeForce 9800M GTS" },␊
535␉{ 0x10DE0629,␉"NVIDIA G94" },␊
536␉{ 0x10DE062A,␉"GeForce 9700M GTS" },␊
537␉{ 0x10DE062B,␉"GeForce 9800M GS" },␊
538␉{ 0x10DE062C,␉"GeForce 9800M GTS" },␊
539␉{ 0x10DE062D,␉"GeForce 9600 GT" },␊
540␉{ 0x10DE062E,␉"GeForce 9600 GT" },␊
541␉{ 0x10DE062F,␉"GeForce 9800 S" },␊
542␉// 0630 - 063F␊
543␉{ 0x10DE0630,␉"NVIDIA G94" },␊
544␉{ 0x10DE0631,␉"GeForce GTS 160M" },␊
545␉{ 0x10DE0632,␉"GeForce GTS 150M" },␊
546␉{ 0x10DE0633,␉"NVIDIA G94" },␊
547␉{ 0x10DE0634,␉"NVIDIA G94" },␊
548␉{ 0x10DE0635,␉"GeForce 9600 GSO" },␊
549␉{ 0x10DE0636,␉"NVIDIA G94" },␊
550␉{ 0x10DE0637,␉"GeForce 9600 GT" },␊
551␉{ 0x10DE0638,␉"Quadro FX 1800" },␊
552␉{ 0x10DE0639,␉"NVIDIA G94" },␊
553␉{ 0x10DE063A,␉"Quadro FX 2700M" },␊
554␉{ 0x10DE063B,␉"NVIDIA G94" },␊
555␉{ 0x10DE063C,␉"NVIDIA G94" },␊
556␉{ 0x10DE063D,␉"NVIDIA G94" },␊
557␉{ 0x10DE063E,␉"NVIDIA G94" },␊
558␉{ 0x10DE063F,␉"NVIDIA G94" },␊
559␉// 0640 - 064F␊
560␉{ 0x10DE0640,␉"GeForce 9500 GT" },␊
561␉{ 0x10DE0641,␉"GeForce 9400 GT" },␊
562␉{ 0x10DE0642,␉"GeForce 8400 GS" },␊
563␉{ 0x10DE0643,␉"GeForce 9500 GT" },␊
564␉{ 0x10DE0644,␉"GeForce 9500 GS" },␊
565␉{ 0x10DE0645,␉"GeForce 9500 GS" },␊
566␉{ 0x10DE0646,␉"GeForce GT 120" },␊
567␉{ 0x10DE0647,␉"GeForce 9600M GT" },␊
568␉{ 0x10DE0648,␉"GeForce 9600M GS" },␊
569␉{ 0x10DE0649,␉"GeForce 9600M GT" },␊
570␉{ 0x10DE064A,␉"GeForce 9700M GT" },␊
571␉{ 0x10DE064B,␉"GeForce 9500M G" },␊
572␉{ 0x10DE064C,␉"GeForce 9650M GT" },␊
573␉// 0650 - 065F␊
574␉{ 0x10DE0650,␉"NVIDIA G96-825" },␊
575␉{ 0x10DE0651,␉"GeForce G 110M" },␊
576␉{ 0x10DE0652,␉"GeForce GT 130M" },␊
577␉{ 0x10DE0653,␉"GeForce GT 120M" },␊
578␉{ 0x10DE0654,␉"GeForce GT 220M" },␊
579␉{ 0x10DE0655,␉"GeForce GT 120" },␊
580␉{ 0x10DE0656,␉"GeForce 9650 S" },␊
581␉{ 0x10DE0657,␉"NVIDIA G96" },␊
582␉{ 0x10DE0658,␉"Quadro FX 380" },␊
583␉{ 0x10DE0659,␉"Quadro FX 580" },␊
584␉{ 0x10DE065A,␉"Quadro FX 1700M" },␊
585␉{ 0x10DE065B,␉"GeForce 9400 GT" },␊
586␉{ 0x10DE065C,␉"Quadro FX 770M" },␊
587␉{ 0x10DE065D,␉"NVIDIA G96" },␊
588␉{ 0x10DE065E,␉"NVIDIA G96" },␊
589␉{ 0x10DE065F,␉"GeForce G210" },␊
590␉// 0660 - 066F␊
591␉// 0670 - 067F␊
592␉// 0680 - 068F␊
593␉// 0690 - 069F␊
594␉// 06A0 - 06AF␊
595␉{ 0x10DE06A0,␉"NVIDIA GT214" },␊
596␉// 06B0 - 06BF␊
597␉{ 0x10DE06B0,␉"NVIDIA GT214" },␊
598␉// 06C0 - 06CF␊
599␉{ 0x10DE06C0,␉"GeForce GTX 480" },␊
600␉{ 0x10DE06C3,␉"GeForce GTX D12U" },␊
601␉{ 0x10DE06C4,␉"GeForce GTX 465" },␊
602␉{ 0x10DE06CA,␉"GeForce GTX 480M" },␊
603␉{ 0x10DE06CD,␉"GeForce GTX 470" },␊
604␉// 06D0 - 06DF␊
605␉/* START */␊
606␉{ 0x10DE06D1,␉"Tesla C2050 / C2070" },␊
607␉// { 0x10DE06D1,␉0x10DE0771,␉"Tesla C2050" },␊
608␉// { 0x10DE06D1,␉0x10DE0772,␉"Tesla C2070" },␊
609␉{ 0x10DE06D2,␉"Tesla M2070 / X2070" },␊
610␉// { 0x10DE06D2,␉0x10DE0774,␉"Tesla M2070" },␊
611␉// { 0x10DE06D2,␉0x10DE0830,␉"Tesla M2070" },␊
612␉// { 0x10DE06D2,␉0x10DE0842,␉"Tesla M2070" },␊
613␉// { 0x10DE06D2,␉0x10DE088F,␉"Tesla X2070" },␊
614␉// { 0x10DE06D2,␉0x10DE0908,␉"Tesla M2070" },␊
615␉/* END */␊
616␉{ 0x10DE06D8,␉"Quadro 6000" },␊
617␉{ 0x10DE06D9,␉"Quadro 5000" },␊
618␉{ 0x10DE06DA,␉"Quadro 5000M" },␊
619␉{ 0x10DE06DC,␉"Quadro 6000" },␊
620␉{ 0x10DE06DD,␉"Quadro 4000" },␊
621␉{ 0x10DE06DE,␉"Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
622␉{ 0x10DE06DE,␉"Tesla M2070" },␉// TODO: sub-device id: ?␉␊
623␉{ 0x10DE06DF,␉"Tesla M2070-Q" },␊
624␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
625␉// 06E0 - 06EF␊
626␉{ 0x10DE06E0,␉"GeForce 9300 GE" },␊
627␉{ 0x10DE06E1,␉"GeForce 9300 GS" },␊
628␉{ 0x10DE06E2,␉"GeForce 8400" },␊
629␉{ 0x10DE06E3,␉"GeForce 8400 SE" },␊
630␉{ 0x10DE06E4,␉"GeForce 8400 GS" },␊
631␉{ 0x10DE06E5,␉"GeForce 9300M GS" },␊
632␉{ 0x10DE06E6,␉"GeForce G100" },␊
633␉{ 0x10DE06E7,␉"GeForce 9300 SE" },␊
634␉{ 0x10DE06E8,␉"GeForce 9200M GS" },␊
635␉{ 0x10DE06E9,␉"GeForce 9300M GS" },␊
636␉{ 0x10DE06EA,␉"Quadro NVS 150M" },␊
637␉{ 0x10DE06EB,␉"Quadro NVS 160M" },␊
638␉{ 0x10DE06EC,␉"GeForce G 105M" },␊
639␉{ 0x10DE06ED,␉"NVIDIA G98" },␊
640␉{ 0x10DE06EF,␉"GeForce G 103M" },␊
641␉// 06F0 - 06FF␊
642␉{ 0x10DE06F0,␉"NVIDIA G98" },␊
643␉{ 0x10DE06F1,␉"GeForce G105M" },␊
644␉{ 0x10DE06F2,␉"NVIDIA G98" },␊
645␉{ 0x10DE06F3,␉"NVIDIA G98" },␊
646␉{ 0x10DE06F4,␉"NVIDIA G98" },␊
647␉{ 0x10DE06F5,␉"NVIDIA G98" },␊
648␉{ 0x10DE06F6,␉"NVIDIA G98" },␊
649␉{ 0x10DE06F7,␉"NVIDIA G98" },␊
650␉{ 0x10DE06F8,␉"Quadro NVS 420" },␊
651␉{ 0x10DE06F9,␉"Quadro FX 370 LP" },␊
652␉{ 0x10DE06FA,␉"Quadro NVS 450" },␊
653␉{ 0x10DE06FB,␉"Quadro FX 370M" },␊
654␉{ 0x10DE06FC,␉"NVIDIA G98" },␊
655␉{ 0x10DE06FD,␉"Quadro NVS 295" },␊
656␉{ 0x10DE06FE,␉"NVIDIA G98" },␊
657␉{ 0x10DE06FF,␉"HICx16 + Graphics" },␊
658␉// 0700 - 070F␊
659␉// 0710 - 071F␊
660␉// 0720 - 072F␊
661␉// 0730 - 073F␊
662␉// 0740 - 074F␊
663␉// 0750 - 075F␊
664␉// 0760 - 076F␊
665␉// 0770 - 077F␊
666␉// 0780 - 078F␊
667␉// 0790 - 079F␊
668␉// 07A0 - 07AF␊
669␉// 07B0 - 07BF␊
670␉// 07C0 - 07CF␊
671␉// 07D0 - 07DF␊
672␉// 07E0 - 07EF␊
673␉{ 0x10DE07E0,␉"GeForce 7150 / nForce 630i" },␊
674␉{ 0x10DE07E1,␉"GeForce 7100 / nForce 630i" },␊
675␉{ 0x10DE07E2,␉"GeForce 7050 / nForce 630i" },␊
676␉{ 0x10DE07E3,␉"GeForce 7050 / nForce 610i" },␊
677␉{ 0x10DE07E5,␉"GeForce 7050 / nForce 620i" },␊
678␉// 07F0 - 07FF␊
679␉// 0800 - 080F␊
680␉// 0810 - 081F␊
681␉// 0820 - 082F␊
682␉// 0830 - 083F␊
683␉// 0840 - 084F␊
684␉{ 0x10DE0840,␉"GeForce 8200M" },␊
685␉{ 0x10DE0844,␉"GeForce 9100M G" },␊
686␉{ 0x10DE0845,␉"GeForce 8200M G" },␊
687␉{ 0x10DE0846,␉"GeForce 9200" },␊
688␉{ 0x10DE0847,␉"GeForce 9100" },␊
689␉{ 0x10DE0848,␉"GeForce 8300" },␊
690␉{ 0x10DE0849,␉"GeForce 8200" },␊
691␉{ 0x10DE084A,␉"nForce 730a" },␊
692␉{ 0x10DE084B,␉"GeForce 9200" },␊
693␉{ 0x10DE084C,␉"nForce 980a/780a SLI" },␊
694␉{ 0x10DE084D,␉"nForce 750a SLI" },␊
695␉{ 0x10DE084F,␉"GeForce 8100 / nForce 720a" },␊
696␉// 0850 - 085F␊
697␉// 0860 - 086F␊
698␉{ 0x10DE0860,␉"GeForce 9300" },␊
699␉{ 0x10DE0861,␉"GeForce 9400" },␊
700␉{ 0x10DE0862,␉"GeForce 9400M G" },␊
701␉{ 0x10DE0863,␉"GeForce 9400M" },␊
702␉{ 0x10DE0864,␉"GeForce 9300" },␊
703␉{ 0x10DE0865,␉"GeForce 9300" },␊
704␉{ 0x10DE0866,␉"GeForce 9400M G" },␊
705␉{ 0x10DE0867,␉"GeForce 9400" },␊
706␉{ 0x10DE0868,␉"nForce 760i SLI" },␊
707␉{ 0x10DE0869,␉"GeForce 9400" },␊
708␉{ 0x10DE086A,␉"GeForce 9400" },␊
709␉{ 0x10DE086C,␉"GeForce 9300 / nForce 730i" },␊
710␉{ 0x10DE086D,␉"GeForce 9200" },␊
711␉{ 0x10DE086E,␉"GeForce 9100M G" },␊
712␉{ 0x10DE086F,␉"GeForce 8200M G" },␊
713␉// 0870 - 087F␊
714␉{ 0x10DE0870,␉"GeForce 9400M" },␊
715␉{ 0x10DE0871,␉"GeForce 9200" },␊
716␉{ 0x10DE0872,␉"GeForce G102M" },␊
717␉{ 0x10DE0873,␉"GeForce G102M" },␊
718␉{ 0x10DE0874,␉"ION 9300M" },␉␊
719␉{ 0x10DE0876,␉"ION 9400M" },␊
720␉{ 0x10DE087A,␉"GeForce 9400" },␊
721␉{ 0x10DE087D,␉"ION 9400M" },␊
722␉{ 0x10DE087E,␉"ION LE" },␊
723␉{ 0x10DE087F,␉"ION LE" },␊
724␉// 0880 - 088F␊
725␉// 0890 - 089F␊
726␉// 08A0 - 08AF␊
727␉{ 0x10DE08A0,␉"GeForce 320M" },␊
728␉// { 0x10DE08A1,␉"NVIDIA MCP89-MZT" },␊
729␉// { 0x10DE08A2,␉"NVIDIA MCP89-EPT" },␊
730␉{ 0x10DE08A3,␉"GeForce 320M" },␊
731␉{ 0x10DE08A4,␉"GeForce 320M" },␊
732␉{ 0x10DE08A5,␉"GeForce 320M" },␊
733␉// 08B0 - 08BF␊
734␉// { 0x10DE08B0,␉"MCP83 MMD" },␊
735␉{ 0x10DE08B1,␉"GeForce 300M" },␊
736␉// { 0x10DE08B2,␉"NVIDIA MCP83-MJ" },␊
737␉// { 0x10DE08B3,␉"NVIDIA MCP89 MM9" },␊
738␉// 08C0 - 08CF␊
739␉// 08D0 - 08DF␊
740␉// 08E0 - 08EF␊
741␉// 08F0 - 08FF␊
742␉// 0900 - 090F␊
743␉// 0910 - 091F␊
744␉// 0920 - 092F␊
745␉// 0930 - 093F␊
746␉// 0940 - 094F␊
747␉// 0950 - 095F␊
748␉// 0960 - 096F␊
749␉// 0970 - 097F␊
750␉// 0980 - 098F␊
751␉// 0990 - 099F␊
752␉// 09A0 - 09AF␊
753␉// 09B0 - 09BF␊
754␉// 09C0 - 09CF␊
755␉// 09D0 - 09DF␊
756␉// 09E0 - 09EF␊
757␉// 09F0 - 09FF␊
758␉// 0A00 - 0A0F␊
759␉// { 0x10DE0A00,␉"NVIDIA GT212" },␊
760␉// 0A10 - 0A1F␊
761␉// { 0x10DE0A10,␉"NVIDIA GT212" },␊
762␉// 0A20 - 0A2F␊
763␉{ 0x10DE0A20,␉"GeForce GT 220" },␊
764␉// { 0x10DE0A21,␉"NVIDIA D10M2-20" },␊
765␉{ 0x10DE0A22,␉"GeForce 315" },␊
766␉{ 0x10DE0A23,␉"GeForce 210" },␊
767␉{ 0x10DE0A26,␉"GeForce 405" },␊
768␉{ 0x10DE0A27,␉"GeForce 405" },␊
769␉{ 0x10DE0A28,␉"GeForce GT 230M" },␊
770␉{ 0x10DE0A29,␉"GeForce GT 330M" },␊
771␉{ 0x10DE0A2A,␉"GeForce GT 230M" },␊
772␉{ 0x10DE0A2B,␉"GeForce GT 330M" },␊
773␉{ 0x10DE0A2C,␉"NVS 5100M" },␊
774␉{ 0x10DE0A2D,␉"GeForce GT 320M" },␉␊
775␉// 0A30 - 0A3F␊
776␉// { 0x10DE0A30,␉"NVIDIA GT216" },␊
777␉{ 0x10DE0A32,␉"GeForce GT 415" },␊
778␉{ 0x10DE0A34,␉"GeForce GT 240M" },␊
779␉{ 0x10DE0A35,␉"GeForce GT 325M" },␊
780␉{ 0x10DE0A38,␉"Quadro 400" },␊
781␉{ 0x10DE0A3C,␉"Quadro FX 880M" },␊
782␉// { 0x10DE0A3D,␉"NVIDIA N10P-ES" },␊
783␉// { 0x10DE0A3F,␉"NVIDIA GT216-INT" },␊
784␉// 0A40 - 0A4F␊
785␉// 0A50 - 0A5F␊
786␉// 0A60 - 0A6F␊
787␉{ 0x10DE0A60,␉"GeForce G210" },␊
788␉// { 0x10DE0A61,␉"NVIDIA NVS 2100" },␊
789␉{ 0x10DE0A62,␉"GeForce 205" },␊
790␉{ 0x10DE0A63,␉"GeForce 310" },␊
791␉{ 0x10DE0A64,␉"ION" },␊
792␉{ 0x10DE0A65,␉"GeForce 210" },␊
793␉{ 0x10DE0A66,␉"GeForce 310" },␊
794␉{ 0x10DE0A67,␉"GeForce 315" },␊
795␉{ 0x10DE0A68,␉"GeForce G105M" },␊
796␉{ 0x10DE0A69,␉"GeForce G105M" },␊
797␉{ 0x10DE0A6A,␉"NVS 2100M" },␊
798␉{ 0x10DE0A6C,␉"NVS 3100M" },␊
799␉{ 0x10DE0A6E,␉"GeForce 305M" },␊
800␉{ 0x10DE0A6F,␉"ION" },␉␊
801␉// 0A70 - 0A7F␊
802␉{ 0x10DE0A70,␉"GeForce 310M" },␊
803␉{ 0x10DE0A71,␉"GeForce 305M" },␊
804␉{ 0x10DE0A72,␉"GeForce 310M" },␊
805␉{ 0x10DE0A73,␉"GeForce 305M" },␊
806␉{ 0x10DE0A74,␉"GeForce G210M" },␊
807␉{ 0x10DE0A75,␉"GeForce G310M" },␊
808␉{ 0x10DE0A76,␉"ION" },␊
809␉{ 0x10DE0A78,␉"Quadro FX 380 LP" },␊
810␉// { 0x10DE0A79,␉"N12M-NS-S" },␊
811␉{ 0x10DE0A7A,␉"GeForce 315M" },␊
812␉{ 0x10DE0A7B,␉"GeForce 505" },␊
813␉{ 0x10DE0A7C,␉"Quadro FX 380M" },␊
814␉// { 0x10DE0A7D,␉"NVIDIA GT218-ES" },␊
815␉// { 0x10DE0A7E,␉"NVIDIA GT218-INT-S" },␊
816␉// { 0x10DE0A7F,␉"NVIDIA GT218-INT-B" },␊
817␉// 0A80 - 0A8F␊
818␉// 0A90 - 0A9F␊
819␉// 0AA0 - 0AAF␊
820␉// 0AB0 - 0ABF␊
821␉// 0AC0 - 0ACF␊
822␉// 0AD0 - 0ADF␊
823␉// 0AE0 - 0AEF␊
824␉// 0AF0 - 0AFF␊
825␉// 0B00 - 0B0F␊
826␉// 0B10 - 0B1F␊
827␉// 0B20 - 0B2F␊
828␉// 0B30 - 0B3F␊
829␉// 0B40 - 0B4F␊
830␉// 0B50 - 0B5F␊
831␉// 0B60 - 0B6F␊
832␉// 0B70 - 0B7F␊
833␉// 0B80 - 0B8F␊
834␉// 0B90 - 0B9F␊
835␉// 0BA0 - 0BAF␊
836␉// 0BB0 - 0BBF␊
837␉// 0BC0 - 0BCF␊
838␉// 0BD0 - 0BDF␊
839␉// 0BE0 - 0BEF␊
840␉// 0BF0 - 0BFF␊
841␉// 0C00 - 0C0F␊
842␉// 0C10 - 0C1F␊
843␉// 0C20 - 0C2F␊
844␉// 0C30 - 0C3F␊
845␉// 0C40 - 0C4F␊
846␉// 0C50 - 0C5F␊
847␉// 0C60 - 0C6F␊
848␉// 0C70 - 0C7F␊
849␉// 0C80 - 0C8F␊
850␉// 0C90 - 0C9F␊
851␉// 0CA0 - 0CAF␊
852␉{ 0x10DE0CA0,␉"GeForce GT 330 " },␊
853␉{ 0x10DE0CA2,␉"GeForce GT 320" },␊
854␉{ 0x10DE0CA3,␉"GeForce GT 240" },␊
855␉{ 0x10DE0CA4,␉"GeForce GT 340" },␊
856␉{ 0x10DE0CA5,␉"GeForce GT 220" },␊
857␉{ 0x10DE0CA7,␉"GeForce GT 330" },␊
858␉{ 0x10DE0CA8,␉"GeForce GTS 260M" },␊
859␉{ 0x10DE0CA9,␉"GeForce GTS 250M" },␊
860␉{ 0x10DE0CAC,␉"GeForce GT 220" },␊
861␉// { 0x10DE0CAD,␉"NVIDIA N10E-ES" },␊
862␉// { 0x10DE0CAE,␉"NVIDIA GT215-INT" },␊
863␉{ 0x10DE0CAF,␉"GeForce GT 335M" },␊
864␉// 0CB0 - 0CBF␉␊
865␉{ 0x10DE0CB0,␉"GeForce GTS 350M" },␊
866␉{ 0x10DE0CB1,␉"GeForce GTS 360M" },␊
867␉{ 0x10DE0CBC,␉"Quadro FX 1800M" },␊
868␉// 0CC0 - 0CCF␊
869␉// 0CD0 - 0CDF␊
870␉// 0CE0 - 0CEF␊
871␉// 0CF0 - 0CFF␊
872␉// 0D00 - 0D0F␊
873␉// 0D10 - 0D1F␊
874␉// 0D20 - 0D2F␊
875␉// 0D30 - 0D3F␊
876␉// 0D40 - 0D4F␊
877␉// 0D50 - 0D5F␊
878␉// 0D60 - 0D6F␊
879␉// 0D70 - 0D7F␊
880␉// 0D80 - 0D8F␊
881␉// 0D90 - 0D9F␊
882␉// 0DA0 - 0DAF␊
883␉// 0DB0 - 0DBF␊
884␉// 0DC0 - 0DCF␊
885␉{ 0x10DE0DC0,␉"GeForce GT 440" },␊
886␉// { 0x10DE0DC1,␉"D12-P1-35" },␊
887␉// { 0x10DE0DC2,␉"D12-P1-35" },␊
888␉{ 0x10DE0DC4,␉"GeForce GTS 450" },␊
889␉{ 0x10DE0DC5,␉"GeForce GTS 450" },␊
890␉{ 0x10DE0DC6,␉"GeForce GTS 450" },␊
891␉// { 0x10DE0DCA,␉"GF10x" },␊
892␉// { 0x10DE0DCC,␉"N12E-GS" },␊
893␉{ 0x10DE0DCD,␉"GeForce GT 555M" },␊
894␉{ 0x10DE0DCE,␉"GeForce GT 555M" },␊
895␉// { 0x10DE0DCF,␉"N12P-GT-B" },␊
896␉// 0DD0 - 0DDF␉␊
897␉// { 0x10DE0DD0,␉"N11E-GT" },␊
898␉{ 0x10DE0DD1,␉"GeForce GTX 460M" },␊
899␉{ 0x10DE0DD2,␉"GeForce GT 445M" },␊
900␉{ 0x10DE0DD3,␉"GeForce GT 435M" },␊
901␉{ 0x10DE0DD6,␉"GeForce GT 550M" },␊
902␉{ 0x10DE0DD8,␉"Quadro 2000" },␊
903␉{ 0x10DE0DDA,␉"Quadro 2000M" },␊
904␉// { 0x10DE0DDE,␉"GF106-ES" },␊
905␉// { 0x10DE0DDF,␉"GF106-INT" },␊
906␉// 0DE0 - 0DEF␊
907␉{ 0x10DE0DE0,␉"GeForce GT 440" },␊
908␉{ 0x10DE0DE1,␉"GeForce GT 430" },␊
909␉{ 0x10DE0DE2,␉"GeForce GT 420" },␊
910␉{ 0x10DE0DE4,␉"GeForce GT 520" },␊
911␉{ 0x10DE0DE5,␉"GeForce GT 530" },␊
912␉{ 0x10DE0DE8,␉"GeForce GT 620M" },␊
913␉{ 0x10DE0DE9,␉"GeForce GT 630M" },␊
914␉{ 0x10DE0DEA,␉"GeForce GT 610M" },␊
915␉{ 0x10DE0DEB,␉"GeForce GT 555M" },␊
916␉{ 0x10DE0DEC,␉"GeForce GT 525M" },␊
917␉{ 0x10DE0DED,␉"GeForce GT 520M" },␊
918␉{ 0x10DE0DEE,␉"GeForce GT 415M" },␊
919␉// { 0x10DE0DEF,␉"N13P-NS1-A1" },␊
920␉// 0DF0 - 0DFF␉␊
921␉{ 0x10DE0DF0,␉"GeForce GT 425M" },␊
922␉{ 0x10DE0DF1,␉"GeForce GT 420M" },␊
923␉{ 0x10DE0DF2,␉"GeForce GT 435M" },␊
924␉{ 0x10DE0DF3,␉"GeForce GT 420M" },␊
925␉{ 0x10DE0DF4,␉"GeForce GT 540M" },␊
926␉{ 0x10DE0DF5,␉"GeForce GT 525M" },␊
927␉{ 0x10DE0DF6,␉"GeForce GT 550M" },␊
928␉{ 0x10DE0DF7,␉"GeForce GT 520M" },␊
929␉{ 0x10DE0DF8,␉"Quadro 600" },␊
930␉{ 0x10DE0DF9,␉"Quadro 500M" },␊
931␉{ 0x10DE0DFA,␉"Quadro 1000M" },␊
932␉{ 0x10DE0DFC,␉"NVS 5200M" },␊
933␉// { 0x10DE0DFE,␉"GF108 ES" },␊
934␉// { 0x10DE0DFF,␉"GF108 INT" },␊
935␉// 0E00 - 0E0F␊
936␉// 0E10 - 0E1F␊
937␉// 0E20 - 0E2F␊
938␉{ 0x10DE0E21,␉"D12U-25" },␊
939␉{ 0x10DE0E22,␉"GeForce GTX 460" },␊
940␉{ 0x10DE0E23,␉"GeForce GTX 460 SE" },␊
941␉{ 0x10DE0E24,␉"GeForce GTX 460" },␊
942␉// { 0x10DE0E25,␉"D12U-50" },␊
943␉{ 0x10DE0E28,␉"GeForce GTX 460" },␊
944␉// 0E30 - 0E3F␊
945␉{ 0x10DE0E30,␉"GeForce GTX 470M" },␊
946␉{ 0x10DE0E31,␉"GeForce GTX 485M" },␊
947␉// { 0x10DE0E32,␉"N12E-GT" },␊
948␉{ 0x10DE0E38,␉"GF104GL" },␊
949␉{ 0x10DE0E3A,␉"Quadro 3000M" },␊
950␉{ 0x10DE0E3B,␉"Quadro 4000M" },␊
951␉// { 0x10DE0E3E,␉"GF104-ES" },␊
952␉// { 0x10DE0E3F,␉"GF104-INT" },␊
953␉// 0E40 - 0E4F␊
954␉// 0E50 - 0E5F␊
955␉// 0E60 - 0E6F␊
956␉// 0E70 - 0E7F␊
957␉// 0E80 - 0E8F␊
958␉// 0E90 - 0E9F␊
959␉// 0EA0 - 0EAF␊
960␉// 0EB0 - 0EBF␊
961␉// 0EC0 - 0ECF␊
962␉// 0ED0 - 0EDF␊
963␉// 0EE0 - 0EEF␊
964␉// 0EF0 - 0EFF␊
965␉// 0F00 - 0F0F␊
966␉// 0F10 - 0F1F␊
967␉// 0F20 - 0F2F␊
968␉// 0F30 - 0F3F␊
969␉// 0F40 - 0F4F␊
970␉// 0F50 - 0F5F␊
971␉// 0F60 - 0F6F␊
972␉// 0F70 - 0F7F␊
973␉// 0F80 - 0F8F␊
974␉// 0F90 - 0F9F␊
975␉// 0FA0 - 0FAF␊
976␉// 0FB0 - 0FBF␊
977␉// 0FC0 - 0FCF␊
978␉// 0FD0 - 0FDF␊
979␉{ 0x10DE0FD1,␉"GeForce GT 650M" },␊
980␉{ 0x10DE0FD2,␉"GeForce GT 640M" },␊
981␉{ 0x10DE0FD4,␉"GeForce GTX 660M" },␊
982␉// { 0x10DE0FDB,␉"GK107-ESP-A1" },␊
983␉// 0FE0 - 0FEF␊
984␉// 0FF0 - 0FFF␊
985␉// 1000 - 100F␊
986␉// 1010 - 101F␊
987␉// 1020 - 102F␊
988␉// 1030 - 103F␊
989␉// 1040 - 104F␊
990␉{ 0x10DE1040,␉"GeForce GT 520" },␊
991␉// { 0x10DE1041,␉"D13M1-45" },␊
992␉{ 0x10DE1042,␉"GeForce 510" },␊
993␉{ 0x10DE1048,␉"GeForce 605" },␊
994␉{ 0x10DE1049,␉"GeForce GT 620" },␊
995␉// 1050 - 105F␊
996␉{ 0x10DE1050,␉"GeForce GT 520M" },␊
997␉{ 0x10DE1051,␉"GeForce GT 520MX" },␊
998␉{ 0x10DE1052,␉"GeForce GT 520M" },␊
999␉{ 0x10DE1054,␉"GeForce GT 410M" },␊
1000␉{ 0x10DE1055,␉"GeForce 410M" },␊
1001␉{ 0x10DE1056,␉"Quadro NVS 4200M" },␊
1002␉{ 0x10DE1057,␉"Quadro NVS 4200M" },␊
1003␉{ 0x10DE1058,␉"GeForce 610M" },␊
1004␉{ 0x10DE1059,␉"GeForce 610M" },␊
1005␉{ 0x10DE105A,␉"GeForce 610M" },␊
1006␉// 1060 - 106F␊
1007␉// 1070 - 107F␊
1008␉// { 0x10DE107D,␉"GF119" },␊
1009␉// { 0x10DE107E,␉"GF119-INT" },␊
1010␉// { 0x10DE107F,␉"GF119-ES" },␊
1011␉// 1080 - 108F␊
1012␉{ 0x10DE1080,␉"GeForce GTX 580" },␊
1013␉{ 0x10DE1081,␉"GeForce GTX 570" },␊
1014␉{ 0x10DE1082,␉"GeForce GTX 560 Ti" },␊
1015␉{ 0x10DE1083,␉"D13U" },␊
1016␉{ 0x10DE1084,␉"GeForce GTX 560" },␊
1017␉{ 0x10DE1086,␉"GeForce GTX 570" },␊
1018␉{ 0x10DE1087,␉"GeForce GTX 560 Ti-448" },␊
1019␉{ 0x10DE1088,␉"GeForce GTX 590" },␊
1020␉{ 0x10DE1089,␉"GeForce GTX 580" },␊
1021␉{ 0x10DE108B,␉"GeForce GTX 590" },␊
1022␉// { 0x10DE108C,␉"D13U" },␊
1023␉{ 0x10DE108E,␉"Tesla C2090" },␊
1024␉// 1090 - 109F␊
1025␉{ 0x10DE1091,␉"Tesla M2090" },␊
1026␉{ 0x10DE1094,␉"Tesla M2075 Dual-Slot Computing Processor Module" },␊
1027␉{ 0x10DE1096,␉"Tesla C2075" },␊
1028␉// { 0x10DE1098,␉"D13U" },␊
1029␉{ 0x10DE109A,␉"Quadro 5010M" },␊
1030␉{ 0x10DE109B,␉"Quadro 7000" },␊
1031␉// 10A0 - 10AF␊
1032␉// 10B0 - 10BF␊
1033␉// 10C0 - 10CF␊
1034␉{ 0x10DE10C0,␉"GeForce 9300 GS" },␊
1035␉{ 0x10DE10C3,␉"GeForce 8400 GS" },␊
1036␉{ 0x10DE10C4,␉"NVIDIA ION" },␊
1037␉{ 0x10DE10C5,␉"GeForce 405" },␊
1038␉// 10D0 - 10DF␊
1039␉{ 0x10DE10D8,␉"NVS 300" },␊
1040␉// 10E0 - 10EF␊
1041␉// 10F0 - 10FF␊
1042␉// 1100 - 110F␊
1043␉// 1110 - 111F␊
1044␉// 1120 - 112F␊
1045␉// 1130 - 113F␊
1046␉// 1140 - 114F␊
1047␉// { 0x10DE1140,␉"GF117" },␊
1048␉{ 0x10DE1141,␉"GeForce 610M" },␊
1049␉{ 0x10DE1142,␉"GeForce 620M" },␊
1050␉// { 0x10DE1143,␉"N13P-GV" },␊
1051␉// { 0x10DE1144,␉"GF117" },␊
1052␉// { 0x10DE1145,␉"GF117" },␊
1053␉// { 0x10DE1146,␉"GF117" },␊
1054␉// { 0x10DE1147,␉"GF117" },␊
1055␉// { 0x10DE1149,␉"GF117-ES" },␊
1056␉// { 0x10DE114A,␉"GF117-INT" },␊
1057␉// { 0x10DE114B,␉"PCI-GEN3-B" },␊
1058␉// 1150 - 115F␊
1059␉// 1160 - 116F␊
1060␉// 1170 - 117F␊
1061␉// 1180 - 118F␊
1062␉{ 0x10DE1180,␉"GeForce GTX 680" },␊
1063␉{ 0x10DE1188,␉"GeForce GTX 690" },␊
1064␉{ 0x10DE1189,␉"GeForce GTX 670" },␊
1065␉// 1190 - 119F␊
1066␉// 11A0 - 11AF␊
1067␉// 11B0 - 11BF␊
1068␉// 11C0 - 11CF␊
1069␉// 11D0 - 11DF␊
1070␉// 11E0 - 11EF␊
1071␉// 11F0 - 11FF␊
1072␉// 1200 - 120F␊
1073␉{ 0x10DE1200,␉"GeForce GTX 560 Ti" },␊
1074␉{ 0x10DE1201,␉"GeForce GTX 560" },␊
1075␉{ 0x10DE1202,␉"GeForce GTX 560 Ti" },␊
1076␉{ 0x10DE1203,␉"GeForce GTX 460 SE v2" },␊
1077␉{ 0x10DE1205,␉"GeForce GTX 460 v2" },␊
1078␉{ 0x10DE1206,␉"GeForce GTX 555" },␊
1079␉{ 0x10DE1208,␉"GeForce GTX 560 SE" },␊
1080␉{ 0x10DE1210,␉"GeForce GTX 570M" },␊
1081␉{ 0x10DE1211,␉"GeForce GTX 580M" },␊
1082␉{ 0x10DE1212,␉"GeForce GTX 675M" },␊
1083␉{ 0x10DE1213,␉"GeForce GTX 670M" },␊
1084␉{ 0x10DE1240,␉"GeForce GT 620M" },␊
1085␉{ 0x10DE1241,␉"GeForce GT 545" },␊
1086␉{ 0x10DE1243,␉"GeForce GT 545" },␊
1087␉{ 0x10DE1244,␉"GeForce GTX 550 Ti" },␊
1088␉{ 0x10DE1245,␉"GeForce GTS 450" },␊
1089␉{ 0x10DE1246,␉"GeForce GTX 550M" },␊
1090␉{ 0x10DE1247,␉"GeForce GT 635M" }, // Subsystem Id: 1043 212C Asus GeForce GT 635M␊
1091␉{ 0x10DE1248,␉"GeForce GTX 555M" },␊
1092␉{ 0x10DE124B,␉"GeForce GT 640" },␊
1093␉{ 0x10DE124D,␉"GeForce GTX 555M" },␊
1094␉// { 0x10DE1250,␉"GF116-INT" },␊
1095␉{ 0x10DE1251,␉"GeForce GTX 560M" },␊
1096␉// 1260 - 126F␊
1097␉// 1270 - 127F␊
1098␉// 1280 - 128F␊
1099␉// 1290 - 129F␊
1100␉// 12A0 - 12AF␊
1101␉// 12B0 - 12BF␊
1102␉// 12C0 - 12CF␊
1103␉// 12D0 - 12DF␊
1104␉// 12E0 - 12EF␊
1105␉// 12F0 - 12FF␊
1106␊
1107};␊
1108␊
1109␊
1110static int patch_nvidia_rom(uint8_t *rom)␊
1111{␊
1112␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1113␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1114␉␉return PATCH_ROM_FAILED;␊
1115␉}␊
1116␉␊
1117␉uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);␊
1118␊
1119␉if (!dcbptr) {␊
1120␉␉printf("no dcb table found\n");␊
1121␉␉return PATCH_ROM_FAILED;␊
1122␉}␊
1123␉else␊
1124␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1125␊
1126␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1127␉uint8_t dcbtable_version = dcbtable[0];␊
1128␉uint8_t headerlength␉ = 0;␊
1129␉uint8_t numentries␉␉ = 0;␊
1130␉uint8_t recordlength␉ = 0;␊
1131␉␊
1132␉if (dcbtable_version >= 0x20)␊
1133␉{␊
1134␉␉uint32_t sig;␊
1135␉␉␊
1136␉␉if (dcbtable_version >= 0x30)␊
1137␉␉{␊
1138␉␉␉headerlength = dcbtable[1];␊
1139␉␉␉numentries␉ = dcbtable[2];␊
1140␉␉␉recordlength = dcbtable[3];␊
1141␊
1142␉␉␉sig = READ_LE_INT(dcbtable, 6);␊
1143␉␉}␊
1144␉␉else␊
1145␉␉{␊
1146␉␉␉sig = READ_LE_INT(dcbtable, 4);␊
1147␉␉␉headerlength = 8;␊
1148␉␉}␊
1149␉␉␊
1150␉␉if (sig != 0x4edcbdcb)␊
1151␉␉{␊
1152␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1153␉␉␉return PATCH_ROM_FAILED;␊
1154␉␉}␊
1155␉}␊
1156␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1157␉{␊
1158␉␉char sig[8] = { 0 };␊
1159␉␉␊
1160␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1161␉␉recordlength = 10;␊
1162␉␉␊
1163␉␉if (strcmp(sig, "DEV_REC"))␊
1164␉␉{␊
1165␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1166␉␉␉return PATCH_ROM_FAILED;␊
1167␉␉}␊
1168␉}␊
1169␉else␊
1170␉{␊
1171␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1172␉␉return PATCH_ROM_FAILED;␊
1173␉}␊
1174␉␊
1175␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1176␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1177␉␊
1178␉uint8_t num_outputs = 0, i = 0;␊
1179␉␊
1180␉struct dcbentry␊
1181␉{␊
1182␉␉uint8_t type;␊
1183␉␉uint8_t index;␊
1184␉␉uint8_t *heads;␊
1185␉} entries[numentries];␊
1186␉␊
1187␉for (i = 0; i < numentries; i++)␊
1188␉{␊
1189␉␉uint32_t connection;␊
1190␉␉connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);␊
1191␊
1192␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1193␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1194␉␉␉continue;␊
1195␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1196␉␉␉continue;␊
1197␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1198␉␉␉continue;␊
1199␉␉␊
1200␉␉entries[num_outputs].type = connection & 0xf;␊
1201␉␉entries[num_outputs].index = num_outputs;␊
1202␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1203␉}␊
1204␉␊
1205␉int has_lvds = false;␊
1206␉uint8_t channel1 = 0, channel2 = 0;␊
1207␉␊
1208␉for (i = 0; i < num_outputs; i++)␊
1209␉{␊
1210␉␉if (entries[i].type == 3)␊
1211␉␉{␊
1212␉␉␉has_lvds = true;␊
1213␉␉␉//printf("found LVDS\n");␊
1214␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1215␉␉␉entries[i].type = TYPE_GROUPED;␊
1216␉␉}␊
1217␉}␊
1218␉␊
1219␉// if we have a LVDS output, we group the rest to the second channel␊
1220␉if (has_lvds)␊
1221␉{␊
1222␉␉for (i = 0; i < num_outputs; i++)␊
1223␉␉{␊
1224␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1225␉␉␉␉continue;␊
1226␉␉␉␊
1227␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1228␉␉␉entries[i].type = TYPE_GROUPED;␊
1229␉␉}␊
1230␉}␊
1231␉else␊
1232␉{␊
1233␉␉int x;␊
1234␉␉// we loop twice as we need to generate two channels␊
1235␉␉for (x = 0; x <= 1; x++)␊
1236␉␉{␊
1237␉␉␉for (i=0; i<num_outputs; i++)␊
1238␉␉␉{␊
1239␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1240␉␉␉␉␉continue;␊
1241␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1242␉␉␉␉// we always group ANALOG and TMDS␊
1243␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1244␉␉␉␉if (i && entries[i].type == 0x2)␊
1245␉␉␉␉{␊
1246␉␉␉␉␉switch (x)␊
1247␉␉␉␉␉{␊
1248␉␉␉␉␉␉case 0:␊
1249␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1250␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1251␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1252␉␉␉␉␉␉␉␊
1253␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
1254␉␉␉␉␉␉␉{␊
1255␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1256␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1257␉␉␉␉␉␉␉}␊
1258␉␉␉␉␉␉␉// group TV as well if there is one␊
1259␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1260␉␉␉␉␉␉␉{␊
1261␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1262␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1263␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1264␉␉␉␉␉␉␉}␊
1265␉␉␉␉␉␉␉break;␊
1266␉␉␉␉␉␉␊
1267␉␉␉␉␉␉case 1:␊
1268␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1269␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1270␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1271␉␉␉␉␉␉␉␊
1272␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
1273␉␉␉␉␉␉␉{␊
1274␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1275␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1276␉␉␉␉␉␉␉}␊
1277␉␉␉␉␉␉␉// group TV as well if there is one␊
1278␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1279␉␉␉␉␉␉␉{␊
1280␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1281␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1282␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1283␉␉␉␉␉␉␉}␊
1284␉␉␉␉␉␉␉break;␊
1285␉␉␉␉␉}␊
1286␉␉␉␉␉break;␊
1287␉␉␉␉}␊
1288␉␉␉}␊
1289␉␉}␊
1290␉}␊
1291␉␊
1292␉// if we have left ungrouped outputs merge them to the empty channel␊
1293␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1294␉togroup = &channel2;␊
1295␉␊
1296␉for (i = 0; i < num_outputs; i++)␊
1297␉{␊
1298␉␉if (entries[i].type != TYPE_GROUPED)␊
1299␉␉{␊
1300␉␉␉//printf("%d not grouped\n", i);␊
1301␉␉␉if (togroup)␊
1302␉␉␉{␊
1303␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1304␉␉␉}␊
1305␉␉␉entries[i].type = TYPE_GROUPED;␊
1306␉␉}␊
1307␉}␊
1308␉␊
1309␉if (channel1 > channel2)␊
1310␉{␊
1311␉␉uint8_t buff = channel1;␊
1312␉␉channel1 = channel2;␊
1313␉␉channel2 = buff;␊
1314␉}␊
1315␉␊
1316␉default_NVCAP[6] = channel1;␊
1317␉default_NVCAP[8] = channel2;␊
1318␉␊
1319␉// patching HEADS␊
1320␉for (i = 0; i < num_outputs; i++)␊
1321␉{␊
1322␉␉if (channel1 & (1 << i))␊
1323␉␉{␊
1324␉␉␉*entries[i].heads = 1;␊
1325␉␉}␊
1326␉␉else if(channel2 & (1 << i))␊
1327␉␉{␊
1328␉␉␉*entries[i].heads = 2;␊
1329␉␉}␊
1330␉}␊
1331␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1332}␊
1333␊
1334static char *get_nvidia_model(uint32_t id)␊
1335{␊
1336␉int i;␊
1337␉␊
1338␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++)␊
1339␉{␊
1340␉␉if (NVKnownChipsets[i].device == id)␊
1341␉␉{␊
1342␉␉␉return NVKnownChipsets[i].name;␊
1343␉␉}␊
1344␉}␊
1345␉return NVKnownChipsets[0].name;␊
1346}␊
1347␊
1348static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1349{␊
1350␉int fd;␊
1351␉int size;␊
1352␉␊
1353␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1354␉{␊
1355␉␉return 0;␊
1356␉}␊
1357␉␊
1358␉size = file_size(fd);␊
1359␉␊
1360␉if (size > bufsize)␊
1361␉{␊
1362␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1363␉␉␉␉filename, bufsize);␊
1364␉␉size = bufsize;␊
1365␉}␊
1366␉size = read(fd, (char *)buf, size);␊
1367␉close(fd);␊
1368␉␊
1369␉return size > 0 ? size : 0;␊
1370}␊
1371␊
1372static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1373{␊
1374␉char tmp[16];␊
1375␉␊
1376␉if (!device)␊
1377␉␉return 0;␊
1378␉␊
1379␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1380␉␉return 0;␊
1381␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1382␉␉return 0;␊
1383␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1384␉␉return 0;␊
1385␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1386␉␉return 0;␊
1387␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1388␉␉return 0;␊
1389␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1390␉␉return 0;␊
1391␉if (devices_number == 1)␊
1392␉{␊
1393␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1394␉␉ return 0;␊
1395␉}␊
1396␉else␊
1397␉{␊
1398␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1399␉␉ return 0;␊
1400␉}␊
1401␊
1402␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1403␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1404␉sprintf(tmp, "Slot-%x",devices_number);␊
1405␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1406␉devices_number++;␊
1407␉␊
1408␉return 1;␊
1409}␊
1410␊
1411int hex2bin(const char *hex, uint8_t *bin, int len)␊
1412{␊
1413␉char␉*p;␊
1414␉int␉␉i;␊
1415␉char␉buf[3];␊
1416␉␊
1417␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1418␉␉printf("[ERROR] bin2hex input error\n");␊
1419␉␉return -1;␊
1420␉}␊
1421␉␊
1422␉buf[2] = '\0';␊
1423␉p = (char *) hex;␊
1424␉␊
1425␉for (i = 0; i < len; i++)␊
1426␉{␊
1427␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1428␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1429␉␉␉return -2;␊
1430␉␉}␊
1431␉␉buf[0] = *p++;␊
1432␉␉buf[1] = *p++;␊
1433␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1434␉}␊
1435␉return 0;␊
1436}␊
1437␊
1438unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1439{␊
1440␉unsigned long long vram_size = 0;␊
1441␉␊
1442␉if (nvCardType < NV_ARCH_50)␊
1443␉{␊
1444␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1445␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1446␉}␊
1447␉else if (nvCardType < NV_ARCH_C0)␊
1448␉{␊
1449␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1450␉␉vram_size |= (vram_size & 0xff) << 32;␊
1451␉␉vram_size &= 0xffffffff00ll;␊
1452␉}␊
1453␉else // >= NV_ARCH_C0␊
1454␉{␊
1455␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1456␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1457␉}␊
1458␉␊
1459␉// Workaround for 9600M GT, GT 210/420/430/440/525M/540M & GTX 560M␊
1460␉switch (nvda_dev->device_id)␊
1461␉{␊
1462␉␉case 0x0647: vram_size = 512*1024*1024; break;␉// 9600M GT 0647␊
1463␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT 0649␊
1464␉␉case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊
1465␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1466␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1467␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1468␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1469␉␉case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M␊
1470␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1471␉␉case 0x1251: vram_size = 1536*1024*1024; break; // GTX 560M␊
1472␉␉default: break;␊
1473␉}␊
1474␉␊
1475␉return vram_size;␊
1476}␊
1477␊
1478static bool checkNvRomSig(uint8_t * aRom){␊
1479 return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊
1480}␊
1481␊
1482bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1483{␊
1484␉struct DevPropDevice␉*device;␊
1485␉char␉␉␉␉␉*devicepath;␊
1486␉option_rom_pci_header_t *rom_pci_header;␊
1487␉volatile uint8_t␉␉*regs;␊
1488␉uint8_t␉␉␉␉␉*rom;␊
1489␉uint8_t␉␉␉␉␉*nvRom;␊
1490␉uint8_t␉␉␉␉␉nvCardType;␊
1491␉unsigned long long␉␉videoRam;␊
1492␉uint32_t␉␉␉␉nvBiosOveride;␊
1493␉uint32_t␉␉␉␉bar[7];␊
1494␉uint32_t␉␉␉␉boot_display;␊
1495␉int␉␉␉␉␉␉nvPatch;␊
1496␉int␉␉␉␉␉␉len;␊
1497␉char␉␉␉␉␉biosVersion[32];␊
1498␉char␉␉␉␉␉nvFilename[32];␊
1499␉char␉␉␉␉␉kNVCAP[12];␊
1500␉char␉␉␉␉␉*model;␊
1501␉const char␉␉␉␉*value;␊
1502␉bool␉␉␉␉␉doit;␊
1503␉␊
1504␉devicepath = get_pci_dev_path(nvda_dev);␊
1505␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1506␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1507␉␊
1508␉// get card type␊
1509␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1510␉␊
1511␉// Amount of VRAM in kilobytes␊
1512␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1513␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1514␉␊
1515␉verbose("%s %dMB NV%02x [%04x:%04x]-[%04x:%04x] :: %s device number: %d\n",␊
1516␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1517␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1518␉␉␉nvda_dev->subsys_id.subsys.vendor_id, nvda_dev->subsys_id.subsys.device_id,␊
1519␉␉␉devicepath, devices_number);␊
1520␉␊
1521␉rom = malloc(NVIDIA_ROM_SIZE);␊
1522␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1523␉␉␉(uint16_t)nvda_dev->device_id);␊
1524␉␊
1525␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1526␉{␊
1527␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1528␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1529␉␉␊
1530␉␉if (nvBiosOveride > 0)␊
1531␉␉{␊
1532␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1533␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1534␉␉}␊
1535␉␉else␊
1536␉␉{␊
1537␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1538␉␉␉return false;␊
1539␉␉}␊
1540␉}␊
1541␉else␊
1542␉{␊
1543␉␉// Otherwise read bios from card␊
1544␉␉nvBiosOveride = 0;␊
1545␉␉␊
1546 // PROM first␊
1547 // Enable PROM access␊
1548 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1549 nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1550 ␊
1551 // Valid Signature ?␊
1552␉␉if (checkNvRomSig(nvRom))␊
1553␉␉{␊
1554 bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1555 DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1556 }␊
1557 else␊
1558 {␊
1559␊
1560 // disable PROM access␊
1561 (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1562 ␊
1563␉␉ //PRAM next␊
1564 nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1565 ␊
1566 if(checkNvRomSig(nvRom))␊
1567 {␊
1568 bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1569 DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1570 }␊
1571 else␊
1572 ␉␉{␊
1573␉␉␉␉// 0xC0000 last␊
1574␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1575␉␉␉␉␊
1576␉␉␉␉// Valid Signature ?␊
1577␉␉␉␉if (!checkNvRomSig(rom))␊
1578␉␉␉␉{␊
1579␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1580␉␉␉␉␉return false;␊
1581␉␉␉␉}␊
1582 else␊
1583 {␊
1584 DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1585 }␊
1586 ␊
1587␉␉␉}//end PRAM check␊
1588 ␊
1589 }//end PROM check␊
1590 ␊
1591␉}//end load rom from bios␊
1592␉␊
1593␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1594␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1595␉␉//return false;␊
1596␉}␊
1597␉␊
1598␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1599␉␊
1600␉// check for 'PCIR' sig␊
1601␉if (rom_pci_header->signature == 0x50434952)␊
1602␉{␊
1603␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1604␉␉{␊
1605␉␉␉// Get Model from the OpROM␊
1606␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1607␉␉}␊
1608␉␉else␊
1609␉␉{␊
1610␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1611␉␉}␊
1612␉}␊
1613␉␊
1614␉if (!string) {␊
1615␉␉string = devprop_create_string();␊
1616␉}␊
1617␉device = devprop_add_device(string, devicepath);␊
1618␉␊
1619␉/* FIXME: for primary graphics card only */␊
1620␉boot_display = 1;␊
1621␉if (devices_number == 1)␊
1622␉{␊
1623␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1624␉}␊
1625␉␊
1626␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1627␉␉uint8_t built_in = 0x01;␊
1628␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1629␉}␊
1630␊
1631␉// get bios version␊
1632␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1633␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1634␉␊
1635␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1636␉␊
1637␉int i, version_start;␊
1638␉int crlf_count = 0;␊
1639␉␊
1640␉// only search the first 384 bytes␊
1641␉for (i = 0; i < 0x180; i++)␊
1642␉{␊
1643␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1644␉␉{␊
1645␉␉␉crlf_count++;␊
1646␉␉␉// second 0x0D0A was found, extract bios version␊
1647␉␉␉if (crlf_count == 2)␊
1648␉␉␉{␊
1649␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1650␉␉␉␉␊
1651␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1652␉␉␉␉{␊
1653␉␉␉␉␉// find start␊
1654␉␉␉␉␉if (rom[version_start] == 0x00)␊
1655␉␉␉␉␉{␊
1656␉␉␉␉␉␉version_start++;␊
1657␉␉␉␉␉␉␊
1658␉␉␉␉␉␉// strip "Version "␊
1659␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1660␉␉␉␉␉␉{␊
1661␉␉␉␉␉␉␉version_start += 8;␊
1662␉␉␉␉␉␉}␊
1663␉␉␉␉␉␉␊
1664␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1665␉␉␉␉␉␉break;␊
1666␉␉␉␉␉}␊
1667␉␉␉␉}␊
1668␉␉␉␉break;␊
1669␉␉␉}␊
1670␉␉}␊
1671␉}␊
1672␉␊
1673␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1674␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1675␉␊
1676␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1677␉{␊
1678␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1679␉␉␊
1680␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1681␉␉{␊
1682␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1683␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1684␉␉}␊
1685␉}␊
1686␉␊
1687␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1688␉{␊
1689␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1690␉␉␊
1691␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1692␉␉{␊
1693␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1694␉␉␉␊
1695␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1696␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1697␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1698␉␉}␊
1699␉}␊
1700␉␊
1701␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1702␉{␊
1703␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1704␉␉␊
1705␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1706␉␉{␊
1707␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1708␉␉␉␊
1709␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1710␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1711␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1712␉␉}␊
1713␉}␊
1714␉␊
1715#if DEBUG_NVCAP␊
1716␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1717␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1718␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1719␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1720␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1721␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1722#endif␊
1723␉␊
1724␉devprop_add_nvidia_template(device);␊
1725␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1726␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
1727␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1728␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1729␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1730␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1731␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1732␉␊
1733␊
1734␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1735␉{␊
1736␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1737␉}␊
1738␉␊
1739␉//add HDMI Audio back to nvidia␊
1740␉doit = false;␊
1741␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1742␉if(getBoolForKey(kEnableHDMIAudio, &doit, &bootInfo->chameleonConfig) && doit){␊
1743␉␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1744␉␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1745␉}␊
1746␉//end Nvidia HDMI Audio␊
1747␊
1748␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1749␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1750␉stringlength = string->length;␊
1751␉␊
1752␉return true;␊
1753}␊
1754

Archive Download this file

Revision: 1953