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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉␉value->word = 0;␊
37␉␉␉␉␉␉break;␊
38␉␉␉␉␉default:␊
39␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
40␉␉␉␉}␊
41␉␉␉}␊
42␉␉␉␉break;␊
43␊
44␉␉␉default:␊
45␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
46␉␉}␊
47␉}␊
48␉else␊
49␉{␊
50␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
51␉}␊
52␊
53␉return true;␊
54}␊
55␊
56bool getProcessorInformationMaximumClock(returnType *value)␊
57{␊
58␉value->word = Platform.CPU.CPUFrequency/1000000;␊
59␉return true;␊
60}␊
61␊
62bool getSMBOemProcessorBusSpeed(returnType *value)␊
63{␊
64␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
65␉{␉␉␊
66␉␉switch (Platform.CPU.Family) ␊
67␉␉{␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model)␊
71␉␉␉␉{␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
80␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_DALES:␊
82␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
83␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
84␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
86␉␉␉␉␉{␊
87␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
88␉␉␉␉␉␉int nhm_bus = 0x3F;␊
89␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
90␉␉␉␉␉␉unsigned long did, vid;␊
91␉␉␉␉␉␉int i;␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉// Nehalem supports Scrubbing␊
94␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
95␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
96␉␉␉␉␉␉{␊
97␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
98␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
99␉␉␉␉␉␉␉vid &= 0xFFFF;␊
100␉␉␉␉␉␉␉did &= 0xFF00;␊
101␉␉␉␉␉␉␉␊
102␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
103␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
104␉␉␉␉␉␉}␊
105␉␉␉␉␉␉␊
106␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
107␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
108␉␉␉␉␉␉qpimult &= 0x7F;␊
109␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
110␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
111␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
112␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
113␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
114␉␉␉␉␉␉value->word = qpibusspeed;␊
115␉␉␉␉␉␉return true;␊
116␉␉␉␉␉}␊
117␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
118␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
119␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
120␉␉␉␉␉{␊
121␉␉␉␉␉␉int busspeed;␊
122␉␉␉␉␉␉busspeed = 100;␊
123␉␉␉␉␉␉value->word = busspeed;␊
124␉␉␉␉␉␉return true;␊
125␉␉␉␉␉}␊
126␉␉␉␉}␊
127␉␉␉}␊
128␉␉}␊
129␉}␊
130␉return false;␊
131}␊
132␊
133uint16_t simpleGetSMBOemProcessorType(void)␊
134{␊
135␉if (Platform.CPU.NoCores >= 4) ␊
136␉{␊
137␉␉return 0x0501;␉// Quad-Core Xeon␊
138␉}␊
139␉else if (Platform.CPU.NoCores == 1) ␊
140␉{␊
141␉␉return 0x0201;␉// Core Solo␊
142␉};␊
143␉␊
144␉return 0x0301;␉␉// Core 2 Duo␊
145}␊
146␊
147bool getSMBOemProcessorType(returnType *value)␊
148{␊
149␉static bool done = false;␉␉␊
150␊
151␉value->word = simpleGetSMBOemProcessorType();␊
152␊
153␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
154␉{␊
155␉␉if (!done)␊
156␉␉{␊
157␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
158␉␉␉done = true;␊
159␉␉}␊
160␊
161␉␉switch (Platform.CPU.Family) ␊
162␉␉{␊
163␉␉␉case 0x06:␊
164␉␉␉{␊
165␉␉␉␉switch (Platform.CPU.Model)␊
166␉␉␉␉{␊
167␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
168␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
169␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
170␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
171␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
172␉␉␉␉␉␉return true;␊
173␊
174␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
175␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
176␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
177␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
178␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
179␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
180␉␉␉␉␉␉else␊
181␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
182␉␉␉␉␉␉return true;␊
183␊
184␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
185␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
186␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
187␉␉␉␉␉␉else␊
188␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
189␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
190␉␉␉␉␉␉␉else␊
191␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
192␉␉␉␉␉␉return true;␊
193␊
194␉␉␉␉␉case CPU_MODEL_DALES:␊
195␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
196␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
197␉␉␉␉␉␉else␊
198␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
199␉␉␉␉␉␉return true;␊
200␊
201␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7, Xeon E3-12xx LGA1155 (32nm)␊
202␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
203␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
204␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
205␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
206␉␉␉␉␉␉else␊
207␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
208␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉// Core i3␊
209␉␉␉␉␉␉else␊
210␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
211␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
212␉␉␉␉␉␉␉else␊
213␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
214␉␉␉␉␉␉return true;␊
215␉␉␉␉}␊
216␉␉␉}␊
217␉␉}␊
218␉}␊
219␉␊
220␉return false;␊
221}␊
222␊
223bool getSMBMemoryDeviceMemoryType(returnType *value)␊
224{␊
225␉static int idx = -1;␊
226␉int␉map;␊
227␊
228␉idx++;␊
229␉if (idx < MAX_RAM_SLOTS)␊
230␉{␊
231␉␉map = Platform.DMI.DIMM[idx];␊
232␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
233␉␉{␊
234␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
235␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
236␉␉␉return true;␊
237␉␉}␊
238␉}␊
239␉␊
240␉return false;␊
241//␉value->byte = SMB_MEM_TYPE_DDR2;␊
242//␉return true;␊
243}␊
244␊
245bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
246{␊
247 value->word = 0xFFFF;␊
248 return true;␊
249}␊
250␊
251bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
252{␊
253␉static int idx = -1;␊
254␉int␉map;␊
255␊
256␉idx++;␊
257␉if (idx < MAX_RAM_SLOTS)␊
258␉{␊
259␉␉map = Platform.DMI.DIMM[idx];␊
260␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
261␉␉{␊
262␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
263␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
264␉␉␉return true;␊
265␉␉}␊
266␉}␊
267␊
268␉return false;␊
269//␉value->dword = 800;␊
270//␉return true;␊
271}␊
272␊
273bool getSMBMemoryDeviceManufacturer(returnType *value)␊
274{␊
275␉static int idx = -1;␊
276␉int␉map;␊
277␊
278␉idx++;␊
279␉if (idx < MAX_RAM_SLOTS)␊
280␉{␊
281␉␉map = Platform.DMI.DIMM[idx];␊
282␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
283␉␉{␊
284␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
285␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
286␉␉␉return true;␊
287␉␉}␊
288␉}␊
289␊
290␉if (!bootInfo->memDetect)␊
291␉␉return false;␊
292␉value->string = NOT_AVAILABLE;␊
293␉return true;␊
294}␊
295␉␊
296bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
297{␊
298␉static int idx = -1;␊
299␉int␉map;␊
300␊
301␉idx++;␊
302␊
303 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
304␊
305␉if (idx < MAX_RAM_SLOTS)␊
306␉{␊
307␉␉map = Platform.DMI.DIMM[idx];␊
308␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
309␉␉{␊
310␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
311␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
312␉␉␉return true;␊
313␉␉}␊
314␉}␊
315␊
316␉if (!bootInfo->memDetect)␊
317␉␉return false;␊
318␉value->string = NOT_AVAILABLE;␊
319␉return true;␊
320}␊
321␊
322bool getSMBMemoryDevicePartNumber(returnType *value)␊
323{␊
324␉static int idx = -1;␊
325␉int␉map;␊
326␊
327␉idx++;␊
328␉if (idx < MAX_RAM_SLOTS)␊
329␉{␊
330␉␉map = Platform.DMI.DIMM[idx];␊
331␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
332␉␉{␊
333␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
334␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
335␉␉␉return true;␊
336␉␉}␊
337␉}␊
338␊
339␉if (!bootInfo->memDetect)␊
340␉␉return false;␊
341␉value->string = NOT_AVAILABLE;␊
342␉return true;␊
343}␊
344␊
345␊
346// getting smbios addr with fast compare ops, late checksum testing ...␊
347#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
348static const char * const SMTAG = "_SM_";␊
349static const char* const DMITAG = "_DMI_";␊
350␊
351SMBEntryPoint *getAddressOfSmbiosTable(void)␊
352{␊
353␉SMBEntryPoint␉*smbios;␊
354␉/* ␊
355␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
356␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
357␉ */␊
358␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
359␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
360␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
361␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
362␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
363␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
364␉ {␊
365␉␉␉return smbios;␊
366␉ }␊
367␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
368␉}␊
369␉printf("ERROR: Unable to find SMBIOS!\n");␊
370␉pause();␊
371␉return NULL;␊
372}␊
373␊
374

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Revision: 1985