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Root/branches/Chimera/Release/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[]␉␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[]␉␉=␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[]␉␉=␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[]␉␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
82const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
83const char *nvidia_name_0[]␉␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
84const char *nvidia_name_1[]␉␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
85const char *nvidia_slot_name[]␉␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
86␊
87static uint8_t default_NVCAP[]= {␊
88␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
89␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
90␉0x00, 0x00, 0x00, 0x00␊
91};␊
92␊
93#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
94␊
95static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
96static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
97␊
98#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
99#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
100␊
101static struct nv_chipsets_t NVKnownChipsets[] = {␊
102␉{ 0x00000000, "Unknown" },␊
103//========================================␊
104␉// 0040 - 004F␊
105␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
106␉{ 0x10DE0041, "GeForce 6800" },␊
107␉{ 0x10DE0042, "GeForce 6800 LE" },␊
108␉{ 0x10DE0043, "GeForce 6800 XE" },␊
109␉{ 0x10DE0044, "GeForce 6800 XT" },␊
110␉{ 0x10DE0045, "GeForce 6800 GT" },␊
111␉{ 0x10DE0046, "GeForce 6800 GT" },␊
112␉{ 0x10DE0047, "GeForce 6800 GS" },␊
113␉{ 0x10DE0048, "GeForce 6800 XT" },␊
114␉{ 0x10DE004D, "Quadro FX 3400" },␊
115␉{ 0x10DE004E, "Quadro FX 4000" },␊
116␉// 0050 - 005F␊
117␉// 0060 - 006F␊
118␉// 0070 - 007F␊
119␉// 0080 - 008F␊
120␉// 0090 - 009F␊
121␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
122␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
123␉{ 0x10DE0092, "GeForce 7800 GT" },␊
124␉{ 0x10DE0093, "GeForce 7800 GS" },␊
125␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
126␉{ 0x10DE0098, "GeForce Go 7800" },␊
127␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
128␉{ 0x10DE009D, "Quadro FX 4500" },␊
129␉// 00A0 - 00AF␊
130␉// 00B0 - 00BF␊
131␉// 00C0 - 00CF␊
132␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
133␉{ 0x10DE00C1, "GeForce 6800" },␊
134␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
135␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
136␉{ 0x10DE00C8, "GeForce Go 6800" },␊
137␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
138␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
139␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
140␉{ 0x10DE00CE, "Quadro FX 1400" },␊
141␉// 00D0 - 00DF␊
142␉// 00E0 - 00EF␊
143␉// 00F0 - 00FF␊
144␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
145␉{ 0x10DE00F2, "GeForce 6600" },␊
146␉{ 0x10DE00F3, "GeForce 6200" },␊
147␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
148␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
149␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
150␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
151␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
152␉// 0100 - 010F␊
153␉// 0110 - 011F␊
154␉// 0120 - 012F␊
155␉// 0130 - 013F␊
156␉// 0140 - 014F␊
157␉{ 0x10DE0140, "GeForce 6600 GT" },␊
158␉{ 0x10DE0141, "GeForce 6600" },␊
159␉{ 0x10DE0142, "GeForce 6600 LE" },␊
160␉{ 0x10DE0143, "GeForce 6600 VE" },␊
161␉{ 0x10DE0144, "GeForce Go 6600" },␊
162␉{ 0x10DE0145, "GeForce 6610 XL" },␊
163␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
164␉{ 0x10DE0147, "GeForce 6700 XL" },␊
165␉{ 0x10DE0148, "GeForce Go 6600" },␊
166␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
167␉{ 0x10DE014A, "Quadro NVS 440" },␊
168␉{ 0x10DE014C, "Quadro FX 550" },␊
169␉{ 0x10DE014D, "Quadro FX 550" },␊
170␉{ 0x10DE014E, "Quadro FX 540" },␊
171␉{ 0x10DE014F, "GeForce 6200" },␊
172␉// 0150 - 015F␊
173␉// 0160 - 016F␊
174␉{ 0x10DE0160, "GeForce 6500" },␊
175␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
176␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
177␉{ 0x10DE0163, "GeForce 6200 LE" },␊
178␉{ 0x10DE0164, "GeForce Go 6200" },␊
179␉{ 0x10DE0165, "Quadro NVS 285" },␊
180␉{ 0x10DE0166, "GeForce Go 6400" },␊
181␉{ 0x10DE0167, "GeForce Go 6200" },␊
182␉{ 0x10DE0168, "GeForce Go 6400" },␊
183␉{ 0x10DE0169, "GeForce 6250" },␊
184␉{ 0x10DE016A, "GeForce 7100 GS" },␊
185␉// 0170 - 017F␊
186␉// 0180 - 018F␊
187␉// 0190 - 019F␊
188␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
189␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
190␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
191␉{ 0x10DE0197, "Tesla C870" },␊
192␉{ 0x10DE019D, "Quadro FX 5600" },␊
193␉{ 0x10DE019E, "Quadro FX 4600" },␊
194␉// 01A0 - 01AF␊
195␉// 01B0 - 01BF␊
196␉// 01C0 - 01CF␊
197␉// 01D0 - 01DF␊
198␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
199␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
200␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
201␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
202␉{ 0x10DE01D6, "GeForce Go 7200" },␊
203␉{ 0x10DE01D7, "GeForce Go 7300" },␊
204␉{ 0x10DE01D8, "GeForce Go 7400" },␊
205␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
206␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
207␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
208␉{ 0x10DE01DC, "Quadro FX 350M" },␊
209␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
210␉{ 0x10DE01DE, "Quadro FX 350" },␊
211␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
212␉// 01E0 - 01EF␊
213␉// 01F0 - 01FF␊
214␉// 0200 - 020F␊
215␉// 0210 - 021F␊
216␉{ 0x10DE0211, "GeForce 6800" },␊
217␉{ 0x10DE0212, "GeForce 6800 LE" },␊
218␉{ 0x10DE0215, "GeForce 6800 GT" },␊
219␉{ 0x10DE0218, "GeForce 6800 XT" },␊
220␉// 0220 - 022F␊
221␉{ 0x10DE0221, "GeForce 6200" },␊
222␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
223␉// 0230 - 023F␊
224␉// 0240 - 024F␊
225␉{ 0x10DE0240, "GeForce 6150" },␊
226␉{ 0x10DE0241, "GeForce 6150 LE" },␊
227␉{ 0x10DE0242, "GeForce 6100" },␊
228␉{ 0x10DE0244, "GeForce Go 6150" },␊
229␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
230␉{ 0x10DE0247, "GeForce Go 6100" },␊
231␉// 0250 - 025F␊
232␉// 0260 - 026F␊
233␉// 0270 - 027F␊
234␉// 0280 - 028F␊
235␉// 0290 - 029F␊
236␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
237␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
238␉{ 0x10DE0292, "GeForce 7900 GS" },␊
239␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
240␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
241␉{ 0x10DE0295, "GeForce 7950 GT" },␊
242␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
243␉{ 0x10DE0299, "Quadro NVS 510M" },␊
244␉{ 0x10DE029A, "Quadro FX 2500M" },␊
245␉{ 0x10DE029B, "Quadro FX 1500M" },␊
246␉{ 0x10DE029C, "Quadro FX 5500" },␊
247␉{ 0x10DE029D, "Quadro FX 3500" },␊
248␉{ 0x10DE029E, "Quadro FX 1500" },␊
249␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
250␉// 02A0 - 02AF␊
251␉// 02B0 - 02BF␊
252␉// 02C0 - 02CF␊
253␉// 02D0 - 02DF␊
254␉// 02E0 - 02EF␊
255␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
256␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
257␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
258␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
259␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
260␉// 02F0 - 02FF␊
261␉// 0300 - 030F␊
262␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
263␉{ 0x10DE0302, "GeForce FX 5800" },␊
264␉{ 0x10DE0308, "Quadro FX 2000" },␊
265␉{ 0x10DE0309, "Quadro FX 1000" },␊
266␉// 0310 - 031F␊
267␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
268␉{ 0x10DE0312, "GeForce FX 5600" },␊
269␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
270␉{ 0x10DE031A, "GeForce FX Go5600" },␊
271␉{ 0x10DE031B, "GeForce FX Go5650" },␊
272␉{ 0x10DE031C, "Quadro FX Go700" },␊
273␉// 0320 - 032F␊
274 { 0x10DE0320, "GeForce FX 5200" },␊
275␉{ 0x10DE0321, "GeForce FX 5200 Ultra" },␊
276␉{ 0x10DE0322, "GeForce FX 5200" },␊
277␉{ 0x10DE0323, "GeForce FX 5200 LE" },␊
278␉{ 0x10DE0324, "GeForce FX Go5200" },␊
279␉{ 0x10DE0325, "GeForce FX Go5250" },␊
280␉{ 0x10DE0326, "GeForce FX 5500" },␊
281␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
282 { 0x10DE0329, "GeForce FX Go5200" },␊
283␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
284␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
285␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
286␉{ 0x10DE032D, "GeForce FX Go5100" },␊
287␉// 0330 - 033F␊
288␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
289␉{ 0x10DE0331, "GeForce FX 5900" },␊
290␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
291␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
292␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
293␉{ 0x10DE0338, "Quadro FX 3000" },␊
294␉{ 0x10DE033F, "Quadro FX 700" },␊
295␉// 0340 - 034F␊
296␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
297␉{ 0x10DE0342, "GeForce FX 5700" },␊
298␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
299␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
300␉{ 0x10DE0347, "GeForce FX Go5700" },␊
301␉{ 0x10DE0348, "GeForce FX Go5700" },␊
302␉{ 0x10DE034C, "Quadro FX Go1000" },␊
303␉{ 0x10DE034E, "Quadro FX 1100" },␊
304␉// 0350 - 035F␊
305␉// 0360 - 036F␊
306␉// 0370 - 037F␊
307␉// 0380 - 038F␊
308␉{ 0x10DE038B, "GeForce 7650 GS" },␊
309␉// 0390 - 039F␊
310␉{ 0x10DE0390, "GeForce 7650 GS" },␊
311␉{ 0x10DE0391, "GeForce 7600 GT" },␊
312␉{ 0x10DE0392, "GeForce 7600 GS" },␊
313␉{ 0x10DE0393, "GeForce 7300 GT" },␊
314␉{ 0x10DE0394, "GeForce 7600 LE" },␊
315␉{ 0x10DE0395, "GeForce 7300 GT" },␊
316␉{ 0x10DE0397, "GeForce Go 7700" },␊
317␉{ 0x10DE0398, "GeForce Go 7600" },␊
318␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
319␉{ 0x10DE039A, "Quadro NVS 300M" },␊
320␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
321␉{ 0x10DE039C, "Quadro FX 550M" },␊
322␉{ 0x10DE039E, "Quadro FX 560" },␊
323␉// 03A0 - 03AF␊
324␉// 03B0 - 03BF␊
325␉// 03C0 - 03CF␊
326␉// 03D0 - 03DF␊
327␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
328␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
329␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
330␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
331␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
332␉// 03E0 - 03EF␊
333␉// 03F0 - 03FF␊
334␉// 0400 - 040F␊
335␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
336␉{ 0x10DE0401, "GeForce 8600 GT" },␊
337␉{ 0x10DE0402, "GeForce 8600 GT" },␊
338␉{ 0x10DE0403, "GeForce 8600 GS" },␊
339␉{ 0x10DE0404, "GeForce 8400 GS" },␊
340␉{ 0x10DE0405, "GeForce 9500M GS" },␊
341␉{ 0x10DE0406, "GeForce 8300 GS" },␊
342␉{ 0x10DE0407, "GeForce 8600M GT" },␊
343␉{ 0x10DE0408, "GeForce 9650M GS" },␊
344␉{ 0x10DE0409, "GeForce 8700M GT" },␊
345␉{ 0x10DE040A, "Quadro FX 370" },␊
346␉{ 0x10DE040B, "Quadro NVS 320M" },␊
347␉{ 0x10DE040C, "Quadro FX 570M" },␊
348␉{ 0x10DE040D, "Quadro FX 1600M" },␊
349␉{ 0x10DE040E, "Quadro FX 570" },␊
350␉{ 0x10DE040F, "Quadro FX 1700" },␊
351␉// 0410 - 041F␊
352␉{ 0x10DE0410, "GeForce GT 330" },␊
353␉// 0420 - 042F␊
354␉{ 0x10DE0420, "GeForce 8400 SE" },␊
355␉{ 0x10DE0421, "GeForce 8500 GT" },␊
356␉{ 0x10DE0422, "GeForce 8400 GS" },␊
357␉{ 0x10DE0423, "GeForce 8300 GS" },␊
358␉{ 0x10DE0424, "GeForce 8400 GS" },␊
359␉{ 0x10DE0425, "GeForce 8600M GS" },␊
360␉{ 0x10DE0426, "GeForce 8400M GT" },␊
361␉{ 0x10DE0427, "GeForce 8400M GS" },␊
362␉{ 0x10DE0428, "GeForce 8400M G" },␊
363␉{ 0x10DE0429, "Quadro NVS 140M" },␊
364␉{ 0x10DE042A, "Quadro NVS 130M" },␊
365␉{ 0x10DE042B, "Quadro NVS 135M" },␊
366␉{ 0x10DE042C, "GeForce 9400 GT" },␊
367␉{ 0x10DE042D, "Quadro FX 360M" },␊
368␉{ 0x10DE042E, "GeForce 9300M G" },␊
369␉{ 0x10DE042F, "Quadro NVS 290" },␊
370␉// 0430 - 043F␊
371␉// 0440 - 044F␊
372␉// 0450 - 045F␊
373␉// 0460 - 046F␊
374␉// 0470 - 047F␊
375␉// 0480 - 048F␊
376␉// 0490 - 049F␊
377␉// 04A0 - 04AF␊
378␉// 04B0 - 04BF␊
379␉// 04C0 - 04CF␊
380␉// 04D0 - 04DF␊
381␉// 04E0 - 04EF␊
382␉// 04F0 - 04FF␊
383␉// 0500 - 050F␊
384␉// 0510 - 051F␊
385␉// 0520 - 052F␊
386␉// 0530 - 053F␊
387 { 0x10DE0530, "GeForce 7190M / nForce 650M" },␊
388␉{ 0x10DE0531, "GeForce 7150M / nForce 630M" },␊
389␉{ 0x10DE0533, "GeForce 7000M / nForce 610M" },␊
390␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
391␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
392␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
393␉// 0540 - 054F␊
394␉// 0550 - 055F␊
395␉// 0560 - 056F␊
396␉// 0570 - 057F␊
397␉// 0580 - 058F␊
398␉// 0590 - 059F␊
399␉// 05A0 - 05AF␊
400␉// 05B0 - 05BF␊
401␉// 05C0 - 05CF␊
402␉// 05D0 - 05DF␊
403␉// 05E0 - 05EF␊
404␉{ 0x10DE05E0, "GeForce GTX 295" },␊
405␉{ 0x10DE05E1, "GeForce GTX 280" },␊
406␉{ 0x10DE05E2, "GeForce GTX 260" },␊
407␉{ 0x10DE05E3, "GeForce GTX 285" },␊
408␉{ 0x10DE05E6, "GeForce GTX 275" },␊
409␉{ 0x10DE05E7, "Tesla C1060 / M1060" },␊
410␉// { 0x10DE05E7, 0x0595, "Tesla C1060" },␊
411␉// { 0x10DE05E7, 0x068F, "Tesla C1060" },␊
412␉// { 0x10DE05E7, 0x0697, "Tesla M1060" },␊
413␉// { 0x10DE05E7, 0x0743, "Tesla M1060" },␊
414␉{ 0x10DE05EA, "GeForce GTX 260" },␊
415␉{ 0x10DE05EB, "GeForce GTX 295" },␊
416␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
417␉// 05F0 - 05FF␊
418␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
419␉{ 0x10DE05F9, "Quadro CX" },␊
420␉{ 0x10DE05FD, "Quadro FX 5800" },␊
421␉{ 0x10DE05FE, "Quadro FX 4800" },␊
422␉{ 0x10DE05FF, "Quadro FX 3800" },␊
423␉// 0600 - 060F␊
424␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
425␉{ 0x10DE0601, "GeForce 9800 GT" },␊
426␉{ 0x10DE0602, "GeForce 8800 GT" },␊
427␉{ 0x10DE0603, "GeForce GT 230" },␊
428␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
429␉{ 0x10DE0605, "GeForce 9800 GT" },␊
430␉{ 0x10DE0606, "GeForce 8800 GS" },␊
431␉{ 0x10DE0607, "GeForce GTS 240" },␊
432␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
433␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
434␉{ 0x10DE060A, "GeForce GTX 280M" },␊
435␉{ 0x10DE060B, "GeForce 9800M GT" },␊
436␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
437␉{ 0x10DE060D, "GeForce 8800 GS" },␊
438␉{ 0x10DE060F, "GeForce GTX 285M" },␊
439␉// 0610 - 061F␊
440␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
441␉{ 0x10DE0611, "GeForce 8800 GT" },␊
442␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
443␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
444␉{ 0x10DE0614, "GeForce 9800 GT" },␊
445␉{ 0x10DE0615, "GeForce GTS 250" },␊
446␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
447␉{ 0x10DE0618, "GeForce GTX 260M" },␊
448␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
449␉{ 0x10DE061A, "Quadro FX 3700" },␊
450␉{ 0x10DE061B, "Quadro VX 200" },␊
451␉{ 0x10DE061C, "Quadro FX 3600M" },␊
452␉{ 0x10DE061D, "Quadro FX 2800M" },␊
453␉{ 0x10DE061E, "Quadro FX 3700M" },␊
454␉{ 0x10DE061F, "Quadro FX 3800M" },␊
455␉// 0620 - 062F␊
456␉{ 0x10DE0621, "GeForce GT 230" },␊
457␉{ 0x10DE0622, "GeForce 9600 GT" },␊
458␉{ 0x10DE0623, "GeForce 9600 GS" },␊
459␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
460␉{ 0x10DE0626, "GeForce GT 130" },␊
461␉{ 0x10DE0627, "GeForce GT 140" },␊
462␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
463␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
464␉{ 0x10DE062B, "GeForce 9800M GS" },␊
465␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
466␉{ 0x10DE062D, "GeForce 9600 GT" },␊
467␉{ 0x10DE062E, "GeForce 9600 GT" },␊
468␉// 0630 - 063F␊
469␉{ 0x10DE0631, "GeForce GTS 160M" },␊
470␉{ 0x10DE0632, "GeForce GTS 150M" },␊
471␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
472␉{ 0x10DE0637, "GeForce 9600 GT" },␊
473␉{ 0x10DE0638, "Quadro FX 1800" },␊
474␉{ 0x10DE063A, "Quadro FX 2700M" },␊
475␉// 0640 - 064F␊
476␉{ 0x10DE0640, "GeForce 9500 GT" },␊
477␉{ 0x10DE0641, "GeForce 9400 GT" },␊
478␉{ 0x10DE0642, "GeForce 8400 GS" },␊
479␉{ 0x10DE0643, "GeForce 9500 GT" },␊
480␉{ 0x10DE0644, "GeForce 9500 GS" },␊
481␉{ 0x10DE0645, "GeForce 9500 GS" },␊
482␉{ 0x10DE0646, "GeForce GT 120" },␊
483␉{ 0x10DE0647, "GeForce 9600M GT" },␊
484␉{ 0x10DE0648, "GeForce 9600M GS" },␊
485␉{ 0x10DE0649, "GeForce 9600M GT" },␊
486␉{ 0x10DE064A, "GeForce 9700M GT" },␊
487␉{ 0x10DE064B, "GeForce 9500M G" },␊
488␉{ 0x10DE064C, "GeForce 9650M GT" },␊
489␉// 0650 - 065F␊
490␉{ 0x10DE0651, "GeForce G 110M" },␊
491␉{ 0x10DE0652, "GeForce GT 130M" },␊
492␉{ 0x10DE0653, "GeForce GT 120M" },␊
493␉{ 0x10DE0654, "GeForce GT 220M" },␊
494␉{ 0x10DE0655, "GeForce GT 120" },␊
495␉{ 0x10DE0656, "GeForce 9650 S" },␊
496␉{ 0x10DE0658, "Quadro FX 380" },␊
497␉{ 0x10DE0659, "Quadro FX 580" },␊
498␉{ 0x10DE065A, "Quadro FX 1700M" },␊
499␉{ 0x10DE065B, "GeForce 9400 GT" },␊
500␉{ 0x10DE065C, "Quadro FX 770M" },␊
501␉{ 0x10DE065F, "GeForce G210" },␊
502␉// 0660 - 066F␊
503␉// 0670 - 067F␊
504␉// 0680 - 068F␊
505␉// 0690 - 069F␊
506␉// 06A0 - 06AF␊
507␉// 06B0 - 06BF␊
508␉// 06C0 - 06CF␊
509␉{ 0x10DE06C0, "GeForce GTX 480" },␊
510␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
511␉{ 0x10DE06C4, "GeForce GTX 465" },␊
512␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
513␉{ 0x10DE06CD, "GeForce GTX 470" },␊
514␉// 06D0 - 06DF␊
515␉{ 0x10DE06D1, "Tesla C2050 / C2070" },␊
516␉// { 0x10DE06D1, 0x0771, "Tesla C2050" },␊
517␉// { 0x10DE06D1, 0x0772, "Tesla C2070" },␊
518␉{ 0x10DE06D2, "Tesla M2070 / M2070" },␊
519␉// { 0x10DE06D2, 0x082F, "Tesla M2050" },␊
520␉// { 0x10DE06D2, 0x082F, "Tesla M2070" },␊
521␉{ 0x10DE06D8, "Quadro 6000" },␊
522␉{ 0x10DE06D9, "Quadro 5000" },␊
523␉{ 0x10DE06DA, "Quadro 5000M" },␊
524␉{ 0x10DE06DC, "Quadro 6000" },␊
525␉{ 0x10DE06DD, "Quadro 4000" },␊
526␉{ 0x10DE06DE, "Tesla M2050" },␊
527␉// { 0x10DE06DE, 0x082F, "Tesla M2050" },␊
528␉// { 0x10DE06DE, 0x0846, "Tesla M2050" },␊
529␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
530␉// 06E0 - 06EF␊
531␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
532␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
533␉{ 0x10DE06E2, "GeForce 8400" },␊
534␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
535␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
536␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
537␉{ 0x10DE06E6, "GeForce G100" },␊
538␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
539␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
540␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
541␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
542␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
543␉{ 0x10DE06EC, "GeForce G 105M" },␊
544␉{ 0x10DE06EF, "GeForce G 103M" },␊
545␉// 06F0 - 06FF␊
546␉{ 0x10DE06F1, "GeForce G105M" },␊
547␉{ 0x10DE06F8, "Quadro NVS 420" },␊
548␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
549␉{ 0x10DE06FA, "Quadro NVS 450" },␊
550␉{ 0x10DE06FB, "Quadro FX 370M" },␊
551␉{ 0x10DE06FD, "Quadro NVS 295" },␊
552␉{ 0x10DE06FF, "HICx16 + Graphics" },␊
553␉// 0700 - 070F␊
554␉// 0710 - 071F␊
555␉// 0720 - 072F␊
556␉// 0730 - 073F␊
557␉// 0740 - 074F␊
558␉// 0750 - 075F␊
559␉// 0760 - 076F␊
560␉// 0770 - 077F␊
561␉// 0780 - 078F␊
562␉// 0790 - 079F␊
563␉// 07A0 - 07AF␊
564␉// 07B0 - 07BF␊
565␉// 07C0 - 07CF␊
566␉// 07D0 - 07DF␊
567␉// 07E0 - 07EF␊
568␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
569␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
570␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
571␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
572␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
573␉// 07F0 - 07FF␊
574␉// 0800 - 080F␊
575␉// 0810 - 081F␊
576␉// 0820 - 082F␊
577␉// 0830 - 083F␊
578␉// 0840 - 084F␊
579␉{ 0x10DE0840, "GeForce 8200M" },␊
580␉{ 0x10DE0844, "GeForce 9100M G" },␊
581␉{ 0x10DE0845, "GeForce 8200M G" },␊
582␉{ 0x10DE0846, "GeForce 9200" },␊
583␉{ 0x10DE0847, "GeForce 9100" },␊
584␉{ 0x10DE0848, "GeForce 8300" },␊
585␉{ 0x10DE0849, "GeForce 8200" },␊
586␉{ 0x10DE084A, "nForce 730a" },␊
587␉{ 0x10DE084B, "GeForce 9200" },␊
588␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
589␉{ 0x10DE084D, "nForce 750a SLI" },␊
590␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
591␉// 0850 - 085F␊
592␉// 0860 - 086F␊
593␉{ 0x10DE0860, "GeForce 9400" },␊
594␉{ 0x10DE0861, "GeForce 9400" },␊
595␉{ 0x10DE0862, "GeForce 9400M G" },␊
596␉{ 0x10DE0863, "GeForce 9400M" },␊
597␉{ 0x10DE0864, "GeForce 9300" },␊
598␉{ 0x10DE0865, "ION" },␊
599␉{ 0x10DE0866, "GeForce 9400M G" },␊
600␉{ 0x10DE0867, "GeForce 9400" },␊
601␉{ 0x10DE0868, "nForce 760i SLI" },␊
602␉{ 0x10DE0869, "GeForce 9400" },␊
603␉{ 0x10DE086A, "GeForce 9400" },␊
604␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
605␉{ 0x10DE086D, "GeForce 9200" },␊
606␉{ 0x10DE086E, "GeForce 9100M G" },␊
607␉{ 0x10DE086F, "GeForce 8200M G" },␊
608␉// 0870 - 087F␊
609␉{ 0x10DE0870, "GeForce 9400M" },␊
610␉{ 0x10DE0871, "GeForce 9200" },␊
611␉{ 0x10DE0872, "GeForce G102M" },␊
612␉{ 0x10DE0873, "GeForce G102M" },␊
613␉{ 0x10DE0874, "ION" },␊
614␉{ 0x10DE0876, "ION" },␊
615␉{ 0x10DE087A, "GeForce 9400" },␊
616␉{ 0x10DE087D, "ION" },␊
617␉{ 0x10DE087E, "ION LE" },␊
618␉{ 0x10DE087F, "ION LE" },␊
619␉// 0880 - 088F␊
620␉// 0890 - 089F␊
621␉// 08A0 - 08AF␊
622␉{ 0x10DE08A0, "GeForce 320M" },␊
623␉{ 0x10DE08A4, "GeForce 320M" },␊
624␉{ 0x10DE08A5, "GeForce 320M" },␊
625␉// 08B0 - 08BF␊
626␉// 08C0 - 08CF␊
627␉// 08D0 - 08DF␊
628␉// 08E0 - 08EF␊
629␉// 08F0 - 08FF␊
630␉// 0900 - 090F␊
631␉// 0910 - 091F␊
632␉// 0920 - 092F␊
633␉// 0930 - 093F␊
634␉// 0940 - 094F␊
635␉// 0950 - 095F␊
636␉// 0960 - 096F␊
637␉// 0970 - 097F␊
638␉// 0980 - 098F␊
639␉// 0990 - 099F␊
640␉// 09A0 - 09AF␊
641␉// 09B0 - 09BF␊
642␉// 09C0 - 09CF␊
643␉// 09D0 - 09DF␊
644␉// 09E0 - 09EF␊
645␉// 09F0 - 09FF␊
646␉// 0A00 - 0A0F␊
647␉// 0A10 - 0A1F␊
648␉// 0A20 - 0A2F␊
649␉{ 0x10DE0A20, "GeForce GT220" },␊
650␉{ 0x10DE0A22, "GeForce 315" },␊
651␉{ 0x10DE0A23, "GeForce 210" },␊
652␉{ 0x10DE0A26, "GeForce 405" },␊
653␉{ 0x10DE0A27, "GeForce 405" },␊
654␉{ 0x10DE0A28, "GeForce GT 230M" },␊
655␉{ 0x10DE0A29, "GeForce GT 330M" },␊
656␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
657␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
658␉{ 0x10DE0A2C, "NVS 5100M" },␊
659␉{ 0x10DE0A2D, "GeForce GT 320M" },␊
660␉// 0A30 - 0A3F␊
661 { 0x10DE0A32, "GeForce GT 415" },␊
662␉{ 0x10DE0A34, "GeForce GT 240M" },␊
663␉{ 0x10DE0A35, "GeForce GT 325M" },␊
664␉{ 0x10DE0A38, "Quadro 400" },␊
665␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
666␉// 0A40 - 0A4F␊
667␉// 0A50 - 0A5F␊
668␉// 0A60 - 0A6F␊
669␉{ 0x10DE0A60, "GeForce G210" },␊
670␉{ 0x10DE0A62, "GeForce 205" },␊
671␉{ 0x10DE0A63, "GeForce 310" },␊
672␉{ 0x10DE0A64, "ION" },␊
673␉{ 0x10DE0A65, "GeForce 210" },␊
674␉{ 0x10DE0A66, "GeForce 310" },␊
675␉{ 0x10DE0A67, "GeForce 315" },␊
676␉{ 0x10DE0A68, "GeForce G105M" },␊
677␉{ 0x10DE0A69, "GeForce G105M" },␊
678␉{ 0x10DE0A6A, "NVS 2100M" },␊
679␉{ 0x10DE0A6C, "NVS 3100M" },␊
680␉{ 0x10DE0A6E, "GeForce 305M" },␊
681␉{ 0x10DE0A6F, "ION" },␊
682␉// 0A70 - 0A7F␊
683␉{ 0x10DE0A70, "GeForce 310M" },␊
684␉{ 0x10DE0A71, "GeForce 305M" },␊
685␉{ 0x10DE0A72, "GeForce 310M" },␊
686␉{ 0x10DE0A73, "GeForce 305M" },␊
687␉{ 0x10DE0A74, "GeForce G210M" },␊
688␉{ 0x10DE0A75, "GeForce 310M" },␊
689␉{ 0x10DE0A76, "ION" },␊
690␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
691␉{ 0x10DE0A7A, "GeForce 315M" },␊
692␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
693␉// 0A80 - 0A8F␊
694␉// 0A90 - 0A9F␊
695␉// 0AA0 - 0AAF␊
696␉// 0AB0 - 0ABF␊
697␉// 0AC0 - 0ACF␊
698␉// 0AD0 - 0ADF␊
699␉// 0AE0 - 0AEF␊
700␉// 0AF0 - 0AFF␊
701␉// 0B00 - 0B0F␊
702␉// 0B10 - 0B1F␊
703␉// 0B20 - 0B2F␊
704␉// 0B30 - 0B3F␊
705␉// 0B40 - 0B4F␊
706␉// 0B50 - 0B5F␊
707␉// 0B60 - 0B6F␊
708␉// 0B70 - 0B7F␊
709␉// 0B80 - 0B8F␊
710␉// 0B90 - 0B9F␊
711␉// 0BA0 - 0BAF␊
712␉// 0BB0 - 0BBF␊
713␉// 0BC0 - 0BCF␊
714␉// 0BD0 - 0BDF␊
715␉// 0BE0 - 0BEF␊
716␉// 0BF0 - 0BFF␊
717␉// 0C00 - 0C0F␊
718␉// 0C10 - 0C1F␊
719␉// 0C20 - 0C2F␊
720␉// 0C30 - 0C3F␊
721␉// 0C40 - 0C4F␊
722␉// 0C50 - 0C5F␊
723␉// 0C60 - 0C6F␊
724␉// 0C70 - 0C7F␊
725␉// 0C80 - 0C8F␊
726␉// 0C90 - 0C9F␊
727␉// 0CA0 - 0CAF␊
728␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
729␉{ 0x10DE0CA2, "GeForce GT 320" },␊
730␉{ 0x10DE0CA3, "GeForce GT 240" },␊
731␉{ 0x10DE0CA4, "GeForce GT 340" },␊
732␉{ 0x10DE0CA5, "GeForce GT 220" },␊
733␉{ 0x10DE0CA7, "GeForce GT 330" },␊
734␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
735␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
736␉{ 0x10DE0CAC, "GeForce GT 220" },␊
737␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
738␉// 0CB0 - 0CBF␊
739␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
740␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
741␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
742␉// 0CC0 - 0CCF␊
743␉// 0CD0 - 0CDF␊
744␉// 0CE0 - 0CEF␊
745␉// 0CF0 - 0CFF␊
746␉// 0D00 - 0D0F␊
747␉// 0D10 - 0D1F␊
748␉// 0D20 - 0D2F␊
749␉// 0D30 - 0D3F␊
750␉// 0D40 - 0D4F␊
751␉// 0D50 - 0D5F␊
752␉// 0D60 - 0D6F␊
753␉// 0D70 - 0D7F␊
754␉// 0D80 - 0D8F␊
755␉// 0D90 - 0D9F␊
756␉// 0DA0 - 0DAF␊
757␉// 0DB0 - 0DBF␊
758␉// 0DC0 - 0DCF␊
759␉{ 0x10DE0DC0, "GeForce GT 440" },␊
760␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
761␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
762␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
763␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
764␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
765␉// 0DD0 - 0DDF␊
766␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
767␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
768␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
769␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
770␉{ 0x10DE0DD8, "Quadro 2000 / Quadro 2000D" },␊
771␉{ 0x10DE0DDA, "Quadro 2000M" },␊
772␉// 0DE0 - 0DEF␊
773␉{ 0x10DE0DE0, "GeForce GT 440" },␊
774␉{ 0x10DE0DE1, "GeForce GT 430" },␊
775␉{ 0x10DE0DE2, "GeForce GT 420" },␊
776␉{ 0x10DE0DE4, "GeForce GT 520" },␊
777␉{ 0x10DE0DE5, "GeForce GT 530" },␊
778 { 0x10DE0DE8, "GeForce GT 620M" },␊
779␉{ 0x10DE0DE9, "GeForce GT 630M" },␊
780 { 0x10DE0DEA, "GeForce 610M" },␊
781␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
782␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
783␉{ 0x10DE0DED, "GeForce GT 520M" },␊
784␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
785 { 0x10DE0DEF, "NVS 5400M" },␊
786␉// 0DF0 - 0DFF␊
787␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
788␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
789␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
790␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
791␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
792␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
793␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
794␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
795␉{ 0x10DE0DF8, "Quadro 600" },␊
796 { 0x10DE0DF9, "Quadro 500M" },␊
797␉{ 0x10DE0DFA, "Quadro 1000M" },␊
798␉{ 0x10DE0DFC, "NVS 5200M" },␊
799␉// 0E00 - 0E0F␊
800␉// 0E10 - 0E1F␊
801␉// 0E20 - 0E2F␊
802␉{ 0x10DE0E22, "GeForce GTX 460" },␊
803␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
804␉{ 0x10DE0E24, "GeForce GTX 460" },␊
805␉// 0E30 - 0E3F␊
806␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
807␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
808␉{ 0x10DE0E3A, "Quadro 3000M" },␊
809␉{ 0x10DE0E3B, "Quadro 4000M" },␊
810␉// 0E40 - 0E4F␊
811␉// 0E50 - 0E5F␊
812␉// 0E60 - 0E6F␊
813␉// 0E70 - 0E7F␊
814␉// 0E80 - 0E8F␊
815␉// 0E90 - 0E9F␊
816␉// 0EA0 - 0EAF␊
817␉// 0EB0 - 0EBF␊
818␉// 0EC0 - 0ECF␊
819␉// 0ED0 - 0EDF␊
820␉// 0EE0 - 0EEF␊
821␉// 0EF0 - 0EFF␊
822␉// 0F00 - 0F0F␊
823 { 0x10DE0F00, "GeForce GT 630" },␊
824 { 0x10DE0F01, "GeForce GT 620" },␊
825␉// 0F10 - 0F1F␊
826␉// 0F20 - 0F2F␊
827␉// 0F30 - 0F3F␊
828␉// 0F40 - 0F4F␊
829␉// 0F50 - 0F5F␊
830␉// 0F60 - 0F6F␊
831␉// 0F70 - 0F7F␊
832␉// 0F80 - 0F8F␊
833␉// 0F90 - 0F9F␊
834␉// 0FA0 - 0FAF␊
835␉// 0FB0 - 0FBF␊
836␉// 0FC0 - 0FCF␊
837 { 0x10DE0FC0, "GeForce GT 640" },␊
838 { 0x10DE0FC1, "GeForce GT 640" },␊
839 { 0x10DE0FC2, "GeForce GT 630" },␊
840 { 0x10DE0FCE, "GeForce GT 640M LE" },␊
841␉// 0FD0 - 0FDF␊
842 { 0x10DE0FD1, "GeForce GT 650M" },␊
843␉{ 0x10DE0FD2, "GeForce GT 640M" },␊
844 { 0x10DE0FD3, "GeForce GT 640M LE" },␊
845␉{ 0x10DE0FD4, "GeForce GTX 660M" },␊
846 { 0x10DE0FD5, "GeForce GT 650M" },␊
847 { 0x10DE0FD8, "GeForce GT 640M" },␊
848␉// 0FE0 - 0FEF␊
849 { 0x10DE0FE0, "GeForce GTX 660M" },␊
850␉// 0FF0 - 0FFF␊
851 { 0x10DE0FFF, "Quadro 410" },␊
852␉// 1000 - 100F␊
853␉// 1010 - 101F␊
854␉// 1020 - 102F␊
855␉// 1030 - 103F␊
856␉// 1040 - 104F␊
857␉{ 0x10DE1040, "GeForce GT 520" },␊
858␉{ 0x10DE1042, "GeForce 510" },␊
859 { 0x10DE1048, "GeForce 605" },␊
860␉{ 0x10DE1049, "GeForce GT 620" },␊
861 { 0x10DE104A, "GeForce GT 610" },␊
862␉// 1050 - 105F␊
863␉{ 0x10DE1050, "GeForce GT 520M" },␊
864␉{ 0x10DE1051, "GeForce GT 520MX" },␊
865 { 0x10DE1052, "GeForce GT 520M" },␊
866␉{ 0x10DE1054, "GeForce GT 410M" },␊
867␉{ 0x10DE1055, "GeForce 410M" },␊
868␉{ 0x10DE1056, "Quadro NVS 4200M" },␊
869␉{ 0x10DE1057, "Quadro NVS 4200M" },␊
870 { 0x10DE1058, "GeForce 610M" },␊
871 { 0x10DE1059, "GeForce 610M" },␊
872 { 0x10DE105A, "GeForce 610M" },␊
873␉// 1060 - 106F␊
874␉// 1070 - 107F␊
875 { 0x10DE107D, "NVS 310" },␊
876␉// 1080 - 108F␊
877␉{ 0x10DE1080, "GeForce GTX 580" },␊
878␉{ 0x10DE1081, "GeForce GTX 570" },␊
879␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
880␉{ 0x10DE1084, "GeForce GTX 560" },␊
881␉{ 0x10DE1086, "GeForce GTX 570" },␊
882␉{ 0x10DE1087, "GeForce GTX 560 Ti 448" },␊
883␉{ 0x10DE1088, "GeForce GTX 590" },␊
884␉{ 0x10DE1089, "GeForce GTX 580" },␊
885␉{ 0x10DE108B, "GeForce GTX 590" },␊
886␉// 1090 - 109F␊
887␉{ 0x10DE1091, "Tesla M2090 / X2090" },␊
888␉// { 0x10DE1091, 0x0974, "Tesla X2090" },␊
889␉{ 0x10DE1094, "Tesla M2075" },␊
890␉{ 0x10DE1096, "Tesla C2075" },␊
891␉{ 0x10DE109A, "Quadro 5010M" },␊
892␉{ 0x10DE109B, "Quadro 7000" },␊
893␉// 10A0 - 10AF␊
894␉// 10B0 - 10BF␊
895␉// 10C0 - 10CF␊
896␉{ 0x10DE10C0, "GeForce 9300 GS" },␊
897␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
898␉{ 0x10DE10C5, "GeForce 405" },␊
899␉// 10D0 - 10DF␊
900␉{ 0x10DE10D8, "NVS 300" },␊
901␉// 10E0 - 10EF␊
902␉// 10F0 - 10FF␊
903␉// 1100 - 110F␊
904␉// 1110 - 111F␊
905␉// 1120 - 112F␊
906␉// 1130 - 113F␊
907␉// 1140 - 114F␊
908 { 0x10DE1140, "GeForce GT 620M / GT 630M" },␊
909␉// 1150 - 115F␊
910␉// 1160 - 116F␊
911␉// 1170 - 117F␊
912␉// 1180 - 118F␊
913␉{ 0x10DE1180, "GeForce GTX 680" },␊
914 { 0x10DE1188, "GeForce GTX 690" },␊
915 { 0x10DE1189, "GeForce GTX 670" },␊
916␉// 1190 - 119F␊
917␉// 11A0 - 11AF␊
918␉// 11B0 - 11BF␊
919␉// 11C0 - 11CF␊
920␉// 11D0 - 11DF␊
921␉// 11E0 - 11EF␊
922␉// 11F0 - 11FF␊
923␉// 1200 - 120F␊
924␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
925␉{ 0x10DE1201, "GeForce GTX 560" },␊
926␉{ 0x10DE1203, "GeForce GTX 460 SE v2" },␊
927 { 0x10DE1205, "GeForce GTX 460 v2" },␊
928 { 0x10DE1206, "GeForce GTX 555" },␊
929 { 0x10DE1207, "GeForce GT 645" },␊
930 { 0x10DE1208, "GeForce GTX 560 SE" },␊
931␉// 1210 - 121F␊
932␉{ 0x10DE1210, "GeForce GTX 570M" },␊
933␉{ 0x10DE1211, "GeForce GTX 580M" },␊
934 { 0x10DE1212, "GeForce GTX 675M" },␊
935␉{ 0x10DE1213, "GeForce GTX 670M" },␊
936␉// 1220 - 122F␊
937␉// 1230 - 123F␊
938␉// 1240 - 124F␊
939 { 0x10DE1240, "GeForce GT 620M" },␊
940␉{ 0x10DE1241, "GeForce GT 545" },␊
941␉{ 0x10DE1243, "GeForce GT 545" },␊
942␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
943␉{ 0x10DE1245, "GeForce GTS 450" },␊
944 { 0x10DE1246, "GeForce GTX 550M" },␊
945␉{ 0x10DE1247, "GeForce GT 555M / GT 635M" },␊
946␉// { 0x10DE1247, 0x212A, "GT 635M" },␊
947␉// { 0x10DE1247, 0x212B, "GT 635M" },␊
948␉// { 0x10DE1247, 0x212C, "GT 635M" },␊
949 { 0x10DE1248, "GeForce GT 555M / GT 635M" },␊
950 { 0x10DE124B, "GeForce GT 640" },␊
951 { 0x10DE1249, "GeForce GTS 450" },␊
952 { 0x10DE124B, "GeForce GT 640" },␊
953 { 0x10DE124D, "GeForce GT 555M / GT 635M" },␊
954␉// 1250 - 125F␊
955␉{ 0x10DE1251, "GeForce GTX 560M" },␊
956␉// 1260 - 126F␊
957␉// 1270 - 127F␊
958␉// 1280 - 128F␊
959␉// 1290 - 129F␊
960␉// 12A0 - 12AF␊
961␉// 12B0 - 12BF␊
962␉// 12C0 - 12CF␊
963␉// 12D0 - 12DF␊
964␉// 12E0 - 12EF␊
965␉// 12F0 - 12FF␊
966};␊
967␊
968static uint16_t swap16(uint16_t x)␊
969{␊
970␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
971}␊
972␊
973static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
974{␊
975␉uint8_t ret[2];␊
976␉␊
977␉ret[0] = ptr[offset+1];␊
978␉ret[1] = ptr[offset];␊
979␉␊
980␉return *((uint16_t*)&ret);␊
981}␊
982␊
983#if 0␊
984static uint32_t swap32(uint32_t x)␊
985{␊
986␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
987}␊
988␊
989static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
990{ ␊
991␉return ptr[offset];␊
992}␊
993␊
994static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
995{␊
996␉uint8_t ret[4];␊
997␉␊
998␉ret[0] = ptr[offset+3];␊
999␉ret[1] = ptr[offset+2];␊
1000␉ret[2] = ptr[offset+1];␊
1001␉ret[3] = ptr[offset];␊
1002␉␊
1003␉return *((uint32_t*)&ret);␊
1004}␊
1005#endif␊
1006␊
1007static int patch_nvidia_rom(uint8_t *rom)␊
1008{␊
1009␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1010␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1011␉␉return PATCH_ROM_FAILED;␊
1012␉}␊
1013␉␊
1014␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
1015␉␊
1016␉if (!dcbptr) {␊
1017␉␉printf("no dcb table found\n");␊
1018␉␉return PATCH_ROM_FAILED;␊
1019␉}␊
1020//␉else␊
1021//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1022␉ ␊
1023␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1024␉uint8_t dcbtable_version = dcbtable[0];␊
1025␉uint8_t headerlength␉ = 0;␊
1026␉uint8_t numentries␉␉ = 0;␊
1027␉uint8_t recordlength␉ = 0;␊
1028␉␊
1029␉if (dcbtable_version >= 0x20)␊
1030␉{␊
1031␉␉uint32_t sig;␊
1032␉␉␊
1033␉␉if (dcbtable_version >= 0x30)␊
1034␉␉{␊
1035␉␉␉headerlength = dcbtable[1];␊
1036␉␉␉numentries␉ = dcbtable[2];␊
1037␉␉␉recordlength = dcbtable[3];␊
1038␊
1039␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
1040␉␉}␊
1041␉␉else␊
1042␉␉{␊
1043␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
1044␉␉␉headerlength = 8;␊
1045␉␉}␊
1046␉␉␊
1047␉␉if (sig != 0x4edcbdcb)␊
1048␉␉{␊
1049␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1050␉␉␉return PATCH_ROM_FAILED;␊
1051␉␉}␊
1052␉}␊
1053␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1054␉{␊
1055␉␉char sig[8] = { 0 };␊
1056␉␉␊
1057␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1058␉␉recordlength = 10;␊
1059␉␉␊
1060␉␉if (strcmp(sig, "DEV_REC"))␊
1061␉␉{␊
1062␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1063␉␉␉return PATCH_ROM_FAILED;␊
1064␉␉}␊
1065␉}␊
1066␉else␊
1067␉{␊
1068␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1069␉␉return PATCH_ROM_FAILED;␊
1070␉}␊
1071␉␊
1072␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1073␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1074␉␊
1075␉uint8_t num_outputs = 0, i = 0;␊
1076␉␊
1077␉struct dcbentry␊
1078␉{␊
1079␉␉uint8_t type;␊
1080␉␉uint8_t index;␊
1081␉␉uint8_t *heads;␊
1082␉} entries[numentries];␊
1083␉␊
1084␉for (i = 0; i < numentries; i++)␊
1085␉{␊
1086␉␉uint32_t connection;␊
1087␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1088␊
1089␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1090␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1091␉␉␉continue;␊
1092␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1093␉␉␉continue;␊
1094␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1095␉␉␉continue;␊
1096␉␉␊
1097␉␉entries[num_outputs].type = connection & 0xf;␊
1098␉␉entries[num_outputs].index = num_outputs;␊
1099␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1100␉}␊
1101␉␊
1102␉int has_lvds = false;␊
1103␉uint8_t channel1 = 0, channel2 = 0;␊
1104␉␊
1105␉for (i = 0; i < num_outputs; i++)␊
1106␉{␊
1107␉␉if (entries[i].type == 3)␊
1108␉␉{␊
1109␉␉␉has_lvds = true;␊
1110␉␉␉//printf("found LVDS\n");␊
1111␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1112␉␉␉entries[i].type = TYPE_GROUPED;␊
1113␉␉}␊
1114␉}␊
1115␉␊
1116␉// if we have a LVDS output, we group the rest to the second channel␊
1117␉if (has_lvds)␊
1118␉{␊
1119␉␉for (i = 0; i < num_outputs; i++)␊
1120␉␉{␊
1121␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1122␉␉␉␉continue;␊
1123␉␉␉␊
1124␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1125␉␉␉entries[i].type = TYPE_GROUPED;␊
1126␉␉}␊
1127␉}␊
1128␉else␊
1129␉{␊
1130␉␉int x;␊
1131␉␉// we loop twice as we need to generate two channels␊
1132␉␉for (x = 0; x <= 1; x++)␊
1133␉␉{␊
1134␉␉␉for (i=0; i<num_outputs; i++)␊
1135␉␉␉{␊
1136␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1137␉␉␉␉␉continue;␊
1138␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1139␉␉␉␉// we always group ANALOG and TMDS␊
1140␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1141␉␉␉␉if (i && entries[i].type == 0x2)␊
1142␉␉␉␉{␊
1143␉␉␉␉␉switch (x)␊
1144␉␉␉␉␉{␊
1145␉␉␉␉␉␉case 0:␊
1146␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1147␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1148␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1149␉␉␉␉␉␉␉␊
1150␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
1151␉␉␉␉␉␉␉{␊
1152␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1153␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1154␉␉␉␉␉␉␉}␊
1155␉␉␉␉␉␉␉// group TV as well if there is one␊
1156␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1157␉␉␉␉␉␉␉{␊
1158␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1159␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1160␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1161␉␉␉␉␉␉␉}␊
1162␉␉␉␉␉␉␉break;␊
1163␉␉␉␉␉␉␊
1164␉␉␉␉␉␉case 1:␊
1165␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1166␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1167␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1168␉␉␉␉␉␉␉␊
1169␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
1170␉␉␉␉␉␉␉{␊
1171␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1172␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1173␉␉␉␉␉␉␉}␊
1174␉␉␉␉␉␉␉// group TV as well if there is one␊
1175␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1176␉␉␉␉␉␉␉{␊
1177␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1178␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1179␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1180␉␉␉␉␉␉␉}␊
1181␉␉␉␉␉␉␉break;␊
1182␉␉␉␉␉}␊
1183␉␉␉␉␉break;␊
1184␉␉␉␉}␊
1185␉␉␉}␊
1186␉␉}␊
1187␉}␊
1188␉␊
1189␉// if we have left ungrouped outputs merge them to the empty channel␊
1190␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1191␉togroup = &channel2;␊
1192␉␊
1193␉for (i = 0; i < num_outputs; i++)␊
1194␉{␊
1195␉␉if (entries[i].type != TYPE_GROUPED)␊
1196␉␉{␊
1197␉␉␉//printf("%d not grouped\n", i);␊
1198␉␉␉if (togroup)␊
1199␉␉␉{␊
1200␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1201␉␉␉}␊
1202␉␉␉entries[i].type = TYPE_GROUPED;␊
1203␉␉}␊
1204␉}␊
1205␉␊
1206␉if (channel1 > channel2)␊
1207␉{␊
1208␉␉uint8_t buff = channel1;␊
1209␉␉channel1 = channel2;␊
1210␉␉channel2 = buff;␊
1211␉}␊
1212␉␊
1213␉default_NVCAP[6] = channel1;␊
1214␉default_NVCAP[8] = channel2;␊
1215␉␊
1216␉// patching HEADS␊
1217␉for (i = 0; i < num_outputs; i++)␊
1218␉{␊
1219␉␉if (channel1 & (1 << i))␊
1220␉␉{␊
1221␉␉␉*entries[i].heads = 1;␊
1222␉␉}␊
1223␉␉else if(channel2 & (1 << i))␊
1224␉␉{␊
1225␉␉␉*entries[i].heads = 2;␊
1226␉␉}␊
1227␉}␊
1228␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1229}␊
1230␊
1231static char *get_nvidia_model(uint32_t id)␊
1232{␊
1233␉int i;␊
1234␉␊
1235␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1236␉␉if (NVKnownChipsets[i].device == id)␊
1237␉␉{␊
1238␉␉␉return NVKnownChipsets[i].name;␊
1239␉␉}␊
1240␉}␊
1241␉return NVKnownChipsets[0].name;␊
1242}␊
1243␊
1244static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1245{␊
1246␉int fd;␊
1247␉int size;␊
1248␉␊
1249␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1250␉{␊
1251␉␉return 0;␊
1252␉}␊
1253␉␊
1254␉size = file_size(fd);␊
1255␉␊
1256␉if (size > bufsize)␊
1257␉{␊
1258␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1259␉␉␉␉filename, bufsize);␊
1260␉␉size = bufsize;␊
1261␉}␊
1262␉size = read(fd, (char *)buf, size);␊
1263␉close(fd);␊
1264␉␊
1265␉return size > 0 ? size : 0;␊
1266}␊
1267␊
1268static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1269{␊
1270␉char tmp[16];␊
1271␉␊
1272␉if (!device)␊
1273␉␉return 0;␊
1274␉␊
1275␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1276␉␉return 0;␊
1277␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1278␉␉return 0;␊
1279␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1280␉␉return 0;␊
1281␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1282␉␉return 0;␊
1283␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1284␉␉return 0;␊
1285␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1286␉␉return 0;␊
1287␉if (devices_number == 1)␊
1288␉{␊
1289 if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1290 return 0;␊
1291␉}␊
1292␉else␊
1293␉{␊
1294␉␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1295␉␉␉return 0;␊
1296␉}␊
1297␉␊
1298␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1299␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1300␉sprintf(tmp, "Slot-%x",devices_number);␊
1301␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1302␉devices_number++;␊
1303␉␊
1304␉return 1;␊
1305}␊
1306␊
1307int hex2bin(const char *hex, uint8_t *bin, int len)␊
1308{␊
1309␉char␉*p;␊
1310␉int␉␉i;␊
1311␉char␉buf[3];␊
1312␉␊
1313␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1314␉␉printf("[ERROR] bin2hex input error\n");␊
1315␉␉return -1;␊
1316␉}␊
1317␉␊
1318␉buf[2] = '\0';␊
1319␉p = (char *) hex;␊
1320␉␊
1321␉for (i = 0; i < len; i++)␊
1322␉{␊
1323␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1324␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1325␉␉␉return -2;␊
1326␉␉}␊
1327␉␉buf[0] = *p++;␊
1328␉␉buf[1] = *p++;␊
1329␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1330␉}␊
1331␉return 0;␊
1332}␊
1333␊
1334unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1335{␊
1336␉unsigned long long vram_size = 0;␊
1337␉␊
1338␉if (nvCardType < NV_ARCH_50)␊
1339␉{␊
1340␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1341␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1342␉}␊
1343␉else if (nvCardType < NV_ARCH_C0)␊
1344␉{␊
1345␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1346␉␉vram_size |= (vram_size & 0xff) << 32;␊
1347␉␉vram_size &= 0xffffffff00ll;␊
1348␉}␊
1349␉else // >= NV_ARCH_C0␊
1350␉{␊
1351␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1352␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1353␉}␊
1354␉␊
1355␉// Workaround for wrong RAM size detected␊
1356␉switch (nvda_dev->device_id)␊
1357␉{␊
1358␉␉case 0x0649: // 9600M GT␊
1359 vram_size = 512*1024*1024; // 512 MB␊
1360 break;␊
1361 case 0x0A65: // GT 210␊
1362␉␉case 0x0DE0: // GT 440␊
1363␉␉case 0x0DE1: // GT 430␊
1364␉␉case 0x0DE2: // GT 420␊
1365␉␉case 0x0DEC: // GT 525M␊
1366␉␉case 0x0DF4: // GT 540M␊
1367␉␉case 0x0DF5: // GT 525M␊
1368 vram_size = 1024*1024*1024; // 1 GB␊
1369␉␉␉break;␊
1370 case 0x1251: // GTX 560M␊
1371 vram_size = 1536*1024*1024; // 1.5 GB␊
1372␉␉␉break;␊
1373␉␉default:␊
1374 break;␊
1375␉}␊
1376␉␊
1377␉return vram_size;␊
1378}␊
1379␊
1380bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1381{␊
1382␉struct DevPropDevice␉*device;␊
1383␉char␉␉␉␉␉*devicepath;␊
1384␉option_rom_pci_header_t *rom_pci_header;␊
1385␉volatile uint8_t␉␉*regs;␊
1386␉uint8_t␉␉␉␉␉*rom;␊
1387␉uint8_t␉␉␉␉␉*nvRom;␊
1388␉uint8_t␉␉␉␉␉nvCardType;␊
1389␉unsigned long long␉␉videoRam;␊
1390␉uint32_t␉␉␉␉nvBiosOveride;␊
1391␉uint32_t␉␉␉␉bar[7];␊
1392␉uint32_t␉␉␉␉boot_display;␊
1393␉int␉␉␉␉␉␉nvPatch;␊
1394␉int␉␉␉␉␉␉len;␊
1395␉char␉␉␉␉␉biosVersion[32];␊
1396␉char␉␉␉␉␉nvFilename[32];␊
1397␉char␉␉␉␉␉kNVCAP[12];␊
1398␉char␉␉␉␉␉*model;␊
1399␉const char␉␉␉␉*value;␊
1400␉bool␉␉␉␉␉doit;␊
1401␉␊
1402␉devicepath = get_pci_dev_path(nvda_dev);␊
1403␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1404␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1405␉␊
1406␉// get card type␊
1407␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1408␉␊
1409␉// Amount of VRAM in kilobytes␊
1410␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1411␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1412␉␊
1413␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1414 model, (uint32_t)(videoRam / 1024 / 1024),␊
1415 (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1416 devicepath);␊
1417␉␊
1418␉rom = malloc(NVIDIA_ROM_SIZE);␊
1419␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1420␉␉␉(uint16_t)nvda_dev->device_id);␊
1421␉␊
1422␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1423␉{␊
1424␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1425␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1426␉␉␊
1427␉␉if (nvBiosOveride > 0)␊
1428␉␉{␊
1429␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1430␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1431␉␉}␊
1432␉␉else␊
1433␉␉{␊
1434␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1435␉␉␉return false;␊
1436␉␉}␊
1437␉}␊
1438␉else␊
1439␉{␊
1440␉␉// Otherwise read bios from card␊
1441␉␉nvBiosOveride = 0;␊
1442␉␉␊
1443␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1444␉␉␊
1445␉␉// PRAMIN first␊
1446␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1447␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1448␉␉␊
1449␉␉// Valid Signature ?␊
1450␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1451␉␉{␊
1452␉␉␉// PROM next␊
1453␉␉␉// Enable PROM access␊
1454␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1455␉␉␉␊
1456␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1457␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1458␉␉␉␊
1459␉␉␉// disable PROM access␊
1460␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1461␉␉␉␊
1462␉␉␉// Valid Signature ?␊
1463␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1464␉␉␉{␊
1465␉␉␉␉// 0xC0000 last␊
1466␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1467␉␉␉␉␊
1468␉␉␉␉// Valid Signature ?␊
1469␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1470␉␉␉␉{␊
1471␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1472␉␉␉␉␉return false;␊
1473␉␉␉␉}␊
1474␉␉␉␉else␊
1475␉␉␉␉{␊
1476␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1477␉␉␉␉}␊
1478␉␉␉}␊
1479␉␉␉else␊
1480␉␉␉{␊
1481␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1482␉␉␉}␊
1483␉␉}␊
1484␉␉else␊
1485␉␉{␊
1486␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1487␉␉}␊
1488␉}␊
1489␉␊
1490␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1491␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1492␉␉//return false;␊
1493␉}␊
1494␉␊
1495␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1496␉␊
1497␉// check for 'PCIR' sig␊
1498␉if (rom_pci_header->signature == 0x50434952)␊
1499␉{␊
1500␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1501␉␉{␊
1502␉␉␉// Get Model from the OpROM␊
1503␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1504␉␉}␊
1505␉␉else␊
1506␉␉{␊
1507␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1508␉␉}␊
1509␉}␊
1510␉␊
1511␉if (!string) {␊
1512␉␉string = devprop_create_string();␊
1513␉}␊
1514␉device = devprop_add_device(string, devicepath);␊
1515␉␊
1516␉/* FIXME: for primary graphics card only */␊
1517␉boot_display = 1;␊
1518␉if (devices_number == 1)␊
1519␉{␊
1520 devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1521␉}␊
1522␉␊
1523␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1524␉␉uint8_t built_in = 0x01;␊
1525␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1526␉}␊
1527␊
1528␉// get bios version␊
1529␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1530␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1531␉␊
1532␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1533␉␊
1534␉int i, version_start;␊
1535␉int crlf_count = 0;␊
1536␉␊
1537␉// only search the first 384 bytes␊
1538␉for (i = 0; i < 0x180; i++)␊
1539␉{␊
1540␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1541␉␉{␊
1542␉␉␉crlf_count++;␊
1543␉␉␉// second 0x0D0A was found, extract bios version␊
1544␉␉␉if (crlf_count == 2)␊
1545␉␉␉{␊
1546␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1547␉␉␉␉␊
1548␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1549␉␉␉␉{␊
1550␉␉␉␉␉// find start␊
1551␉␉␉␉␉if (rom[version_start] == 0x00)␊
1552␉␉␉␉␉{␊
1553␉␉␉␉␉␉version_start++;␊
1554␉␉␉␉␉␉␊
1555␉␉␉␉␉␉// strip "Version "␊
1556␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1557␉␉␉␉␉␉{␊
1558␉␉␉␉␉␉␉version_start += 8;␊
1559␉␉␉␉␉␉}␊
1560␉␉␉␉␉␉␊
1561␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1562␉␉␉␉␉␉break;␊
1563␉␉␉␉␉}␊
1564␉␉␉␉}␊
1565␉␉␉␉break;␊
1566␉␉␉}␊
1567␉␉}␊
1568␉}␊
1569␉␊
1570␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1571␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1572␉␊
1573␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1574␉{␊
1575␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1576␉␉␊
1577␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1578␉␉{␊
1579␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1580␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1581␉␉}␊
1582␉}␊
1583␉␊
1584␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1585␉{␊
1586␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1587␉␉␊
1588␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1589␉␉{␊
1590␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1591␉␉␉␊
1592␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1593␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1594␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1595␉␉}␊
1596␉}␊
1597␉␊
1598␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1599␉{␊
1600␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1601␉␉␊
1602␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1603␉␉{␊
1604␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1605␉␉␉␊
1606␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1607␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1608␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1609␉␉}␊
1610␉}␊
1611␉␊
1612#if DEBUG_NVCAP␊
1613␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1614␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1615␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1616␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1617␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1618␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1619#endif␊
1620␉␊
1621␉devprop_add_nvidia_template(device);␊
1622␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1623␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1624␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1625␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1626␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1627␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1628␉␊
1629␉//add HDMI Audio back to nvidia␊
1630␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1631//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1632//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1633␉//end Nvidia HDMI Audio␊
1634␉␊
1635␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1636␉{␊
1637␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1638␉}␊
1639␉␊
1640␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1641␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1642␉stringlength = string->length;␊
1643␉␊
1644␉return true;␊
1645}␊
1646

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