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1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "bootstruct.h"␊
12#include "pci.h"␊
13␊
14#ifndef DEBUG_USB␊
15#define DEBUG_USB 0␊
16#endif␊
17␊
18#if DEBUG_USB␊
19#define DBG(x...)␉printf(x)␊
20#else␊
21#define DBG(x...)␊
22#endif␊
23␊
24#define kUSBBusFix␉␉␉"USBBusFix"␉␉␉␊
25#define kEHCIacquire␉␉"EHCIacquire"␉␉␊
26#define kUHCIreset␉␉␉"UHCIreset"␉␉␉␊
27#define kLegacyOff␉␉␉"USBLegacyOff"␉␉␊
28#define kEHCIhard␉␉␉"EHCIhard"␉␉␉␊
29␊
30int usb_loop();␊
31void notify_usb_dev(pci_dt_t *pci_dev);␊
32␊
33struct pciList* usbList = NULL;␊
34␊
35static int legacy_off (pci_dt_t *pci_dev);␊
36static int ehci_acquire (pci_dt_t *pci_dev);␊
37static int uhci_reset (pci_dt_t *pci_dev);␊
38␊
39// Add usb device to the list␊
40void notify_usb_dev(pci_dt_t *pci_dev)␊
41{␊
42␉struct pciList* current = usbList;␊
43␉if(!usbList)␊
44␉{␊
45␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
46 if (!usbList) {␊
47 return;␊
48 }␊
49␉␉usbList->next = NULL;␊
50␉␉usbList->pciDev = pci_dev;␊
51␉␉␊
52␉}␊
53␉else␊
54␉{␊
55␉␉while(current != NULL && current->next != NULL)␊
56␉␉{␊
57␉␉␉current = current->next;␊
58␉␉}␊
59␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
60 if (!current) {␊
61 return;␊
62 }␊
63␉␉current = current->next;␊
64␉␉␊
65␉␉current->pciDev = pci_dev;␊
66␉␉current->next = NULL;␊
67␉}␊
68}␊
69␊
70// Loop through the list and call the apropriate patch function␊
71int usb_loop(void);␊
72int usb_loop(void)␊
73{␊
74␉int retVal = 1;␊
75␉bool fix_ehci = true, fix_uhci = true, fix_usb = true, fix_legacy = true;␊
76␉␊
77␉if (getBoolForKey(kUSBBusFix, &fix_usb, DEFAULT_BOOT_CONFIG))␊
78␉{␊
79␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
80␉}␊
81␉else ␊
82␉{␊
83␉␉getBoolForKey(kEHCIacquire, &fix_ehci, DEFAULT_BOOT_CONFIG);␊
84␉␉getBoolForKey(kUHCIreset, &fix_uhci, DEFAULT_BOOT_CONFIG);␊
85␉␉getBoolForKey(kLegacyOff, &fix_legacy, DEFAULT_BOOT_CONFIG);␊
86␉}␊
87␉␉␉␉␊
88␉DBG("\n");␊
89␉struct pciList* current = usbList;␊
90␉␊
91␉while(current)␊
92␉{␊
93␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
94␉␉{␊
95␉␉␉// EHCI␊
96␉␉␉case 0x20:␊
97␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊
98␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊
99␉␉␉␉␊
100␉␉␉␉break;␊
101␉␉␉␉␊
102␉␉␉// UHCI␊
103␉␉␉case 0x00:␊
104␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊
105␊
106␉␉␉␉break;␊
107␉␉␉default:␊
108␉␉␉␉break;␊
109␉␉}␊
110␉␉␊
111␉␉current = current->next;␊
112␉}␊
113␉return retVal;␊
114}␊
115␊
116static int legacy_off (pci_dt_t *pci_dev)␊
117{␊
118␉// Set usb legacy off modification by Signal64␊
119␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
120␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
121␉// AKA: Make this run immediatly before the kernel is called␊
122␉␉␊
123␉DBG("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
124␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
125␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
126␉␊
127␉␊
128␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
129␉uint32_t capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
130␉␊
131␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
132␉uint32_t opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
133␉␊
134␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
135␉uint8_t eecp=*((unsigned char*)(capaddr + 9));␊
136␉␊
137␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
138␉␊
139␉␊
140#if DEBUG_USB␊
141 uint32_t usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
142␉uint32_t usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
143␉uint32_t usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
144␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
145 ␊
146 // read PCI Config 32bit USBLEGSUP (eecp+0) ␊
147␉uint32_t usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
148␉␊
149␉// informational only␊
150␉int isBIOSowned = !!((usblegsup) & (1 << (16)));␊
151␉int isOSowned = !!((usblegsup) & (1 << (24)));␊
152␉␊
153␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
154␉uint32_t usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
155␉␊
156␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
157#else␊
158 uint32_t usbcmd;␊
159#endif␉␊
160␉␊
161␉␊
162␉// Reset registers to Legacy OFF␊
163␉DBG("Clearing USBLEGCTLSTS\n");␊
164␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
165␉␊
166␉// if delay value is in milliseconds it doesn't appear to work. ␊
167␉// setting value to anything up to 65535 does not add the expected delay here.␊
168␉delay(100);␊
169␉␊
170␉usbcmd = *((unsigned int*)(opaddr));␊
171#if DEBUG_USB␊
172␊
173␉usbsts = *((unsigned int*)(opaddr + 4));␊
174␉usbintr = *((unsigned int*)(opaddr + 8));␊
175␉␊
176␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
177#endif␊
178␉DBG("Clearing Registers\n");␊
179␉␊
180␉// clear registers to default␊
181␉usbcmd = (usbcmd & 0xffffff00);␊
182␉*((unsigned int*)(opaddr)) = usbcmd;␊
183␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
184␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
185␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
186␉␊
187␉␊
188#if DEBUG_USB␊
189 // get the results␊
190␉usbcmd = *((unsigned int*)(opaddr));␊
191␉usbsts = *((unsigned int*)(opaddr + 4));␊
192␉usbintr = *((unsigned int*)(opaddr + 8));␊
193␉␊
194␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
195 ␊
196 // read 32bit USBLEGSUP (eecp+0) ␊
197␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
198␉␊
199␉// informational only␊
200␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
201␉isOSowned = !!((usblegsup) & (1 << (24)));␊
202␉␊
203␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
204␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
205␉␊
206␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
207#endif␉␊
208␉␊
209␉DBG("Legacy USB Off Done\n");␉␊
210␉return 1;␊
211}␊
212␊
213static int ehci_acquire (pci_dt_t *pci_dev)␊
214{␊
215␉int␉␉j, k;␉␊
216␉uint8_t␉␉legacy[8];␊
217␉bool␉␉alwaysHardBIOSReset = false;␊
218␉␉␊
219␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, DEFAULT_BOOT_CONFIG)) {␊
220␉␉alwaysHardBIOSReset = true;␊
221␉}␊
222␊
223␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
224␉uint32_t base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
225␊
226␉DBG("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
227␉␉pci_dev->vendor_id, pci_dev->device_id,␊
228␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
229␉␉base);␊
230␊
231␉if (*((unsigned char*)base) < 0xc)␊
232␉{␊
233␉␉DBG("Config space too small: no legacy implementation\n");␊
234␉␉return 1;␊
235␉}␊
236␉uint8_t eecp = *((unsigned char*)(base + 9));␊
237␉if (!eecp) {␊
238␉␉DBG("No extended capabilities: no legacy implementation\n");␊
239␉␉return 1;␊
240␉}␊
241␊
242␉DBG("eecp=%x\n",eecp);␊
243␊
244␉// bad way to do it␊
245␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
246␉for (j = 0; j < 8; j++) {␊
247␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
248␉␉DBG("%02x ", legacy[j]);␊
249␉}␊
250␉DBG("\n");␊
251␊
252␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
253␉//We try soft reset first - some systems hang on reboot with hard reset␊
254␉// Definitely needed during reboot on 10.4.6␊
255␊
256␉bool isOwnershipConflict = (((legacy[3] & 1) != 0) && ((legacy[2] & 1) != 0));␊
257␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
258␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
259␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
260␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
261␉␉for (k = 0; k < 25; k++) {␊
262␉␉␉for (j = 0; j < 8; j++) {␊
263␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
264␉␉␉}␊
265␉␉␉if (legacy[3] == 0) {␊
266␉␉␉␉break;␊
267␉␉␉}␊
268␉␉␉delay(10);␊
269␉␉}␊
270␉}␉␊
271␊
272␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
273␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
274␊
275␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
276␉for (k = 0; k < 25; k++) {␊
277␉␉for (j = 0;j < 8; j++) {␊
278␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
279␉␉}␊
280␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
281␉␉if (legacy[2] == 0) {␊
282␉␉␉break;␊
283␉␉}␊
284␉␉delay(10);␊
285␉}␊
286␊
287␉for (j = 0;j < 8; j++) {␊
288␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
289␉}␊
290␉isOwnershipConflict = ((legacy[2]) != 0);␊
291␉if (isOwnershipConflict) {␊
292␉␉// Soft reset has failed. Assume SMI being ignored␊
293␉␉// Hard reset␊
294␉␉// Force Clear BIOS BIT␊
295␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
296␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
297␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
298␊
299␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
300␉␉for (k = 0; k < 25; k++) {␊
301␉␉␉for (j = 0; j < 8; j++) {␊
302␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
303␉␉␉}␊
304␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
305␊
306␉␉␉if ((legacy[2]) == 0) {␊
307␉␉␉␉break;␊
308␉␉␉}␊
309␉␉␉delay(10);␉␊
310␉␉}␉␉␊
311␉␉// Disable further SMI events␊
312␉␉for (j = 4; j < 8; j++) {␊
313␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
314␉␉}␊
315␉}␊
316␊
317␉for (j = 0; j < 8; j++) {␊
318␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
319␉}␊
320␊
321␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
322␊
323␉// Final Ownership Resolution Check...␊
324␉if (legacy[2] & 1) {␉␉␉␉␉␊
325␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
326␉␉return 0;␊
327␉}␊
328␊
329␉DBG("EHCI Acquire OS Ownership done\n");␉␊
330␉return 1;␊
331}␊
332␊
333static int uhci_reset (pci_dt_t *pci_dev)␊
334{␊
335␉uint32_t base, port_base;␊
336␉␊
337␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
338␉port_base = (base >> 5) & 0x07ff;␊
339␊
340␉DBG("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
341␉␉pci_dev->vendor_id, pci_dev->device_id,␊
342␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
343␉␉port_base, base);␊
344␉␊
345␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
346␊
347␉outw (port_base, 0x0002);␊
348␉delay(10);␊
349␉outw (port_base+4,0);␊
350␉delay(10);␊
351␉outw (port_base,0);␊
352␉return 1;␊
353}␊
354

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