| 1 | /*␊ |
| 2 | *␊ |
| 3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
| 4 | *␊ |
| 5 | */␊ |
| 6 | ␊ |
| 7 | #ifndef __LIBSAIO_PCI_H␊ |
| 8 | #define __LIBSAIO_PCI_H␊ |
| 9 | ␊ |
| 10 | typedef struct {␊ |
| 11 | ␉uint32_t␉␉:2;␊ |
| 12 | ␉uint32_t␉reg␉:6;␊ |
| 13 | ␉uint32_t␉func:3;␊ |
| 14 | ␉uint32_t␉dev␉:5;␊ |
| 15 | ␉uint32_t␉bus␉:8;␊ |
| 16 | ␉uint32_t␉␉:7;␊ |
| 17 | ␉uint32_t␉eb␉:1;␊ |
| 18 | } pci_addr_t;␊ |
| 19 | ␊ |
| 20 | typedef union {␊ |
| 21 | ␉pci_addr_t␉bits;␊ |
| 22 | ␉uint32_t␉addr;␊ |
| 23 | } pci_dev_t;␊ |
| 24 | ␊ |
| 25 | typedef struct pci_dt_t {␊ |
| 26 | ␉pci_dev_t␉␉dev;␊ |
| 27 | ␊ |
| 28 | ␉uint16_t␉vendor_id;␊ |
| 29 | ␉uint16_t␉device_id;␊ |
| 30 | ␉␊ |
| 31 | ␉union {␊ |
| 32 | ␉␉struct {␊ |
| 33 | ␉␉␉uint16_t␉vendor_id;␊ |
| 34 | ␉␉␉uint16_t␉device_id;␊ |
| 35 | ␉␉}␉␉␉subsys;␊ |
| 36 | ␉␉uint32_t␉subsys_id;␊ |
| 37 | ␉}␉␉␉␉␉␉subsys_id;␊ |
| 38 | ␉␊ |
| 39 | ␉uint16_t␉class_id;␉␊ |
| 40 | ␊ |
| 41 | ␉struct pci_dt_t␉*parent;␊ |
| 42 | ␉struct pci_dt_t␉*children;␊ |
| 43 | ␉struct pci_dt_t␉*next;␊ |
| 44 | } pci_dt_t;␊ |
| 45 | ␊ |
| 46 | struct pciList␊ |
| 47 | {␊ |
| 48 | ␉pci_dt_t* pciDev;␊ |
| 49 | ␉struct pciList* next;␊ |
| 50 | };␊ |
| 51 | ␊ |
| 52 | #define PCIADDR(bus, dev, func)␉(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)␊ |
| 53 | #define PCI_ADDR_REG␉␉0xcf8␊ |
| 54 | #define PCI_DATA_REG␉␉0xcfc␊ |
| 55 | ␊ |
| 56 | extern pci_dt_t␉␉*root_pci_dev;␊ |
| 57 | extern uint8_t␉␉pci_config_read8(uint32_t, uint8_t);␊ |
| 58 | extern uint16_t␉␉pci_config_read16(uint32_t, uint8_t);␊ |
| 59 | extern uint32_t␉␉pci_config_read32(uint32_t, uint8_t);␊ |
| 60 | extern void␉␉pci_config_write8(uint32_t, uint8_t, uint8_t);␊ |
| 61 | extern void␉␉pci_config_write16(uint32_t, uint8_t, uint16_t);␊ |
| 62 | extern void␉␉pci_config_write32(uint32_t, uint8_t, uint32_t);␊ |
| 63 | //extern char␉␉*get_pci_dev_path(pci_dt_t *);␊ |
| 64 | extern void␉␉build_pci_dt(void);␊ |
| 65 | extern void␉␉dump_pci_dt(pci_dt_t *);␊ |
| 66 | extern void␉␉setup_pci_devs(pci_dt_t *pci_dt);␊ |
| 67 | extern int getPciRootUID(void);␊ |
| 68 | ␊ |
| 69 | //-----------------------------------------------------------------------------␊ |
| 70 | // added by iNDi␊ |
| 71 | ␊ |
| 72 | struct pci_rom_pci_header_t {␊ |
| 73 | ␉uint32_t␉signature;␉␉␉// 0x50434952 'PCIR'␊ |
| 74 | ␉uint16_t␉vendor;␊ |
| 75 | ␉uint16_t␉device;␊ |
| 76 | ␉uint16_t␉product;␊ |
| 77 | ␉uint16_t␉length;␊ |
| 78 | ␉uint8_t␉␉revision;␉␉␉// 0 = PCI 2.1␊ |
| 79 | ␉uint8_t␉␉class[3];␊ |
| 80 | ␉uint16_t␉rom_size;␉␉␉␊ |
| 81 | ␉uint16_t␉code_revision;␊ |
| 82 | ␉uint8_t␉␉code_type;␉␉␉// 0 = x86␊ |
| 83 | ␉uint8_t␉␉last_image;␉␉␉// 0x80␊ |
| 84 | ␉uint16_t␉reserverd;␊ |
| 85 | };␊ |
| 86 | ␊ |
| 87 | struct pci_rom_pnp_header_t {␊ |
| 88 | ␉uint32_t␉signature;␉␉␉// 0x24506E50 '$PnP'␊ |
| 89 | ␉uint8_t␉␉revision;␉␉␉// 1␊ |
| 90 | ␉uint8_t␉␉length;␉␉␉␉//␊ |
| 91 | ␉uint16_t␉offset;␉␉␉␉␊ |
| 92 | ␉uint8_t␉␉checksum;␊ |
| 93 | ␉uint32_t␉identifier;␊ |
| 94 | ␉uint16_t␉manufacturer;␊ |
| 95 | ␉uint16_t␉product;␊ |
| 96 | ␉uint8_t␉␉class[3];␊ |
| 97 | ␉uint8_t␉␉indicators;␊ |
| 98 | ␉uint16_t␉boot_vector;␊ |
| 99 | ␉uint16_t␉disconnect_vector;␊ |
| 100 | ␉uint16_t␉bootstrap_vector;␊ |
| 101 | ␉uint16_t␉reserved;␊ |
| 102 | ␉uint16_t␉resource_vector;␊ |
| 103 | };␊ |
| 104 | ␊ |
| 105 | struct pci_rom_bios_t {␊ |
| 106 | ␉uint16_t␉signature;␉␉␉// 0x55AA␊ |
| 107 | ␉uint8_t␉␉size;␉␉␉␉// Multiples of 512␊ |
| 108 | ␉uint32_t␉entry_point;␊ |
| 109 | ␉uint8_t␉␉reserved[15];␊ |
| 110 | ␉uint16_t␉pci_header;␊ |
| 111 | ␉uint16_t␉pnp_header;␊ |
| 112 | };␊ |
| 113 | ␊ |
| 114 | /*␊ |
| 115 | * Under PCI, each device has 256 bytes of configuration address space,␊ |
| 116 | * of which the first 64 bytes are standardized as follows:␊ |
| 117 | */␊ |
| 118 | ␊ |
| 119 | #define PCI_VENDOR_ID␉␉␉␉0x00␉/* 16 bits */␊ |
| 120 | #define PCI_DEVICE_ID␉␉␉␉0x02␉/* 16 bits */␊ |
| 121 | #define PCI_COMMAND␉␉␉␉␉0x04␉/* 16 bits */␊ |
| 122 | #define PCI_COMMAND_IO␉␉␉␉0x1␉␉/* Enable response in I/O space */␊ |
| 123 | #define PCI_COMMAND_MEMORY␉␉␉0x2␉␉/* Enable response in Memory space */␊ |
| 124 | #define PCI_COMMAND_MASTER␉␉␉0x4␉␉/* Enable bus mastering */␊ |
| 125 | #define PCI_COMMAND_SPECIAL␉␉␉0x8␉␉/* Enable response to special cycles */␊ |
| 126 | #define PCI_COMMAND_INVALIDATE␉␉0x10␉/* Use memory write and invalidate */␊ |
| 127 | #define PCI_COMMAND_VGA_PALETTE␉␉0x20␉/* Enable palette snooping */␊ |
| 128 | #define PCI_COMMAND_PARITY␉␉␉0x40␉/* Enable parity checking */␊ |
| 129 | #define PCI_COMMAND_WAIT␉␉␉0x80␉/* Enable address/data stepping */␊ |
| 130 | #define PCI_COMMAND_SERR␉␉␉0x100␉/* Enable SERR */␊ |
| 131 | #define PCI_COMMAND_FAST_BACK␉␉0x200␉/* Enable back-to-back writes */␊ |
| 132 | #define PCI_COMMAND_DISABLE_INTx␉0x400␉/* PCIE: Disable INTx interrupts */␊ |
| 133 | ␊ |
| 134 | #define PCI_STATUS␉␉␉␉␉0x06␉/* 16 bits */␊ |
| 135 | #define PCI_STATUS_INTx␉␉␉␉0x08␉/* PCIE: INTx interrupt pending */␊ |
| 136 | #define PCI_STATUS_CAP_LIST␉␉␉0x10␉/* Support Capability List */␊ |
| 137 | #define PCI_STATUS_66MHZ␉␉␉0x20␉/* Support 66 Mhz PCI 2.1 bus */␊ |
| 138 | #define PCI_STATUS_UDF␉␉␉␉0x40␉/* Support User Definable Features [obsolete] */␊ |
| 139 | #define PCI_STATUS_FAST_BACK␉␉0x80␉/* Accept fast-back to back */␊ |
| 140 | #define PCI_STATUS_PARITY␉␉␉0x100␉/* Detected parity error */␊ |
| 141 | #define PCI_STATUS_DEVSEL_MASK␉␉0x600␉/* DEVSEL timing */␊ |
| 142 | #define PCI_STATUS_DEVSEL_FAST␉␉0x000␊ |
| 143 | #define PCI_STATUS_DEVSEL_MEDIUM␉0x200␊ |
| 144 | #define PCI_STATUS_DEVSEL_SLOW␉␉0x400␊ |
| 145 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800␉/* Set on target abort */␊ |
| 146 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000␉/* Master ack of " */␊ |
| 147 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000␉/* Set on master abort */␊ |
| 148 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000␉/* Set when we drive SERR */␊ |
| 149 | #define PCI_STATUS_DETECTED_PARITY␉0x8000␉/* Set on parity error */␊ |
| 150 | ␊ |
| 151 | #define PCI_CLASS_REVISION␉␉␉0x08␉/* High 24 bits are class, low 8 revision */␊ |
| 152 | #define PCI_REVISION_ID␉␉␉␉0x08 /* Revision ID */␊ |
| 153 | #define PCI_CLASS_PROG␉␉␉␉0x09 /* Reg. Level Programming Interface */␊ |
| 154 | #define PCI_CLASS_DEVICE␉␉␉0x0a /* Device class */␊ |
| 155 | ␊ |
| 156 | #define PCI_CACHE_LINE_SIZE␉␉␉0x0c␉/* 8 bits */␊ |
| 157 | #define PCI_LATENCY_TIMER␉␉␉0x0d␉/* 8 bits */␊ |
| 158 | #define PCI_HEADER_TYPE␉␉␉␉0x0e␉/* 8 bits */␊ |
| 159 | #define PCI_HEADER_TYPE_NORMAL␉␉0␊ |
| 160 | #define PCI_HEADER_TYPE_BRIDGE␉␉1␊ |
| 161 | #define PCI_HEADER_TYPE_CARDBUS␉␉2␉␊ |
| 162 | ␊ |
| 163 | #define PCI_BIST␉␉␉␉␉0x0f␉/* 8 bits */␊ |
| 164 | #define PCI_BIST_CODE_MASK␉␉␉0x0f␉/* Return result */␊ |
| 165 | #define PCI_BIST_START␉␉␉␉0x40␉/* 1 to start BIST, 2 secs or less */␊ |
| 166 | #define PCI_BIST_CAPABLE␉␉␉0x80␉/* 1 if BIST capable */␊ |
| 167 | ␊ |
| 168 | /*␊ |
| 169 | * Base addresses specify locations in memory or I/O space.␊ |
| 170 | * Decoded size can be determined by writing a value of␊ |
| 171 | * 0xffffffff to the register, and reading it back. Only␊ |
| 172 | * 1 bits are decoded.␊ |
| 173 | */␊ |
| 174 | #define PCI_BASE_ADDRESS_0␉␉␉␉0x10␉/* 32 bits */␊ |
| 175 | #define PCI_BASE_ADDRESS_1␉␉␉␉0x14␉/* 32 bits [htype 0,1 only] */␊ |
| 176 | #define PCI_BASE_ADDRESS_2␉␉␉␉0x18␉/* 32 bits [htype 0 only] */␊ |
| 177 | #define PCI_BASE_ADDRESS_3␉␉␉␉0x1c␉/* 32 bits */␊ |
| 178 | #define PCI_BASE_ADDRESS_4␉␉␉␉0x20␉/* 32 bits */␊ |
| 179 | #define PCI_BASE_ADDRESS_5␉␉␉␉0x24␉/* 32 bits */␊ |
| 180 | #define PCI_BASE_ADDRESS_SPACE␉␉␉0x01␉/* 0 = memory, 1 = I/O */␊ |
| 181 | #define PCI_BASE_ADDRESS_SPACE_IO␉␉0x01␊ |
| 182 | #define PCI_BASE_ADDRESS_SPACE_MEMORY␉0x00␊ |
| 183 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉0x06␊ |
| 184 | #define PCI_BASE_ADDRESS_MEM_TYPE_32␉0x00␉/* 32 bit address */␊ |
| 185 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M␉0x02␉/* Below 1M [obsolete] */␊ |
| 186 | #define PCI_BASE_ADDRESS_MEM_TYPE_64␉0x04␉/* 64 bit address */␊ |
| 187 | #define PCI_BASE_ADDRESS_MEM_PREFETCH␉0x08␉/* prefetchable? */␊ |
| 188 | #define PCI_BASE_ADDRESS_MEM_MASK␉(~(pciaddr_t)0x0f)␊ |
| 189 | #define PCI_BASE_ADDRESS_IO_MASK␉(~(pciaddr_t)0x03)␊ |
| 190 | /* bit 1 is reserved if address_space = 1 */␊ |
| 191 | ␊ |
| 192 | /* Header type 0 (normal devices) */␊ |
| 193 | #define PCI_CARDBUS_CIS␉␉␉␉␉0x28␊ |
| 194 | #define PCI_SUBSYSTEM_VENDOR_ID␉␉␉0x2c␊ |
| 195 | #define PCI_SUBSYSTEM_ID␉␉␉␉0x2e␊ |
| 196 | #define PCI_ROM_ADDRESS␉␉␉␉␉0x30␉␉/* Bits 31..11 are address, 10..1 reserved */␊ |
| 197 | #define PCI_ROM_ADDRESS_ENABLE␉␉␉0x01␊ |
| 198 | #define PCI_ROM_ADDRESS_MASK␉(~(pciaddr_t)0x7ff)␊ |
| 199 | ␊ |
| 200 | #define PCI_CAPABILITY_LIST␉␉␉␉0x34␉␉/* Offset of first capability list entry */␊ |
| 201 | ␊ |
| 202 | /* 0x35-0x3b are reserved */␊ |
| 203 | #define PCI_INTERRUPT_LINE␉␉␉␉0x3c␉␉/* 8 bits */␊ |
| 204 | #define PCI_INTERRUPT_PIN␉␉␉␉0x3d␉␉/* 8 bits */␊ |
| 205 | #define PCI_MIN_GNT␉␉␉␉␉␉0x3e␉␉/* 8 bits */␊ |
| 206 | #define PCI_MAX_LAT␉␉␉␉␉␉0x3f␉␉/* 8 bits */␊ |
| 207 | ␊ |
| 208 | /* Header type 1 (PCI-to-PCI bridges) */␊ |
| 209 | #define PCI_PRIMARY_BUS␉␉␉␉␉0x18␉␉/* Primary bus number */␊ |
| 210 | #define PCI_SECONDARY_BUS␉␉␉␉0x19␉␉/* Secondary bus number */␊ |
| 211 | #define PCI_SUBORDINATE_BUS␉␉␉␉0x1a␉␉/* Highest bus number behind the bridge */␊ |
| 212 | #define PCI_SEC_LATENCY_TIMER␉␉␉0x1b␉␉/* Latency timer for secondary interface */␊ |
| 213 | #define PCI_IO_BASE␉␉␉␉␉␉0x1c␉␉/* I/O range behind the bridge */␊ |
| 214 | #define PCI_IO_LIMIT␉␉␉␉␉0x1d␊ |
| 215 | #define PCI_IO_RANGE_TYPE_MASK␉␉␉0x0f␉␉/* I/O bridging type */␊ |
| 216 | #define PCI_IO_RANGE_TYPE_16␉␉␉0x00␊ |
| 217 | #define PCI_IO_RANGE_TYPE_32␉␉␉0x01␊ |
| 218 | #define PCI_IO_RANGE_MASK␉␉␉␉~0x0f␊ |
| 219 | #define PCI_SEC_STATUS␉␉␉␉␉0x1e␉␉/* Secondary status register */␊ |
| 220 | #define PCI_MEMORY_BASE␉␉␉␉␉0x20␉␉/* Memory range behind */␊ |
| 221 | #define PCI_MEMORY_LIMIT␉␉␉␉0x22␊ |
| 222 | #define PCI_MEMORY_RANGE_TYPE_MASK␉␉0x0f␊ |
| 223 | #define PCI_MEMORY_RANGE_MASK␉␉␉~0x0f␊ |
| 224 | #define PCI_PREF_MEMORY_BASE␉␉␉0x24␉␉/* Prefetchable memory range behind */␊ |
| 225 | #define PCI_PREF_MEMORY_LIMIT␉␉␉0x26␊ |
| 226 | #define PCI_PREF_RANGE_TYPE_MASK␉␉0x0f␊ |
| 227 | #define PCI_PREF_RANGE_TYPE_32␉␉␉0x00␊ |
| 228 | #define PCI_PREF_RANGE_TYPE_64␉␉␉0x01␊ |
| 229 | #define PCI_PREF_RANGE_MASK␉␉␉␉~0x0f␊ |
| 230 | #define PCI_PREF_BASE_UPPER32␉␉␉0x28␉␉/* Upper half of prefetchable memory range */␊ |
| 231 | #define PCI_PREF_LIMIT_UPPER32␉␉␉0x2c␊ |
| 232 | #define PCI_IO_BASE_UPPER16␉␉␉␉0x30␉␉/* Upper half of I/O addresses */␊ |
| 233 | #define PCI_IO_LIMIT_UPPER16␉␉␉0x32␊ |
| 234 | /* 0x34 same as for htype 0 */␊ |
| 235 | /* 0x35-0x3b is reserved */␊ |
| 236 | #define PCI_ROM_ADDRESS1␉␉␉␉0x38␉␉/* Same as PCI_ROM_ADDRESS, but for htype 1 */␊ |
| 237 | /* 0x3c-0x3d are same as for htype 0 */␊ |
| 238 | #define PCI_BRIDGE_CONTROL␉␉␉␉0x3e␊ |
| 239 | #define PCI_BRIDGE_CTL_PARITY␉␉␉0x01␉␉/* Enable parity detection on secondary interface */␊ |
| 240 | #define PCI_BRIDGE_CTL_SERR␉␉␉␉0x02␉␉/* The same for SERR forwarding */␊ |
| 241 | #define PCI_BRIDGE_CTL_NO_ISA␉␉␉0x04␉␉/* Disable bridging of ISA ports */␊ |
| 242 | #define PCI_BRIDGE_CTL_VGA␉␉␉␉0x08␉␉/* Forward VGA addresses */␊ |
| 243 | #define PCI_BRIDGE_CTL_MASTER_ABORT␉␉0x20␉␉/* Report master aborts */␊ |
| 244 | #define PCI_BRIDGE_CTL_BUS_RESET␉␉0x40␉␉/* Secondary bus reset */␊ |
| 245 | #define PCI_BRIDGE_CTL_FAST_BACK␉␉0x80␉␉/* Fast Back2Back enabled on secondary interface */␊ |
| 246 | #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100␉␉/* PCI-X? */␊ |
| 247 | #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200␉␉/* PCI-X? */␊ |
| 248 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400␉/* PCI-X? */␊ |
| 249 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800␉/* PCI-X? */␊ |
| 250 | ␊ |
| 251 | /* Header type 2 (CardBus bridges) */␊ |
| 252 | /* 0x14-0x15 reserved */␊ |
| 253 | #define PCI_CB_SEC_STATUS␉␉␉␉0x16␉␉/* Secondary status */␊ |
| 254 | #define PCI_CB_PRIMARY_BUS␉␉␉␉0x18␉␉/* PCI bus number */␊ |
| 255 | #define PCI_CB_CARD_BUS␉␉␉␉␉0x19␉␉/* CardBus bus number */␊ |
| 256 | #define PCI_CB_SUBORDINATE_BUS␉␉␉0x1a␉␉/* Subordinate bus number */␊ |
| 257 | #define PCI_CB_LATENCY_TIMER␉␉␉0x1b␉␉/* CardBus latency timer */␊ |
| 258 | #define PCI_CB_MEMORY_BASE_0␉␉␉0x1c␊ |
| 259 | #define PCI_CB_MEMORY_LIMIT_0␉␉␉0x20␊ |
| 260 | #define PCI_CB_MEMORY_BASE_1␉␉␉0x24␊ |
| 261 | #define PCI_CB_MEMORY_LIMIT_1␉␉␉0x28␊ |
| 262 | #define PCI_CB_IO_BASE_0␉␉␉␉0x2c␊ |
| 263 | #define PCI_CB_IO_BASE_0_HI␉␉␉␉0x2e␊ |
| 264 | #define PCI_CB_IO_LIMIT_0␉␉␉␉0x30␊ |
| 265 | #define PCI_CB_IO_LIMIT_0_HI␉␉␉0x32␊ |
| 266 | #define PCI_CB_IO_BASE_1␉␉␉␉0x34␊ |
| 267 | #define PCI_CB_IO_BASE_1_HI␉␉␉␉0x36␊ |
| 268 | #define PCI_CB_IO_LIMIT_1␉␉␉␉0x38␊ |
| 269 | #define PCI_CB_IO_LIMIT_1_HI␉␉␉0x3a␊ |
| 270 | #define PCI_CB_IO_RANGE_MASK␉␉␉~0x03␊ |
| 271 | /* 0x3c-0x3d are same as for htype 0 */␊ |
| 272 | #define PCI_CB_BRIDGE_CONTROL␉␉␉0x3e␊ |
| 273 | #define PCI_CB_BRIDGE_CTL_PARITY␉␉0x01␉␉/* Similar to standard bridge control register */␊ |
| 274 | #define PCI_CB_BRIDGE_CTL_SERR␉␉␉0x02␊ |
| 275 | #define PCI_CB_BRIDGE_CTL_ISA␉␉␉0x04␊ |
| 276 | #define PCI_CB_BRIDGE_CTL_VGA␉␉␉0x08␊ |
| 277 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉0x20␊ |
| 278 | #define PCI_CB_BRIDGE_CTL_CB_RESET␉␉0x40␉␉/* CardBus reset */␊ |
| 279 | #define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉0x80␉␉/* Enable interrupt for 16-bit cards */␊ |
| 280 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100␉␉/* Prefetch enable for both memory regions */␊ |
| 281 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200␊ |
| 282 | #define PCI_CB_BRIDGE_CTL_POST_WRITES␉0x400␊ |
| 283 | #define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉0x40␊ |
| 284 | #define PCI_CB_SUBSYSTEM_ID␉␉␉␉0x42␊ |
| 285 | #define PCI_CB_LEGACY_MODE_BASE␉␉␉0x44␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊ |
| 286 | /* 0x48-0x7f reserved */␊ |
| 287 | ␊ |
| 288 | /* Capability lists */␊ |
| 289 | #define PCI_CAP_LIST_ID␉␉␉␉␉0␉␉␉/* Capability ID */␊ |
| 290 | #define PCI_CAP_ID_PM␉␉␉␉␉0x01␉␉/* Power Management */␊ |
| 291 | #define PCI_CAP_ID_AGP␉␉␉␉␉0x02␉␉/* Accelerated Graphics Port */␊ |
| 292 | #define PCI_CAP_ID_VPD␉␉␉␉␉0x03␉␉/* Vital Product Data */␊ |
| 293 | #define PCI_CAP_ID_SLOTID␉␉␉␉0x04␉␉/* Slot Identification */␊ |
| 294 | #define PCI_CAP_ID_MSI␉␉␉␉␉0x05␉␉/* Message Signaled Interrupts */␊ |
| 295 | #define PCI_CAP_ID_CHSWP␉␉␉␉0x06␉␉/* CompactPCI HotSwap */␊ |
| 296 | #define PCI_CAP_ID_PCIX␉␉␉␉␉0x07␉␉/* PCI-X */␊ |
| 297 | #define PCI_CAP_ID_HT␉␉␉␉␉0x08␉␉/* HyperTransport */␊ |
| 298 | #define PCI_CAP_ID_VNDR␉␉␉␉␉0x09␉␉/* Vendor specific */␊ |
| 299 | #define PCI_CAP_ID_DBG␉␉␉␉␉0x0A␉␉/* Debug port */␊ |
| 300 | #define PCI_CAP_ID_CCRC␉␉␉␉␉0x0B␉␉/* CompactPCI Central Resource Control */␊ |
| 301 | #define PCI_CAP_ID_HOTPLUG␉␉␉␉0x0C␉␉/* PCI hot-plug */␊ |
| 302 | #define PCI_CAP_ID_SSVID␉␉␉␉0x0D␉␉/* Bridge subsystem vendor/device ID */␊ |
| 303 | #define PCI_CAP_ID_AGP3␉␉␉␉␉0x0E␉␉/* AGP 8x */␊ |
| 304 | #define PCI_CAP_ID_SECURE␉␉␉␉0x0F␉␉/* Secure device (?) */␊ |
| 305 | #define PCI_CAP_ID_EXP␉␉␉␉␉0x10␉␉/* PCI Express */␊ |
| 306 | #define PCI_CAP_ID_MSIX␉␉␉␉␉0x11␉␉/* MSI-X */␊ |
| 307 | #define PCI_CAP_ID_SATA␉␉␉␉␉0x12␉␉/* Serial-ATA HBA */␊ |
| 308 | #define PCI_CAP_ID_AF␉␉␉␉␉0x13␉␉/* Advanced features of PCI devices integrated in PCIe root cplx */␊ |
| 309 | #define PCI_CAP_LIST_NEXT␉␉␉␉1␉␉␉/* Next capability in the list */␊ |
| 310 | #define PCI_CAP_FLAGS␉␉␉␉␉2␉␉␉/* Capability defined flags (16 bits) */␊ |
| 311 | #define PCI_CAP_SIZEOF␉␉␉␉␉4␊ |
| 312 | ␊ |
| 313 | /* Capabilities residing in the PCI Express extended configuration space */␊ |
| 314 | ␊ |
| 315 | #define PCI_EXT_CAP_ID_AER␉␉␉␉0x01␉␉/* Advanced Error Reporting */␊ |
| 316 | #define PCI_EXT_CAP_ID_VC␉␉␉␉0x02␉␉/* Virtual Channel */␊ |
| 317 | #define PCI_EXT_CAP_ID_DSN␉␉␉␉0x03␉␉/* Device Serial Number */␊ |
| 318 | #define PCI_EXT_CAP_ID_PB␉␉␉␉0x04␉␉/* Power Budgeting */␊ |
| 319 | #define PCI_EXT_CAP_ID_RCLINK␉␉␉0x05␉␉/* Root Complex Link Declaration */␊ |
| 320 | #define PCI_EXT_CAP_ID_RCILINK␉␉␉0x06␉␉/* Root Complex Internal Link Declaration */␊ |
| 321 | #define PCI_EXT_CAP_ID_RCECOLL␉␉␉0x07␉␉/* Root Complex Event Collector */␊ |
| 322 | #define PCI_EXT_CAP_ID_MFVC␉␉␉␉0x08␉␉/* Multi-Function Virtual Channel */␊ |
| 323 | #define PCI_EXT_CAP_ID_RBCB␉␉␉␉0x0a␉␉/* Root Bridge Control Block */␊ |
| 324 | #define PCI_EXT_CAP_ID_VNDR␉␉␉␉0x0b␉␉/* Vendor specific */␊ |
| 325 | #define PCI_EXT_CAP_ID_ACS␉␉␉␉0x0d␉␉/* Access Controls */␊ |
| 326 | #define PCI_EXT_CAP_ID_ARI␉␉␉␉0x0e␉␉/* Alternative Routing-ID Interpretation */␊ |
| 327 | #define PCI_EXT_CAP_ID_ATS␉␉␉␉0x0f␉␉/* Address Translation Service */␊ |
| 328 | #define PCI_EXT_CAP_ID_SRIOV␉␉␉0x10␉␉/* Single Root I/O Virtualization */␊ |
| 329 | ␊ |
| 330 | /* Power Management Registers */␊ |
| 331 | ␊ |
| 332 | #define PCI_PM_CAP_VER_MASK␉␉␉␉0x0007␉␉/* Version (2=PM1.1) */␊ |
| 333 | #define PCI_PM_CAP_PME_CLOCK␉␉␉0x0008␉␉/* Clock required for PME generation */␊ |
| 334 | #define PCI_PM_CAP_DSI␉␉␉␉␉0x0020␉␉/* Device specific initialization required */␊ |
| 335 | #define PCI_PM_CAP_AUX_C_MASK␉␉␉0x01c0␉␉/* Maximum aux current required in D3cold */␊ |
| 336 | #define PCI_PM_CAP_D1␉␉␉␉␉0x0200␉␉/* D1 power state support */␊ |
| 337 | #define PCI_PM_CAP_D2␉␉␉␉␉0x0400␉␉/* D2 power state support */␊ |
| 338 | #define PCI_PM_CAP_PME_D0␉␉␉␉0x0800␉␉/* PME can be asserted from D0 */␊ |
| 339 | #define PCI_PM_CAP_PME_D1␉␉␉␉0x1000␉␉/* PME can be asserted from D1 */␊ |
| 340 | #define PCI_PM_CAP_PME_D2␉␉␉␉0x2000␉␉/* PME can be asserted from D2 */␊ |
| 341 | #define PCI_PM_CAP_PME_D3_HOT␉␉␉0x4000␉␉/* PME can be asserted from D3hot */␊ |
| 342 | #define PCI_PM_CAP_PME_D3_COLD␉␉␉0x8000␉␉/* PME can be asserted from D3cold */␊ |
| 343 | #define PCI_PM_CTRL␉␉␉␉␉␉4␉␉␉/* PM control and status register */␊ |
| 344 | #define PCI_PM_CTRL_STATE_MASK␉␉␉0x0003␉␉/* Current power state (D0 to D3) */␊ |
| 345 | #define PCI_PM_CTRL_PME_ENABLE␉␉␉0x0100␉␉/* PME pin enable */␊ |
| 346 | #define PCI_PM_CTRL_DATA_SEL_MASK␉␉0x1e00␉␉/* PM table data index */␊ |
| 347 | #define PCI_PM_CTRL_DATA_SCALE_MASK␉␉0x6000␉␉/* PM table data scaling factor */␊ |
| 348 | #define PCI_PM_CTRL_PME_STATUS␉␉␉0x8000␉␉/* PME pin status */␊ |
| 349 | #define PCI_PM_PPB_EXTENSIONS␉␉␉6␉␉␉/* PPB support extensions */␊ |
| 350 | #define PCI_PM_PPB_B2_B3␉␉␉␉0x40␉␉/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */␊ |
| 351 | #define PCI_PM_BPCC_ENABLE␉␉␉␉0x80␉␉/* Secondary bus is power managed */␊ |
| 352 | #define PCI_PM_DATA_REGISTER␉␉␉7␉␉␉/* PM table contents read here */␊ |
| 353 | #define PCI_PM_SIZEOF␉␉␉␉␉8␊ |
| 354 | ␊ |
| 355 | /* AGP registers */␊ |
| 356 | ␊ |
| 357 | #define PCI_AGP_VERSION␉␉␉␉␉2␉␉␉/* BCD version number */␊ |
| 358 | #define PCI_AGP_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
| 359 | #define PCI_AGP_STATUS␉␉␉␉␉4␉␉␉/* Status register */␊ |
| 360 | #define PCI_AGP_STATUS_RQ_MASK␉␉␉0xff000000␉/* Maximum number of requests - 1 */␊ |
| 361 | #define PCI_AGP_STATUS_ISOCH␉␉␉0x10000␉␉/* Isochronous transactions supported */␊ |
| 362 | #define PCI_AGP_STATUS_ARQSZ_MASK␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
| 363 | #define PCI_AGP_STATUS_CAL_MASK␉␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
| 364 | #define PCI_AGP_STATUS_SBA␉␉␉␉0x0200␉␉/* Sideband addressing supported */␊ |
| 365 | #define PCI_AGP_STATUS_ITA_COH␉␉␉0x0100␉␉/* In-aperture accesses always coherent */␊ |
| 366 | #define PCI_AGP_STATUS_GART64␉␉␉0x0080␉␉/* 64-bit GART entries supported */␊ |
| 367 | #define PCI_AGP_STATUS_HTRANS␉␉␉0x0040␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊ |
| 368 | #define PCI_AGP_STATUS_64BIT␉␉␉0x0020␉␉/* 64-bit addressing cycles supported */␊ |
| 369 | #define PCI_AGP_STATUS_FW␉␉␉␉0x0010␉␉/* Fast write transfers supported */␊ |
| 370 | #define PCI_AGP_STATUS_AGP3␉␉␉␉0x0008␉␉/* AGP3 mode supported */␊ |
| 371 | #define PCI_AGP_STATUS_RATE4␉␉␉0x0004␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊ |
| 372 | #define PCI_AGP_STATUS_RATE2␉␉␉0x0002␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊ |
| 373 | #define PCI_AGP_STATUS_RATE1␉␉␉0x0001␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊ |
| 374 | #define PCI_AGP_COMMAND␉␉␉␉␉8␉␉␉/* Control register */␊ |
| 375 | #define PCI_AGP_COMMAND_RQ_MASK␉␉␉0xff000000 /* Master: Maximum number of requests */␊ |
| 376 | #define PCI_AGP_COMMAND_ARQSZ_MASK␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
| 377 | #define PCI_AGP_COMMAND_CAL_MASK␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
| 378 | #define PCI_AGP_COMMAND_SBA␉␉␉␉0x0200␉␉/* Sideband addressing enabled */␊ |
| 379 | #define PCI_AGP_COMMAND_AGP␉␉␉␉0x0100␉␉/* Allow processing of AGP transactions */␊ |
| 380 | #define PCI_AGP_COMMAND_GART64␉␉␉0x0080␉␉/* 64-bit GART entries enabled */␊ |
| 381 | #define PCI_AGP_COMMAND_64BIT␉␉␉0x0020␉␉/* Allow generation of 64-bit addr cycles */␊ |
| 382 | #define PCI_AGP_COMMAND_FW␉␉␉␉0x0010␉␉/* Enable FW transfers */␊ |
| 383 | #define PCI_AGP_COMMAND_RATE4␉␉␉0x0004␉␉/* Use 4x rate (RFU in AGP3 mode) */␊ |
| 384 | #define PCI_AGP_COMMAND_RATE2␉␉␉0x0002␉␉/* Use 2x rate (8x in AGP3 mode) */␊ |
| 385 | #define PCI_AGP_COMMAND_RATE1␉␉␉0x0001␉␉/* Use 1x rate (4x in AGP3 mode) */␊ |
| 386 | #define PCI_AGP_SIZEOF␉␉␉␉␉12␊ |
| 387 | ␊ |
| 388 | /* Vital Product Data */␊ |
| 389 | ␊ |
| 390 | #define PCI_VPD_ADDR␉␉␉␉␉2␉␉␉/* Address to access (15 bits!) */␊ |
| 391 | #define PCI_VPD_ADDR_MASK␉␉␉␉0x7fff␉␉/* Address mask */␊ |
| 392 | #define PCI_VPD_ADDR_F␉␉␉␉␉0x8000␉␉/* Write 0, 1 indicates completion */␊ |
| 393 | #define PCI_VPD_DATA␉␉␉␉␉4␉␉␉/* 32-bits of data returned here */␊ |
| 394 | ␊ |
| 395 | /* Slot Identification */␊ |
| 396 | ␊ |
| 397 | #define PCI_SID_ESR␉␉␉␉␉␉2␉␉␉/* Expansion Slot Register */␊ |
| 398 | #define PCI_SID_ESR_NSLOTS␉␉␉␉0x1f␉␉/* Number of expansion slots available */␊ |
| 399 | #define PCI_SID_ESR_FIC␉␉␉␉␉0x20␉␉/* First In Chassis Flag */␊ |
| 400 | #define PCI_SID_CHASSIS_NR␉␉␉␉3␉␉␉/* Chassis Number */␊ |
| 401 | ␊ |
| 402 | /* Message Signaled Interrupts registers */␊ |
| 403 | ␊ |
| 404 | #define PCI_MSI_FLAGS␉␉␉␉␉2␉␉␉/* Various flags */␊ |
| 405 | #define PCI_MSI_FLAGS_MASK_BIT␉␉␉0x100␉␉/* interrupt masking & reporting supported */␊ |
| 406 | #define PCI_MSI_FLAGS_64BIT␉␉␉␉0x080␉␉/* 64-bit addresses allowed */␊ |
| 407 | #define PCI_MSI_FLAGS_QSIZE␉␉␉␉0x070␉␉/* Message queue size configured */␊ |
| 408 | #define PCI_MSI_FLAGS_QMASK␉␉␉␉0x00e␉␉/* Maximum queue size available */␊ |
| 409 | #define PCI_MSI_FLAGS_ENABLE␉␉␉0x001␉␉/* MSI feature enabled */␊ |
| 410 | #define PCI_MSI_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
| 411 | #define PCI_MSI_ADDRESS_LO␉␉␉␉4␉␉␉/* Lower 32 bits */␊ |
| 412 | #define PCI_MSI_ADDRESS_HI␉␉␉␉8␉␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊ |
| 413 | #define PCI_MSI_DATA_32␉␉␉␉␉8␉␉␉/* 16 bits of data for 32-bit devices */␊ |
| 414 | #define PCI_MSI_DATA_64␉␉␉␉␉12␉␉␉/* 16 bits of data for 64-bit devices */␊ |
| 415 | #define PCI_MSI_MASK_BIT_32␉␉␉␉12␉␉␉/* per-vector masking for 32-bit devices */␊ |
| 416 | #define PCI_MSI_MASK_BIT_64␉␉␉␉16␉␉␉/* per-vector masking for 64-bit devices */␊ |
| 417 | #define PCI_MSI_PENDING_32␉␉␉␉16␉␉␉/* per-vector interrupt pending for 32-bit devices */␊ |
| 418 | #define PCI_MSI_PENDING_64␉␉␉␉20␉␉␉/* per-vector interrupt pending for 64-bit devices */␊ |
| 419 | ␊ |
| 420 | /* PCI-X */␊ |
| 421 | #define PCI_PCIX_COMMAND 2 /* Command register offset */␊ |
| 422 | #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */␊ |
| 423 | #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */␊ |
| 424 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */␊ |
| 425 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070␊ |
| 426 | #define PCI_PCIX_COMMAND_RESERVED 0xf80␊ |
| 427 | #define PCI_PCIX_STATUS 4 /* Status register offset */␊ |
| 428 | #define PCI_PCIX_STATUS_FUNCTION 0x00000007␊ |
| 429 | #define PCI_PCIX_STATUS_DEVICE 0x000000f8␊ |
| 430 | #define PCI_PCIX_STATUS_BUS 0x0000ff00␊ |
| 431 | #define PCI_PCIX_STATUS_64BIT 0x00010000␊ |
| 432 | #define PCI_PCIX_STATUS_133MHZ 0x00020000␊ |
| 433 | #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */␊ |
| 434 | #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */␊ |
| 435 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */␊ |
| 436 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊ |
| 437 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000␊ |
| 438 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000␊ |
| 439 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */␊ |
| 440 | #define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉␉␉␉␉0x40000000 /* 266 MHz capable */␊ |
| 441 | #define PCI_PCIX_STATUS_533MHZ␉␉␉␉ 0x80000000 /* 533 MHz capable */␊ |
| 442 | #define PCI_PCIX_SIZEOF␉␉4␊ |
| 443 | ␊ |
| 444 | /* PCI-X Bridges */␊ |
| 445 | #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */␊ |
| 446 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001␊ |
| 447 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002␊ |
| 448 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */␊ |
| 449 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */␊ |
| 450 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */␊ |
| 451 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020␊ |
| 452 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0␊ |
| 453 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00␊ |
| 454 | #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */␊ |
| 455 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007␊ |
| 456 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8␊ |
| 457 | #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00␊ |
| 458 | #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000␊ |
| 459 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000␊ |
| 460 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */␊ |
| 461 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */␊ |
| 462 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */␊ |
| 463 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000␊ |
| 464 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000␊ |
| 465 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */␊ |
| 466 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */␊ |
| 467 | #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff␊ |
| 468 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000␊ |
| 469 | #define PCI_PCIX_BRIDGE_SIZEOF 12␊ |
| 470 | ␊ |
| 471 | /* PCI Express */␊ |
| 472 | #define PCI_EXP_FLAGS␉␉0x2␉/* Capabilities register */␊ |
| 473 | #define PCI_EXP_FLAGS_VERS␉0x000f␉/* Capability version */␊ |
| 474 | #define PCI_EXP_FLAGS_TYPE␉0x00f0␉/* Device/Port type */␊ |
| 475 | #define PCI_EXP_TYPE_ENDPOINT␉0x0␉/* Express Endpoint */␊ |
| 476 | #define PCI_EXP_TYPE_LEG_END␉0x1␉/* Legacy Endpoint */␊ |
| 477 | #define PCI_EXP_TYPE_ROOT_PORT 0x4␉/* Root Port */␊ |
| 478 | #define PCI_EXP_TYPE_UPSTREAM␉0x5␉/* Upstream Port */␊ |
| 479 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6␉/* Downstream Port */␊ |
| 480 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7␉/* PCI/PCI-X Bridge */␊ |
| 481 | #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8␉/* PCI/PCI-X to PCIE Bridge */␊ |
| 482 | #define PCI_EXP_TYPE_ROOT_INT_EP 0x9␉/* Root Complex Integrated Endpoint */␊ |
| 483 | #define PCI_EXP_TYPE_ROOT_EC 0xa␉/* Root Complex Event Collector */␊ |
| 484 | #define PCI_EXP_FLAGS_SLOT␉0x0100␉/* Slot implemented */␊ |
| 485 | #define PCI_EXP_FLAGS_IRQ␉0x3e00␉/* Interrupt message number */␊ |
| 486 | #define PCI_EXP_DEVCAP␉␉0x4␉/* Device capabilities */␊ |
| 487 | #define PCI_EXP_DEVCAP_PAYLOAD␉0x07␉/* Max_Payload_Size */␊ |
| 488 | #define PCI_EXP_DEVCAP_PHANTOM␉0x18␉/* Phantom functions */␊ |
| 489 | #define PCI_EXP_DEVCAP_EXT_TAG␉0x20␉/* Extended tags */␊ |
| 490 | #define PCI_EXP_DEVCAP_L0S␉0x1c0␉/* L0s Acceptable Latency */␊ |
| 491 | #define PCI_EXP_DEVCAP_L1␉0xe00␉/* L1 Acceptable Latency */␊ |
| 492 | #define PCI_EXP_DEVCAP_ATN_BUT␉0x1000␉/* Attention Button Present */␊ |
| 493 | #define PCI_EXP_DEVCAP_ATN_IND␉0x2000␉/* Attention Indicator Present */␊ |
| 494 | #define PCI_EXP_DEVCAP_PWR_IND␉0x4000␉/* Power Indicator Present */␊ |
| 495 | #define PCI_EXP_DEVCAP_RBE␉0x8000␉/* Role-Based Error Reporting */␊ |
| 496 | #define PCI_EXP_DEVCAP_PWR_VAL␉0x3fc0000 /* Slot Power Limit Value */␊ |
| 497 | #define PCI_EXP_DEVCAP_PWR_SCL␉0xc000000 /* Slot Power Limit Scale */␊ |
| 498 | #define PCI_EXP_DEVCAP_FLRESET␉0x10000000 /* Function-Level Reset */␊ |
| 499 | #define PCI_EXP_DEVCTL␉␉0x8␉/* Device Control */␊ |
| 500 | #define PCI_EXP_DEVCTL_CERE␉0x0001␉/* Correctable Error Reporting En. */␊ |
| 501 | #define PCI_EXP_DEVCTL_NFERE␉0x0002␉/* Non-Fatal Error Reporting Enable */␊ |
| 502 | #define PCI_EXP_DEVCTL_FERE␉0x0004␉/* Fatal Error Reporting Enable */␊ |
| 503 | #define PCI_EXP_DEVCTL_URRE␉0x0008␉/* Unsupported Request Reporting En. */␊ |
| 504 | #define PCI_EXP_DEVCTL_RELAXED␉0x0010␉/* Enable Relaxed Ordering */␊ |
| 505 | #define PCI_EXP_DEVCTL_PAYLOAD␉0x00e0␉/* Max_Payload_Size */␊ |
| 506 | #define PCI_EXP_DEVCTL_EXT_TAG␉0x0100␉/* Extended Tag Field Enable */␊ |
| 507 | #define PCI_EXP_DEVCTL_PHANTOM␉0x0200␉/* Phantom Functions Enable */␊ |
| 508 | #define PCI_EXP_DEVCTL_AUX_PME␉0x0400␉/* Auxiliary Power PM Enable */␊ |
| 509 | #define PCI_EXP_DEVCTL_NOSNOOP␉0x0800␉/* Enable No Snoop */␊ |
| 510 | #define PCI_EXP_DEVCTL_READRQ␉0x7000␉/* Max_Read_Request_Size */␊ |
| 511 | #define PCI_EXP_DEVCTL_BCRE␉0x8000␉/* Bridge Configuration Retry Enable */␊ |
| 512 | #define PCI_EXP_DEVCTL_FLRESET␉0x8000␉/* Function-Level Reset [bit shared with BCRE] */␊ |
| 513 | #define PCI_EXP_DEVSTA␉␉0xa␉/* Device Status */␊ |
| 514 | #define PCI_EXP_DEVSTA_CED␉0x01␉/* Correctable Error Detected */␊ |
| 515 | #define PCI_EXP_DEVSTA_NFED␉0x02␉/* Non-Fatal Error Detected */␊ |
| 516 | #define PCI_EXP_DEVSTA_FED␉0x04␉/* Fatal Error Detected */␊ |
| 517 | #define PCI_EXP_DEVSTA_URD␉0x08␉/* Unsupported Request Detected */␊ |
| 518 | #define PCI_EXP_DEVSTA_AUXPD␉0x10␉/* AUX Power Detected */␊ |
| 519 | #define PCI_EXP_DEVSTA_TRPND␉0x20␉/* Transactions Pending */␊ |
| 520 | #define PCI_EXP_LNKCAP␉␉0xc␉/* Link Capabilities */␊ |
| 521 | #define PCI_EXP_LNKCAP_SPEED␉0x0000f␉/* Maximum Link Speed */␊ |
| 522 | #define PCI_EXP_LNKCAP_WIDTH␉0x003f0␉/* Maximum Link Width */␊ |
| 523 | #define PCI_EXP_LNKCAP_ASPM␉0x00c00␉/* Active State Power Management */␊ |
| 524 | #define PCI_EXP_LNKCAP_L0S␉0x07000␉/* L0s Acceptable Latency */␊ |
| 525 | #define PCI_EXP_LNKCAP_L1␉0x38000␉/* L1 Acceptable Latency */␊ |
| 526 | #define PCI_EXP_LNKCAP_CLOCKPM␉0x40000␉/* Clock Power Management */␊ |
| 527 | #define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */␊ |
| 528 | #define PCI_EXP_LNKCAP_DLLA␉0x100000 /* Data Link Layer Active Reporting */␊ |
| 529 | #define PCI_EXP_LNKCAP_LBNC␉0x200000 /* Link Bandwidth Notification Capability */␊ |
| 530 | #define PCI_EXP_LNKCAP_PORT␉0xff000000 /* Port Number */␊ |
| 531 | #define PCI_EXP_LNKCTL␉␉0x10␉/* Link Control */␊ |
| 532 | #define PCI_EXP_LNKCTL_ASPM␉0x0003␉/* ASPM Control */␊ |
| 533 | #define PCI_EXP_LNKCTL_RCB␉0x0008␉/* Read Completion Boundary */␊ |
| 534 | #define PCI_EXP_LNKCTL_DISABLE␉0x0010␉/* Link Disable */␊ |
| 535 | #define PCI_EXP_LNKCTL_RETRAIN␉0x0020␉/* Retrain Link */␊ |
| 536 | #define PCI_EXP_LNKCTL_CLOCK␉0x0040␉/* Common Clock Configuration */␊ |
| 537 | #define PCI_EXP_LNKCTL_XSYNCH␉0x0080␉/* Extended Synch */␊ |
| 538 | #define PCI_EXP_LNKCTL_CLOCKPM␉0x0100␉/* Clock Power Management */␊ |
| 539 | #define PCI_EXP_LNKCTL_HWAUTWD␉0x0200␉/* Hardware Autonomous Width Disable */␊ |
| 540 | #define PCI_EXP_LNKCTL_BWMIE␉0x0400␉/* Bandwidth Mgmt Interrupt Enable */␊ |
| 541 | #define PCI_EXP_LNKCTL_AUTBWIE␉0x0800␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊ |
| 542 | #define PCI_EXP_LNKSTA␉␉0x12␉/* Link Status */␊ |
| 543 | #define PCI_EXP_LNKSTA_SPEED␉0x000f␉/* Negotiated Link Speed */␊ |
| 544 | #define PCI_EXP_LNKSTA_WIDTH␉0x03f0␉/* Negotiated Link Width */␊ |
| 545 | #define PCI_EXP_LNKSTA_TR_ERR␉0x0400␉/* Training Error (obsolete) */␊ |
| 546 | #define PCI_EXP_LNKSTA_TRAIN␉0x0800␉/* Link Training */␊ |
| 547 | #define PCI_EXP_LNKSTA_SL_CLK␉0x1000␉/* Slot Clock Configuration */␊ |
| 548 | #define PCI_EXP_LNKSTA_DL_ACT␉0x2000␉/* Data Link Layer in DL_Active State */␊ |
| 549 | #define PCI_EXP_LNKSTA_BWMGMT␉0x4000␉/* Bandwidth Mgmt Status */␊ |
| 550 | #define PCI_EXP_LNKSTA_AUTBW␉0x8000␉/* Autonomous Bandwidth Mgmt Status */␊ |
| 551 | #define PCI_EXP_SLTCAP␉␉0x14␉/* Slot Capabilities */␊ |
| 552 | #define PCI_EXP_SLTCAP_ATNB␉0x0001␉/* Attention Button Present */␊ |
| 553 | #define PCI_EXP_SLTCAP_PWRC␉0x0002␉/* Power Controller Present */␊ |
| 554 | #define PCI_EXP_SLTCAP_MRL␉0x0004␉/* MRL Sensor Present */␊ |
| 555 | #define PCI_EXP_SLTCAP_ATNI␉0x0008␉/* Attention Indicator Present */␊ |
| 556 | #define PCI_EXP_SLTCAP_PWRI␉0x0010␉/* Power Indicator Present */␊ |
| 557 | #define PCI_EXP_SLTCAP_HPS␉0x0020␉/* Hot-Plug Surprise */␊ |
| 558 | #define PCI_EXP_SLTCAP_HPC␉0x0040␉/* Hot-Plug Capable */␊ |
| 559 | #define PCI_EXP_SLTCAP_PWR_VAL␉0x00007f80 /* Slot Power Limit Value */␊ |
| 560 | #define PCI_EXP_SLTCAP_PWR_SCL␉0x00018000 /* Slot Power Limit Scale */␊ |
| 561 | #define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */␊ |
| 562 | #define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */␊ |
| 563 | #define PCI_EXP_SLTCAP_PSN␉0xfff80000 /* Physical Slot Number */␊ |
| 564 | #define PCI_EXP_SLTCTL␉␉0x18␉/* Slot Control */␊ |
| 565 | #define PCI_EXP_SLTCTL_ATNB␉0x0001␉/* Attention Button Pressed Enable */␊ |
| 566 | #define PCI_EXP_SLTCTL_PWRF␉0x0002␉/* Power Fault Detected Enable */␊ |
| 567 | #define PCI_EXP_SLTCTL_MRLS␉0x0004␉/* MRL Sensor Changed Enable */␊ |
| 568 | #define PCI_EXP_SLTCTL_PRSD␉0x0008␉/* Presence Detect Changed Enable */␊ |
| 569 | #define PCI_EXP_SLTCTL_CMDC␉0x0010␉/* Command Completed Interrupt Enable */␊ |
| 570 | #define PCI_EXP_SLTCTL_HPIE␉0x0020␉/* Hot-Plug Interrupt Enable */␊ |
| 571 | #define PCI_EXP_SLTCTL_ATNI␉0x00c0␉/* Attention Indicator Control */␊ |
| 572 | #define PCI_EXP_SLTCTL_PWRI␉0x0300␉/* Power Indicator Control */␊ |
| 573 | #define PCI_EXP_SLTCTL_PWRC␉0x0400␉/* Power Controller Control */␊ |
| 574 | #define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */␊ |
| 575 | #define PCI_EXP_SLTCTL_LLCHG␉0x1000␉/* Data Link Layer State Changed Enable */␊ |
| 576 | #define PCI_EXP_SLTSTA␉␉0x1a␉/* Slot Status */␊ |
| 577 | #define PCI_EXP_SLTSTA_ATNB␉0x0001␉/* Attention Button Pressed */␊ |
| 578 | #define PCI_EXP_SLTSTA_PWRF␉0x0002␉/* Power Fault Detected */␊ |
| 579 | #define PCI_EXP_SLTSTA_MRLS␉0x0004␉/* MRL Sensor Changed */␊ |
| 580 | #define PCI_EXP_SLTSTA_PRSD␉0x0008␉/* Presence Detect Changed */␊ |
| 581 | #define PCI_EXP_SLTSTA_CMDC␉0x0010␉/* Command Completed */␊ |
| 582 | #define PCI_EXP_SLTSTA_MRL_ST␉0x0020␉/* MRL Sensor State */␊ |
| 583 | #define PCI_EXP_SLTSTA_PRES␉0x0040␉/* Presence Detect State */␊ |
| 584 | #define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */␊ |
| 585 | #define PCI_EXP_SLTSTA_LLCHG␉0x0100␉/* Data Link Layer State Changed */␊ |
| 586 | #define PCI_EXP_RTCTL␉␉0x1c␉/* Root Control */␊ |
| 587 | #define PCI_EXP_RTCTL_SECEE␉0x0001␉/* System Error on Correctable Error */␊ |
| 588 | #define PCI_EXP_RTCTL_SENFEE␉0x0002␉/* System Error on Non-Fatal Error */␊ |
| 589 | #define PCI_EXP_RTCTL_SEFEE␉0x0004␉/* System Error on Fatal Error */␊ |
| 590 | #define PCI_EXP_RTCTL_PMEIE␉0x0008␉/* PME Interrupt Enable */␊ |
| 591 | #define PCI_EXP_RTCTL_CRSVIS␉0x0010␉/* Configuration Request Retry Status Visible to SW */␊ |
| 592 | #define PCI_EXP_RTCAP␉␉0x1e␉/* Root Capabilities */␊ |
| 593 | #define PCI_EXP_RTCAP_CRSVIS␉0x0010␉/* Configuration Request Retry Status Visible to SW */␊ |
| 594 | #define PCI_EXP_RTSTA␉␉0x20␉/* Root Status */␊ |
| 595 | #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */␊ |
| 596 | #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */␊ |
| 597 | #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */␊ |
| 598 | #define PCI_EXP_DEVCAP2␉␉␉0x24␉/* Device capabilities 2 */␊ |
| 599 | #define PCI_EXP_DEVCTL2␉␉␉0x28␉/* Device Control */␊ |
| 600 | #define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉((x) & 0xf) /* Completion Timeout Ranges Supported */␊ |
| 601 | #define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉((x) & 0xf) /* Completion Timeout Value */␊ |
| 602 | #define PCI_EXP_DEV2_TIMEOUT_DIS␉0x0010␉/* Completion Timeout Disable Supported */␊ |
| 603 | #define PCI_EXP_DEV2_ARI␉␉0x0020␉/* ARI Forwarding */␊ |
| 604 | #define PCI_EXP_DEVSTA2␉␉␉0x2a␉/* Device Status */␊ |
| 605 | #define PCI_EXP_LNKCAP2␉␉␉0x2c␉/* Link Capabilities */␊ |
| 606 | #define PCI_EXP_LNKCTL2␉␉␉0x30␉/* Link Control */␊ |
| 607 | #define PCI_EXP_LNKCTL2_SPEED(x)␉((x) & 0xf) /* Target Link Speed */␊ |
| 608 | #define PCI_EXP_LNKCTL2_CMPLNC␉␉0x0010␉/* Enter Compliance */␊ |
| 609 | #define PCI_EXP_LNKCTL2_SPEED_DIS␉0x0020␉/* Hardware Autonomous Speed Disable */␊ |
| 610 | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉(((x) >> 6) & 1) /* Selectable De-emphasis */␊ |
| 611 | #define PCI_EXP_LNKCTL2_MARGIN(x)␉(((x) >> 7) & 7) /* Transmit Margin */␊ |
| 612 | #define PCI_EXP_LNKCTL2_MOD_CMPLNC␉0x0400␉/* Enter Modified Compliance */␊ |
| 613 | #define PCI_EXP_LNKCTL2_CMPLNC_SOS␉0x0800␉/* Compliance SOS */␊ |
| 614 | #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */␊ |
| 615 | #define PCI_EXP_LNKSTA2␉␉␉0x32␉/* Link Status */␊ |
| 616 | #define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉((x) & 1)␉/* Current De-emphasis Level */␊ |
| 617 | #define PCI_EXP_SLTCAP2␉␉␉0x34␉/* Slot Capabilities */␊ |
| 618 | #define PCI_EXP_SLTCTL2␉␉␉0x38␉/* Slot Control */␊ |
| 619 | #define PCI_EXP_SLTSTA2␉␉␉0x3a␉/* Slot Status */␊ |
| 620 | ␊ |
| 621 | /* MSI-X */␊ |
| 622 | #define PCI_MSIX_ENABLE␉␉0x8000␊ |
| 623 | #define PCI_MSIX_MASK␉␉0x4000␊ |
| 624 | #define PCI_MSIX_TABSIZE␉0x03ff␊ |
| 625 | #define PCI_MSIX_TABLE␉␉4␊ |
| 626 | #define PCI_MSIX_PBA␉␉8␊ |
| 627 | #define PCI_MSIX_BIR␉␉0x7␊ |
| 628 | ␊ |
| 629 | /* Subsystem vendor/device ID for PCI bridges */␊ |
| 630 | #define PCI_SSVID_VENDOR␉4␊ |
| 631 | #define PCI_SSVID_DEVICE␉6␊ |
| 632 | ␊ |
| 633 | /* Advanced Error Reporting */␊ |
| 634 | #define PCI_ERR_UNCOR_STATUS␉4␉␉␉/* Uncorrectable Error Status */␊ |
| 635 | #define PCI_ERR_UNC_TRAIN␉␉0x00000001␉/* Undefined in PCIe rev1.1 & 2.0 spec */␊ |
| 636 | #define PCI_ERR_UNC_DLP␉␉␉0x00000010␉/* Data Link Protocol */␊ |
| 637 | #define PCI_ERR_UNC_SDES␉␉0x00000020␉/* Surprise Down Error */␊ |
| 638 | #define PCI_ERR_UNC_POISON_TLP␉0x00001000␉/* Poisoned TLP */␊ |
| 639 | #define PCI_ERR_UNC_FCP␉␉␉0x00002000␉/* Flow Control Protocol */␊ |
| 640 | #define PCI_ERR_UNC_COMP_TIME␉0x00004000␉/* Completion Timeout */␊ |
| 641 | #define PCI_ERR_UNC_COMP_ABORT␉0x00008000␉/* Completer Abort */␊ |
| 642 | #define PCI_ERR_UNC_UNX_COMP␉0x00010000␉/* Unexpected Completion */␊ |
| 643 | #define PCI_ERR_UNC_RX_OVER␉␉0x00020000␉/* Receiver Overflow */␊ |
| 644 | #define PCI_ERR_UNC_MALF_TLP␉0x00040000␉/* Malformed TLP */␊ |
| 645 | #define PCI_ERR_UNC_ECRC␉␉0x00080000␉/* ECRC Error Status */␊ |
| 646 | #define PCI_ERR_UNC_UNSUP␉␉0x00100000␉/* Unsupported Request */␊ |
| 647 | #define PCI_ERR_UNC_ACS_VIOL␉0x00200000␉/* ACS Violation */␊ |
| 648 | #define PCI_ERR_UNCOR_MASK␉␉8␉␉␉/* Uncorrectable Error Mask */␊ |
| 649 | /* Same bits as above */␊ |
| 650 | #define PCI_ERR_UNCOR_SEVER␉␉12␉␉␉/* Uncorrectable Error Severity */␊ |
| 651 | /* Same bits as above */␊ |
| 652 | #define PCI_ERR_COR_STATUS␉␉16␉␉␉/* Correctable Error Status */␊ |
| 653 | #define PCI_ERR_COR_RCVR␉␉0x00000001␉/* Receiver Error Status */␊ |
| 654 | #define PCI_ERR_COR_BAD_TLP␉␉0x00000040␉/* Bad TLP Status */␊ |
| 655 | #define PCI_ERR_COR_BAD_DLLP␉0x00000080␉/* Bad DLLP Status */␊ |
| 656 | #define PCI_ERR_COR_REP_ROLL␉0x00000100␉/* REPLAY_NUM Rollover */␊ |
| 657 | #define PCI_ERR_COR_REP_TIMER␉0x00001000␉/* Replay Timer Timeout */␊ |
| 658 | #define PCI_ERR_COR_REP_ANFE␉0x00002000␉/* Advisory Non-Fatal Error */␊ |
| 659 | #define PCI_ERR_COR_MASK␉␉20␉␉␉/* Correctable Error Mask */␊ |
| 660 | /* Same bits as above */␊ |
| 661 | #define PCI_ERR_CAP␉␉␉␉24␉␉␉/* Advanced Error Capabilities */␊ |
| 662 | #define PCI_ERR_CAP_FEP(x)␉␉((x) & 31)␉/* First Error Pointer */␊ |
| 663 | #define PCI_ERR_CAP_ECRC_GENC␉0x00000020␉/* ECRC Generation Capable */␊ |
| 664 | #define PCI_ERR_CAP_ECRC_GENE␉0x00000040␉/* ECRC Generation Enable */␊ |
| 665 | #define PCI_ERR_CAP_ECRC_CHKC␉0x00000080␉/* ECRC Check Capable */␊ |
| 666 | #define PCI_ERR_CAP_ECRC_CHKE␉0x00000100␉/* ECRC Check Enable */␊ |
| 667 | #define PCI_ERR_HEADER_LOG␉␉28␉/* Header Log Register (16 bytes) */␊ |
| 668 | #define PCI_ERR_ROOT_COMMAND␉44␉/* Root Error Command */␊ |
| 669 | #define PCI_ERR_ROOT_STATUS␉␉48␊ |
| 670 | #define PCI_ERR_ROOT_COR_SRC␉52␊ |
| 671 | #define PCI_ERR_ROOT_SRC␉␉54␊ |
| 672 | ␊ |
| 673 | /* Virtual Channel */␊ |
| 674 | #define PCI_VC_PORT_REG1␉4␊ |
| 675 | #define PCI_VC_PORT_REG2␉8␊ |
| 676 | #define PCI_VC_PORT_CTRL␉12␊ |
| 677 | #define PCI_VC_PORT_STATUS␉14␊ |
| 678 | #define PCI_VC_RES_CAP␉␉16␊ |
| 679 | #define PCI_VC_RES_CTRL␉␉20␊ |
| 680 | #define PCI_VC_RES_STATUS␉26␊ |
| 681 | ␊ |
| 682 | /* Power Budgeting */␊ |
| 683 | #define PCI_PWR_DSR␉␉4␉/* Data Select Register */␊ |
| 684 | #define PCI_PWR_DATA␉␉8␉/* Data Register */␊ |
| 685 | #define PCI_PWR_DATA_BASE(x)␉((x) & 0xff)␉ /* Base Power */␊ |
| 686 | #define PCI_PWR_DATA_SCALE(x)␉(((x) >> 8) & 3) /* Data Scale */␊ |
| 687 | #define PCI_PWR_DATA_PM_SUB(x)␉(((x) >> 10) & 7) /* PM Sub State */␊ |
| 688 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */␊ |
| 689 | #define PCI_PWR_DATA_TYPE(x)␉(((x) >> 15) & 7) /* Type */␊ |
| 690 | #define PCI_PWR_DATA_RAIL(x)␉(((x) >> 18) & 7) /* Power Rail */␊ |
| 691 | #define PCI_PWR_CAP␉␉12␉/* Capability */␊ |
| 692 | #define PCI_PWR_CAP_BUDGET(x)␉((x) & 1)␉/* Included in system budget */␊ |
| 693 | ␊ |
| 694 | /* Access Control Services */␊ |
| 695 | #define PCI_ACS_CAP␉␉␉␉0x04␉/* ACS Capability Register */␊ |
| 696 | #define PCI_ACS_CAP_VALID␉␉0x0001␉/* ACS Source Validation */␊ |
| 697 | #define PCI_ACS_CAP_BLOCK␉␉0x0002␉/* ACS Translation Blocking */␊ |
| 698 | #define PCI_ACS_CAP_REQ_RED␉␉0x0004␉/* ACS P2P Request Redirect */␊ |
| 699 | #define PCI_ACS_CAP_CMPLT_RED␉0x0008␉/* ACS P2P Completion Redirect */␊ |
| 700 | #define PCI_ACS_CAP_FORWARD␉␉0x0010␉/* ACS Upstream Forwarding */␊ |
| 701 | #define PCI_ACS_CAP_EGRESS␉␉0x0020␉/* ACS P2P Egress Control */␊ |
| 702 | #define PCI_ACS_CAP_TRANS␉␉0x0040␉/* ACS Direct Translated P2P */␊ |
| 703 | #define PCI_ACS_CAP_VECTOR(x)␉(((x) >> 8) & 0xff) /* Egress Control Vector Size */␊ |
| 704 | #define PCI_ACS_CTRL␉␉␉0x06␉/* ACS Control Register */␊ |
| 705 | #define PCI_ACS_CTRL_VALID␉␉0x0001␉/* ACS Source Validation Enable */␊ |
| 706 | #define PCI_ACS_CTRL_BLOCK␉␉0x0002␉/* ACS Translation Blocking Enable */␊ |
| 707 | #define PCI_ACS_CTRL_REQ_RED␉0x0004␉/* ACS P2P Request Redirect Enable */␊ |
| 708 | #define PCI_ACS_CTRL_CMPLT_RED␉0x0008␉/* ACS P2P Completion Redirect Enable */␊ |
| 709 | #define PCI_ACS_CTRL_FORWARD␉0x0010␉/* ACS Upstream Forwarding Enable */␊ |
| 710 | #define PCI_ACS_CTRL_EGRESS␉␉0x0020␉/* ACS P2P Egress Control Enable */␊ |
| 711 | #define PCI_ACS_CTRL_TRANS␉␉0x0040␉/* ACS Direct Translated P2P Enable */␊ |
| 712 | #define PCI_ACS_EGRESS_CTRL␉␉0x08␉/* Egress Control Vector */␊ |
| 713 | ␊ |
| 714 | /* Alternative Routing-ID Interpretation */␊ |
| 715 | #define PCI_ARI_CAP␉␉␉␉0x04␉/* ARI Capability Register */␊ |
| 716 | #define PCI_ARI_CAP_MFVC␉␉0x0001␉/* MFVC Function Groups Capability */␊ |
| 717 | #define PCI_ARI_CAP_ACS␉␉␉0x0002␉/* ACS Function Groups Capability */␊ |
| 718 | #define PCI_ARI_CAP_NFN(x)␉␉(((x) >> 8) & 0xff) /* Next Function Number */␊ |
| 719 | #define PCI_ARI_CTRL␉␉␉0x06␉/* ARI Control Register */␊ |
| 720 | #define PCI_ARI_CTRL_MFVC␉␉0x0001␉/* MFVC Function Groups Enable */␊ |
| 721 | #define PCI_ARI_CTRL_ACS␉␉0x0002␉/* ACS Function Groups Enable */␊ |
| 722 | #define PCI_ARI_CTRL_FG(x)␉(((x) >> 4) & 7) /* Function Group */␊ |
| 723 | ␊ |
| 724 | /* Address Translation Service */␊ |
| 725 | #define PCI_ATS_CAP␉␉␉␉0x04␉/* ATS Capability Register */␊ |
| 726 | #define PCI_ATS_CAP_IQD(x)␉((x) & 0x1f) /* Invalidate Queue Depth */␊ |
| 727 | #define PCI_ATS_CTRL␉␉␉0x06␉/* ATS Control Register */␊ |
| 728 | #define PCI_ATS_CTRL_STU(x)␉((x) & 0x1f) /* Smallest Translation Unit */␊ |
| 729 | #define PCI_ATS_CTRL_ENABLE␉0x8000␉/* ATS Enable */␊ |
| 730 | ␊ |
| 731 | /* Single Root I/O Virtualization */␊ |
| 732 | #define PCI_IOV_CAP␉␉0x04␉/* SR-IOV Capability Register */␊ |
| 733 | #define PCI_IOV_CAP_VFM␉0x00000001 /* VF Migration Capable */␊ |
| 734 | #define PCI_IOV_CAP_IMN(x)␉((x) >> 21) /* VF Migration Interrupt Message Number */␊ |
| 735 | #define PCI_IOV_CTRL␉␉0x08␉/* SR-IOV Control Register */␊ |
| 736 | #define PCI_IOV_CTRL_VFE␉0x0001␉/* VF Enable */␊ |
| 737 | #define PCI_IOV_CTRL_VFME␉0x0002␉/* VF Migration Enable */␊ |
| 738 | #define PCI_IOV_CTRL_VFMIE␉0x0004␉/* VF Migration Interrupt Enable */␊ |
| 739 | #define PCI_IOV_CTRL_MSE␉0x0008␉/* VF MSE */␊ |
| 740 | #define PCI_IOV_CTRL_ARI␉0x0010␉/* ARI Capable Hierarchy */␊ |
| 741 | #define PCI_IOV_STATUS␉␉0x0a␉/* SR-IOV Status Register */␊ |
| 742 | #define PCI_IOV_STATUS_MS␉0x0001␉/* VF Migration Status */␊ |
| 743 | #define PCI_IOV_INITIALVF␉0x0c␉/* Number of VFs that are initially associated */␊ |
| 744 | #define PCI_IOV_TOTALVF␉␉0x0e␉/* Maximum number of VFs that could be associated */␊ |
| 745 | #define PCI_IOV_NUMVF␉␉0x10␉/* Number of VFs that are available */␊ |
| 746 | #define PCI_IOV_FDL␉␉0x12␉/* Function Dependency Link */␊ |
| 747 | #define PCI_IOV_OFFSET␉␉0x14␉/* First VF Offset */␊ |
| 748 | #define PCI_IOV_STRIDE␉␉0x16␉/* Routing ID offset from one VF to the next one */␊ |
| 749 | #define PCI_IOV_DID␉␉0x1a␉/* VF Device ID */␊ |
| 750 | #define PCI_IOV_SUPPS␉␉0x1c␉/* Supported Page Sizes */␊ |
| 751 | #define PCI_IOV_SYSPS␉␉0x20␉/* System Page Size */␊ |
| 752 | #define PCI_IOV_BAR_BASE␉0x24␉/* VF BAR0, VF BAR1, ... VF BAR5 */␊ |
| 753 | #define PCI_IOV_NUM_BAR␉␉6␉/* Number of VF BARs */␊ |
| 754 | #define PCI_IOV_MSAO␉␉0x3c␉/* VF Migration State Array Offset */␊ |
| 755 | #define PCI_IOV_MSA_BIR(x)␉((x) & 7) /* VF Migration State BIR */␊ |
| 756 | #define PCI_IOV_MSA_OFFSET(x)␉((x) & 0xfffffff8) /* VF Migration State Offset */␊ |
| 757 | ␊ |
| 758 | /*␊ |
| 759 | * The PCI interface treats multi-function devices as independent␊ |
| 760 | * devices. The slot/function address of each device is encoded␊ |
| 761 | * in a single byte as follows:␊ |
| 762 | *␊ |
| 763 | *␉7:3 = slot␊ |
| 764 | *␉2:0 = function␊ |
| 765 | */␊ |
| 766 | #define PCI_DEVFN(slot,func)␉((((slot) & 0x1f) << 3) | ((func) & 0x07))␊ |
| 767 | #define PCI_SLOT(devfn)␉␉(((devfn) >> 3) & 0x1f)␊ |
| 768 | #define PCI_FUNC(devfn)␉␉((devfn) & 0x07)␊ |
| 769 | ␊ |
| 770 | /* Device classes and subclasses */␊ |
| 771 | ␊ |
| 772 | #define PCI_CLASS_NOT_DEFINED␉␉0x0000␊ |
| 773 | #define PCI_CLASS_NOT_DEFINED_VGA␉0x0001␊ |
| 774 | ␊ |
| 775 | #define PCI_BASE_CLASS_STORAGE␉␉0x01␊ |
| 776 | #define PCI_CLASS_STORAGE_SCSI␉␉0x0100␊ |
| 777 | #define PCI_CLASS_STORAGE_IDE␉␉0x0101␊ |
| 778 | #define PCI_CLASS_STORAGE_FLOPPY␉0x0102␊ |
| 779 | #define PCI_CLASS_STORAGE_IPI␉␉0x0103␊ |
| 780 | #define PCI_CLASS_STORAGE_RAID␉␉0x0104␊ |
| 781 | #define PCI_CLASS_STORAGE_ATA␉␉0x0105␊ |
| 782 | #define PCI_CLASS_STORAGE_SATA␉␉0x0106␊ |
| 783 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601␊ |
| 784 | #define PCI_CLASS_STORAGE_SAS␉␉0x0107␊ |
| 785 | #define PCI_CLASS_STORAGE_OTHER␉␉0x0180␊ |
| 786 | ␊ |
| 787 | #define PCI_BASE_CLASS_NETWORK␉␉0x02␊ |
| 788 | #define PCI_CLASS_NETWORK_ETHERNET␉0x0200␊ |
| 789 | #define PCI_CLASS_NETWORK_TOKEN_RING␉0x0201␊ |
| 790 | #define PCI_CLASS_NETWORK_FDDI␉␉0x0202␊ |
| 791 | #define PCI_CLASS_NETWORK_ATM␉␉0x0203␊ |
| 792 | #define PCI_CLASS_NETWORK_ISDN␉␉0x0204␊ |
| 793 | #define PCI_CLASS_NETWORK_OTHER␉␉0x0280␊ |
| 794 | ␊ |
| 795 | #define PCI_BASE_CLASS_DISPLAY␉␉0x03␊ |
| 796 | #define PCI_CLASS_DISPLAY_VGA␉␉0x0300␊ |
| 797 | #define PCI_CLASS_DISPLAY_XGA␉␉0x0301␊ |
| 798 | #define PCI_CLASS_DISPLAY_3D␉␉0x0302␊ |
| 799 | #define PCI_CLASS_DISPLAY_OTHER␉␉0x0380␊ |
| 800 | ␊ |
| 801 | #define PCI_BASE_CLASS_MULTIMEDIA␉0x04␊ |
| 802 | #define PCI_CLASS_MULTIMEDIA_VIDEO␉0x0400␊ |
| 803 | #define PCI_CLASS_MULTIMEDIA_AUDIO␉0x0401␊ |
| 804 | #define PCI_CLASS_MULTIMEDIA_PHONE␉0x0402␊ |
| 805 | #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV␉0x0403␊ |
| 806 | #define PCI_CLASS_MULTIMEDIA_OTHER␉0x0480␊ |
| 807 | ␊ |
| 808 | #define PCI_BASE_CLASS_MEMORY␉␉0x05␊ |
| 809 | #define PCI_CLASS_MEMORY_RAM␉␉0x0500␊ |
| 810 | #define PCI_CLASS_MEMORY_FLASH␉␉0x0501␊ |
| 811 | #define PCI_CLASS_MEMORY_OTHER␉␉0x0580␊ |
| 812 | ␊ |
| 813 | #define PCI_BASE_CLASS_BRIDGE␉␉0x06␊ |
| 814 | #define PCI_CLASS_BRIDGE_HOST␉␉0x0600␊ |
| 815 | #define PCI_CLASS_BRIDGE_ISA␉␉0x0601␊ |
| 816 | #define PCI_CLASS_BRIDGE_EISA␉␉0x0602␊ |
| 817 | #define PCI_CLASS_BRIDGE_MC␉␉␉0x0603␊ |
| 818 | #define PCI_CLASS_BRIDGE_PCI␉␉0x0604␊ |
| 819 | #define PCI_CLASS_BRIDGE_PCMCIA␉␉0x0605␊ |
| 820 | #define PCI_CLASS_BRIDGE_NUBUS␉␉0x0606␊ |
| 821 | #define PCI_CLASS_BRIDGE_CARDBUS␉0x0607␊ |
| 822 | #define PCI_CLASS_BRIDGE_RACEWAY␉0x0608␊ |
| 823 | #define PCI_CLASS_BRIDGE_PCI_SEMI␉0x0609␊ |
| 824 | #define PCI_CLASS_BRIDGE_IB_TO_PCI␉0x060a␊ |
| 825 | #define PCI_CLASS_BRIDGE_OTHER␉␉0x0680␊ |
| 826 | ␊ |
| 827 | #define PCI_BASE_CLASS_COMMUNICATION␉0x07␊ |
| 828 | #define PCI_CLASS_COMMUNICATION_SERIAL␉0x0700␊ |
| 829 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701␊ |
| 830 | #define PCI_CLASS_COMMUNICATION_MSERIAL␉0x0702␊ |
| 831 | #define PCI_CLASS_COMMUNICATION_MODEM␉0x0703␊ |
| 832 | #define PCI_CLASS_COMMUNICATION_OTHER␉0x0780␊ |
| 833 | ␊ |
| 834 | #define PCI_BASE_CLASS_SYSTEM␉␉0x08␊ |
| 835 | #define PCI_CLASS_SYSTEM_PIC␉␉0x0800␊ |
| 836 | #define PCI_CLASS_SYSTEM_DMA␉␉0x0801␊ |
| 837 | #define PCI_CLASS_SYSTEM_TIMER␉␉0x0802␊ |
| 838 | #define PCI_CLASS_SYSTEM_RTC␉␉0x0803␊ |
| 839 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG␉0x0804␊ |
| 840 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805␊ |
| 841 | #define PCI_CLASS_SYSTEM_OTHER␉␉␉0x0880␊ |
| 842 | ␊ |
| 843 | #define PCI_BASE_CLASS_INPUT␉␉␉0x09␊ |
| 844 | #define PCI_CLASS_INPUT_KEYBOARD␉␉0x0900␊ |
| 845 | #define PCI_CLASS_INPUT_PEN␉␉␉␉0x0901␊ |
| 846 | #define PCI_CLASS_INPUT_MOUSE␉␉␉0x0902␊ |
| 847 | #define PCI_CLASS_INPUT_SCANNER␉␉␉0x0903␊ |
| 848 | #define PCI_CLASS_INPUT_GAMEPORT␉␉0x0904␊ |
| 849 | #define PCI_CLASS_INPUT_OTHER␉␉␉0x0980␊ |
| 850 | ␊ |
| 851 | #define PCI_BASE_CLASS_DOCKING␉␉␉0x0a␊ |
| 852 | #define PCI_CLASS_DOCKING_GENERIC␉␉0x0a00␊ |
| 853 | #define PCI_CLASS_DOCKING_OTHER␉␉␉0x0a80␊ |
| 854 | ␊ |
| 855 | #define PCI_BASE_CLASS_PROCESSOR␉␉0x0b␊ |
| 856 | #define PCI_CLASS_PROCESSOR_386␉␉␉0x0b00␊ |
| 857 | #define PCI_CLASS_PROCESSOR_486␉␉␉0x0b01␊ |
| 858 | #define PCI_CLASS_PROCESSOR_PENTIUM␉␉0x0b02␊ |
| 859 | #define PCI_CLASS_PROCESSOR_ALPHA␉␉0x0b10␊ |
| 860 | #define PCI_CLASS_PROCESSOR_POWERPC␉␉0x0b20␊ |
| 861 | #define PCI_CLASS_PROCESSOR_MIPS␉␉0x0b30␊ |
| 862 | #define PCI_CLASS_PROCESSOR_CO␉␉␉0x0b40␊ |
| 863 | ␊ |
| 864 | #define PCI_BASE_CLASS_SERIAL␉␉␉0x0c␊ |
| 865 | #define PCI_CLASS_SERIAL_FIREWIRE␉␉0x0c00␊ |
| 866 | #define PCI_CLASS_SERIAL_ACCESS␉␉␉0x0c01␊ |
| 867 | #define PCI_CLASS_SERIAL_SSA␉␉␉0x0c02␊ |
| 868 | #define PCI_CLASS_SERIAL_USB␉␉␉0x0c03␊ |
| 869 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300␊ |
| 870 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310␊ |
| 871 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320␊ |
| 872 | #define PCI_CLASS_SERIAL_USB_XHCI 0x0c0330␊ |
| 873 | #define PCI_CLASS_SERIAL_FIBER␉␉␉0x0c04␊ |
| 874 | #define PCI_CLASS_SERIAL_SMBUS␉␉␉0x0c05␊ |
| 875 | #define PCI_CLASS_SERIAL_INFINIBAND␉␉0x0c06␊ |
| 876 | ␊ |
| 877 | #define PCI_BASE_CLASS_WIRELESS␉␉␉0x0d␊ |
| 878 | #define PCI_CLASS_WIRELESS_IRDA␉␉␉0x0d00␊ |
| 879 | #define PCI_CLASS_WIRELESS_CONSUMER_IR␉0x0d01␊ |
| 880 | #define PCI_CLASS_WIRELESS_RF␉␉␉0x0d10␊ |
| 881 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010␊ |
| 882 | #define PCI_CLASS_WIRELESS_OTHER␉␉0x0d80␊ |
| 883 | ␊ |
| 884 | #define PCI_BASE_CLASS_INTELLIGENT␉␉0x0e␊ |
| 885 | #define PCI_CLASS_INTELLIGENT_I2O␉␉0x0e00␊ |
| 886 | ␊ |
| 887 | #define PCI_BASE_CLASS_SATELLITE␉␉0x0f␊ |
| 888 | #define PCI_CLASS_SATELLITE_TV␉␉␉0x0f00␊ |
| 889 | #define PCI_CLASS_SATELLITE_AUDIO␉␉0x0f01␊ |
| 890 | #define PCI_CLASS_SATELLITE_VOICE␉␉0x0f03␊ |
| 891 | #define PCI_CLASS_SATELLITE_DATA␉␉0x0f04␊ |
| 892 | ␊ |
| 893 | #define PCI_BASE_CLASS_CRYPT␉␉␉0x10␊ |
| 894 | #define PCI_CLASS_CRYPT_NETWORK␉␉␉0x1000␊ |
| 895 | #define PCI_CLASS_CRYPT_ENTERTAINMENT␉0x1010␊ |
| 896 | #define PCI_CLASS_CRYPT_OTHER␉␉␉0x1080␊ |
| 897 | ␊ |
| 898 | #define PCI_BASE_CLASS_SIGNAL␉␉␉0x11␊ |
| 899 | #define PCI_CLASS_SIGNAL_DPIO␉␉␉0x1100␊ |
| 900 | #define PCI_CLASS_SIGNAL_PERF_CTR␉␉0x1101␊ |
| 901 | #define PCI_CLASS_SIGNAL_SYNCHRONIZER␉0x1110␊ |
| 902 | #define PCI_CLASS_SIGNAL_OTHER␉␉␉0x1180␊ |
| 903 | ␊ |
| 904 | #define PCI_CLASS_OTHERS␉␉␉␉0xff␊ |
| 905 | ␊ |
| 906 | /* Several ID's we need in the library */␊ |
| 907 | ␊ |
| 908 | #define PCI_VENDOR_ID_APPLE␉␉␉␉0x106b␊ |
| 909 | #define PCI_VENDOR_ID_AMD␉␉␉␉0x1022 ␊ |
| 910 | #define PCI_VENDOR_ID_ATI␉␉␉␉0x1002␊ |
| 911 | #define PCI_VENDOR_ID_INTEL␉␉␉␉0x8086␊ |
| 912 | #define PCI_VENDOR_ID_NVIDIA␉␉␉0x10de␊ |
| 913 | #define PCI_VENDOR_ID_REALTEK␉␉␉0x10ec␊ |
| 914 | #define PCI_VENDOR_ID_TEXAS_INSTRUMENTS␉0x104c␊ |
| 915 | #define PCI_VENDOR_ID_VIA␉␉␉␉0x1106␊ |
| 916 | ␊ |
| 917 | #endif /* !__LIBSAIO_PCI_H */␊ |
| 918 | |
