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Root/branches/ErmaC/Trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73␊
74unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
75{␊
76␉int l1, h1, l2, h2;␊
77␉unsigned long long t;␊
78␉␊
79␉outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
80␉outb(base + SMBHSTDAT, 0xff);␊
81␉␊
82␉rdtsc(l1, h1);␊
83␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
84␉{ ␊
85␉␉rdtsc(l2, h2);␊
86␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
87␉␉if (t > 5)␊
88␉␉␉return 0xFF; // break␊
89␉}␊
90␉␊
91␉outb(base + SMBHSTCMD, cmd);␊
92␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
93␉outb(base + SMBHSTCNT, 0x48 );␊
94␉␊
95␉rdtsc(l1, h1);␊
96␉␊
97␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
98␉{␉␊
99␉␉rdtsc(l2, h2);␊
100␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
101␉␉if (t > 5)␊
102␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
103 }␊
104 return inb(base + SMBHSTDAT);␊
105}␊
106␊
107/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
108#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
109␊
110int spd_indexes[] = {␊
111␉SPD_MEMORY_TYPE,␊
112␉SPD_DDR3_MEMORY_BANK,␊
113␉SPD_DDR3_MEMORY_CODE,␊
114␉SPD_NUM_ROWS,␊
115␉SPD_NUM_COLUMNS,␊
116␉SPD_NUM_DIMM_BANKS,␊
117␉SPD_NUM_BANKS_PER_SDRAM,␊
118␉4,7,8,9,12,64, /* TODO: give names to these values */␊
119␉95,96,97,98, 122,123,124,125 /* UIS */␊
120};␊
121#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
122␊
123/** Read from spd *used* values only*/␊
124static void init_spd(char * spd, uint32_t base, int slot)␊
125{␊
126␉int i;␊
127␉for (i=0; i< SPD_INDEXES_SIZE; i++)␊
128␉{␊
129␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
130␉}␊
131}␊
132␊
133/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
134 have different formats, always return a valid ptr.*/␊
135const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
136{␊
137 uint8_t bank = 0;␊
138 uint8_t code = 0;␊
139 int i = 0;␊
140 uint8_t * spd = (uint8_t *) slot->spd;␊
141␊
142 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
143 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
144 code = spd[SPD_DDR3_MEMORY_CODE];␊
145 for (i=0; i < VEN_MAP_SIZE; i++)␊
146 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
147 return vendorMap[i].name;␊
148 }␊
149 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
150 if(spd[64]==0x7f) {␊
151 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
152␉␉␉ bank++;␊
153␉␉␉ READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
154␉␉␉}␊
155␉␉␉READ_SPD(spd, base, slot_num,i);␊
156 code = spd[i];␊
157 } else {␊
158 code = spd[64]; ␊
159 bank = 0;␊
160 }␊
161 for (i=0; i < VEN_MAP_SIZE; i++)␊
162 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
163 return vendorMap[i].name;␊
164 }␊
165 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
166 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
167 return "Unifosa";␊
168 return "NoName";␊
169}␊
170␊
171/** Get Default Memory Module Speed (no overclocking handled) */␊
172int getDDRspeedMhz(const char * spd)␊
173{␊
174 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
175 switch(spd[12]) {␊
176 case 0x0f:␊
177 return 1066;␊
178 case 0x0c:␊
179 return 1333;␊
180 case 0x0a:␊
181 return 1600;␊
182 case 0x14:␊
183 default:␊
184 return 800;␊
185 }␊
186 } ␊
187 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
188 switch(spd[9]) {␊
189 case 0x50:␊
190 return 400;␊
191 case 0x3d:␊
192 return 533;␊
193 case 0x30:␊
194 return 667;␊
195 case 0x25:␊
196 default:␊
197 return 800;␊
198 }␊
199 }␊
200 return 800; // default freq for unknown types␊
201}␊
202␊
203#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
204#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
205␊
206/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
207const char *getDDRSerial(const char* spd)␊
208{␊
209␉static char asciiSerial[16];␊
210 ␊
211 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
212 {␊
213␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
214 }␊
215 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
216 { ␊
217␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
218 }␊
219␊
220␉return strdup(asciiSerial);␊
221}␊
222␊
223/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
224const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
225{␊
226␉static char asciiPartNo[32];␊
227␉int i, start=0, index = 0;␊
228␊
229 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
230␉␉start = 128;␊
231␉}␊
232 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
233␉␉start = 73;␊
234␉}␊
235␉␊
236␉// Check that the spd part name is zero terminated and that it is ascii:␊
237␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
238␉char c;␊
239␉for (i=start; i < start + sizeof(asciiPartNo); i++)␊
240␉{␊
241␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
242␉␉c = spd[i];␊
243␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
244␉␉␉asciiPartNo[index++] = c;␊
245␉␉else if (!isascii(c))␊
246␉␉␉break;␊
247␉}␊
248␉␊
249␉return strdup(asciiPartNo);␊
250}␊
251␊
252int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
253␊
254␊
255/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
256static void read_smb_intel(pci_dt_t *smbus_dev)␊
257{ ␊
258␉int i, speed;␊
259␉uint8_t spd_size, spd_type;␊
260␉uint32_t base, mmio, hostc;␊
261//␉bool dump = false;␊
262␉RamSlotInfo_t* slot;␊
263␊
264␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
265␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
266␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
267␊
268␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
269␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
270␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
271␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
272␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
273␊
274//Azi: no use for this!␊
275// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
276␉// needed at least for laptops␊
277␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
278␊
279␉char spdbuf[MAX_SPD_SIZE];␊
280␉// Search MAX_RAM_SLOTS slots␊
281␉for (i = 0; i < MAX_RAM_SLOTS; i++){␊
282␉␉slot = &Platform.RAM.DIMM[i];␊
283␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
284␉␉DBG("SPD[0] (size): 0x%02x @0x%x\n", spd_size, 0x50 + i);␊
285␉// Check spd is present␊
286␉if (spd_size && (spd_size != 0xff))␊
287␉{␊
288␊
289␉␉slot->spd = spdbuf;␊
290␉␉slot->InUse = true;␊
291␊
292␉␉bzero(slot->spd, spd_size);␊
293␊
294 // Copy spd data into buffer␊
295␊
296␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
297␉␉init_spd(slot->spd, base, i);␊
298␊
299␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
300␉␉{␊
301␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
302␊
303␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) * ␊
304␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
305␉␉␉break;␊
306␊
307␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
308␊
309␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
310␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
311␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
312␊
313␉␉␉break;␊
314␉␉}␊
315␊
316␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
317␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
318␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
319␉␉slot->Vendor = getVendorName(slot, base, i);␊
320␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
321␊
322␉␉// determine spd speed␊
323␉␉speed = getDDRspeedMhz(slot->spd);␊
324␉␉if (slot->Frequency<speed) slot->Frequency = speed;␊
325␉␉␉␊
326␉␉␉// pci memory controller if available, is more reliable␊
327␉␉␉if (Platform.RAM.Frequency > 0)␊
328␉␉␉{␊
329␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
330␉␉␉␉// now round off special cases␊
331␉␉␉␉uint32_t fmod100 = freq %100;␊
332␉␉␉␉switch(fmod100) {␊
333␉␉␉␉␉case 1:␉freq--;␉break;␊
334␉␉␉␉␉case 32:␉freq++;␉break;␊
335␉␉␉␉␉case 65:␉freq++; break;␊
336␉␉␉␉␉case 98:␉freq+=2;break;␊
337␉␉␉␉␉case 99:␉freq++; break;␊
338␉␉␉␉}␊
339␉␉␉␉slot->Frequency = freq;␊
340␉␉␉}␊
341␊
342␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
343 i, ␊
344 (int)slot->Type,␊
345 slot->ModuleSize, ␊
346 spd_memory_types[spd_type],␊
347 slot->Frequency,␊
348 slot->Vendor,␊
349 slot->PartNo,␊
350 slot->SerialNo); ␊
351␊
352␊
353␉␉}␊
354␊
355␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
356␉␉Platform.DMI.DIMM[i]= ␊
357 ␉i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ? ␊
358 ␉mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
359␉␉slot->spd = NULL;␊
360␊
361␉} // for␊
362}␊
363␊
364static struct smbus_controllers_t smbus_controllers[] = {␊
365␊
366␉{0x8086, 0x269B, "ESB2",␉␉read_smb_intel },␊
367␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊
368␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊
369␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊
370␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊
371␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊
372␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊
373␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␉␊
374␉{0x8086, 0x3A30, "ICH10R",␉␉read_smb_intel },␊
375␉{0x8086, 0x3A60, "ICH10B",␉␉read_smb_intel },␊
376␉{0x8086, 0x3B30, "5 Series",␉␉read_smb_intel },␊
377␉{0x8086, 0x1C22, "6 Series",␉␉read_smb_intel },␊
378␉{0x8086, 0x1E22, "7 Series",␉␉read_smb_intel },␊
379␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊
380␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel }␊
381␊
382};␊
383␊
384// initial call : pci_dt = root_pci_dev;␊
385// find_and_read_smbus_controller(root_pci_dev);␊
386bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
387{␊
388␉pci_dt_t␉*current = pci_dt;␊
389␉int i;␊
390␊
391␉while (current) {␊
392#if 0␊
393␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
394␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
395␉␉current->class_id, current->vendor_id, current->device_id, ␊
396␉␉get_pci_dev_path(current));␊
397#endif␊
398␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
399␉{␊
400␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
401␉␉{␊
402␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
403␉␉␉return true;␊
404␉␉␉}␊
405␉␉}␊
406␉␉find_and_read_smbus_controller(current->children);␊
407␉␉current = current->next;␊
408␉}␊
409 return false; // not found␊
410}␊
411␊
412void scan_spd(PlatformInfo_t *p)␊
413{␊
414␉find_and_read_smbus_controller(root_pci_dev);␊
415}␊
416␊
417

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