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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30 int␉␉attempts = 0;␊
31 uint64_t latchTime;␊
32 uint64_t␉saveTime,intermediate;␊
33 unsigned int timerValue, lastValue;␊
34 //boolean_t␉int_enabled;␊
35 /*␊
36 * Table of correction factors to account for␊
37 *␉ - timer counter quantization errors, and␊
38 *␉ - undercounts 0..5␊
39 */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45 uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52 };␊
53␊
54 //int_enabled = ml_set_interrupts_enabled(FALSE);␊
55␊
56restart:␊
57 if (attempts >= 9) // increase to up to 9 attempts.␊
58 // This will flash-reboot. TODO: Use tscPanic instead.␊
59 printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
60 attempts++;␊
61 enable_PIT2();␉␉// turn on PIT2␊
62 set_PIT2(0);␉␉// reset timer 2 to be zero␊
63 latchTime = rdtsc64();␉// get the time stamp to time ␊
64 latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
65 set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
66 saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
67 get_PIT2(&lastValue);␊
68 get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
69 do {␊
70␉␉intermediate = get_PIT2(&timerValue);␊
71␉␉if (timerValue > lastValue) {␊
72␉␉␉// Timer wrapped␊
73␉␉␉set_PIT2(0);␊
74␉␉␉disable_PIT2();␊
75␉␉␉goto restart;␊
76␉␉}␊
77␉␉lastValue = timerValue;␊
78 } while (timerValue > 5);␊
79 printf("timerValue␉ %d\n",timerValue);␊
80 printf("intermediate 0x%016llx\n",intermediate);␊
81 printf("saveTime␉ 0x%016llx\n",saveTime);␊
82 ␊
83 intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
84 intermediate *= scale[timerValue];␉// rescale measured time spent␊
85 intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
86 intermediate += latchTime;␉␉// add on our save fudge␊
87 ␊
88 set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
89 disable_PIT2();␉␉␉// turn off PIT 2␊
90␉␊
91 //ml_set_interrupts_enabled(int_enabled);␊
92 return intermediate;␊
93}␊
94␊
95/*␊
96 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
97 */␊
98static uint64_t measure_tsc_frequency(void)␊
99{␊
100␉uint64_t tscStart;␊
101␉uint64_t tscEnd;␊
102␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
103␉unsigned long pollCount;␊
104␉uint64_t retval = 0;␊
105␉int i;␊
106␉␊
107␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
108␉ * counter 2. We run this loop 3 times to make sure the cache␊
109␉ * is hot and we take the minimum delta from all of the runs.␊
110␉ * That is to say that we're biased towards measuring the minimum␊
111␉ * number of TSC ticks that occur while waiting for the timer to␊
112␉ * expire. That theoretically helps avoid inconsistencies when␊
113␉ * running under a VM if the TSC is not virtualized and the host␊
114␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
115␉ */␊
116␉for(i = 0; i < 10; ++i)␊
117␉{␊
118␉␉enable_PIT2();␊
119␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
120␉␉tscStart = rdtsc64();␊
121␉␉pollCount = poll_PIT2_gate();␊
122␉␉tscEnd = rdtsc64();␊
123␉␉/* The poll loop must have run at least a few times for accuracy */␊
124␉␉if (pollCount <= 1)␊
125␉␉␉continue;␊
126␉␉/* The TSC must increment at LEAST once every millisecond.␊
127␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
128␉␉ * be >= 30. Anything less and the processor is way too slow.␊
129␉␉ */␊
130␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
131␉␉␉continue;␊
132␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
133␉␉if ( (tscEnd - tscStart) < tscDelta )␊
134␉␉␉tscDelta = tscEnd - tscStart;␊
135␉}␊
136␉/* tscDelta is now the least number of TSC ticks the processor made in␊
137␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
138␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
139␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
140␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
141␉ * dividing by the milliseconds, we simply multiply by 1000.␊
142␉ */␊
143␊
144␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
145␉ * that we're going to multiply by 1000 first so we do need at least some␊
146␉ * arithmetic headroom. For now, 32-bit should be enough.␊
147␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
148␉ */␊
149␉if (tscDelta > (1ULL<<32))␊
150␉␉retval = 0;␊
151␉else␊
152␉{␊
153␉␉retval = tscDelta * 1000 / 30;␊
154␉}␊
155␉disable_PIT2();␊
156␉return retval;␊
157}␊
158␊
159/*␊
160 * Original comment/code:␊
161 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
162 *␊
163 * Measures the Actual Performance Frequency in Hz (64-bit)␊
164 * (just a naming change, mperf --> aperf )␊
165 */␊
166static uint64_t measure_aperf_frequency(void)␊
167{␊
168␉uint64_t aperfStart;␊
169␉uint64_t aperfEnd;␊
170␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
171␉unsigned long pollCount;␊
172␉uint64_t retval = 0;␊
173␉int i;␊
174␉␊
175␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
176␉ * counter 2. We run this loop 3 times to make sure the cache␊
177␉ * is hot and we take the minimum delta from all of the runs.␊
178␉ * That is to say that we're biased towards measuring the minimum␊
179␉ * number of APERF ticks that occur while waiting for the timer to␊
180␉ * expire.␊
181␉ */␊
182␉for(i = 0; i < 10; ++i)␊
183␉{␊
184␉␉enable_PIT2();␊
185␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
186␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
187␉␉pollCount = poll_PIT2_gate();␊
188␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
189␉␉/* The poll loop must have run at least a few times for accuracy */␊
190␉␉if (pollCount <= 1)␊
191␉␉␉continue;␊
192␉␉/* The TSC must increment at LEAST once every millisecond.␊
193␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
194␉␉ * be >= 30. Anything less and the processor is way too slow.␊
195␉␉ */␊
196␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
197␉␉␉continue;␊
198␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
199␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
200␉␉␉aperfDelta = aperfEnd - aperfStart;␊
201␉}␊
202␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
203␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
204␉ */␊
205␉␊
206␉if (aperfDelta > (1ULL<<32))␊
207␉␉retval = 0;␊
208␉else␊
209␉{␊
210␉␉retval = aperfDelta * 1000 / 30;␊
211␉}␊
212␉disable_PIT2();␊
213␉return retval;␊
214}␊
215␊
216/*␊
217 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
218 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
219 *␉ a max multi. (used to calculate the FSB freq.),␊
220 *␉ and a current multi. (used to calculate the CPU freq.)␊
221 * - fsbFrequency = tscFrequency / multi␊
222 * - cpuFrequency = fsbFrequency * multi␊
223 */␊
224void scan_cpu(PlatformInfo_t *p)␊
225{␊
226␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
227␉uint64_t␉msr, flex_ratio;␊
228␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
229␉const char␉*newratio;␊
230␉int␉␉len, myfsb;␊
231␉uint8_t␉␉bus_ratio_min;␊
232␉uint32_t␉max_ratio, min_ratio;␊
233␊
234␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
235␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
236␊
237␉/* get cpuid values */␊
238␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
239␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
240␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
241␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
242␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
243␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
244␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊
245␉{␊
246␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
247␉}␊
248␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊
249␉{␊
250␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
251␉}␊
252␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
253␉{␊
254␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
255␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
256␉}␊
257␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
258␉{␊
259␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
260␉}␊
261␊
262#if DEBUG_CPU␊
263␉{␊
264␉␉int␉␉i;␊
265␉␉printf("CPUID Raw Values:\n");␊
266␉␉for (i=0; i<CPUID_MAX; i++)␊
267␉␉{␊
268␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
269␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
270␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
271␉␉}␊
272␉}␊
273#endif␊
274␊
275␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
276␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
277␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
278␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
279␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
280␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
281␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
282␊
283␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
284␊
285␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
286␉␉p->CPU.Family == 0x06 &&␊
287␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
288␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
289␉␉)␊
290␉{␊
291␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
292␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊
293␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊
294␉}␊
295␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
296␉{␊
297␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
298␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
299␉}␊
300␉else␊
301␉{␊
302␉␉// Use previous method for Cores and Threads␊
303␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
304␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
305␉}␊
306␊
307␉/* get brand string (if supported) */␊
308␉/* Copyright: from Apple's XNU cpuid.c */␊
309␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
310␉␉uint32_t␉reg[4];␊
311␉␉char␉␉str[128], *s;␊
312␉␉/*␊
313␉␉ * The brand string 48 bytes (max), guaranteed to␊
314␉␉ * be NULL terminated.␊
315␉␉ */␊
316␉␉do_cpuid(0x80000002, reg);␊
317␉␉bcopy((char *)reg, &str[0], 16);␊
318␉␉do_cpuid(0x80000003, reg);␊
319␉␉bcopy((char *)reg, &str[16], 16);␊
320␉␉do_cpuid(0x80000004, reg);␊
321␉␉bcopy((char *)reg, &str[32], 16);␊
322␉␉for (s = str; *s != '\0'; s++) {␊
323␉␉␉if (*s != ' ') break;␊
324␉␉}␊
325␉␉␊
326␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
327␉␉␊
328␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
329␉␉␉/*␊
330␉␉␉ * This string means we have a firmware-programmable brand string,␊
331␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
332␉␉␉ */␊
333␉␉␉p->CPU.BrandString[0] = '\0';␊
334␉␉}␊
335␉}␊
336␉␊
337␉/* setup features */␊
338␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
339␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
340␉}␊
341␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
342␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
343␉}␊
344␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
345␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
346␉}␊
347␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
348␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
349␉}␊
350␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
351␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
352␉}␊
353␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
354␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
355␉}␊
356␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
357␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
358␉}␊
359␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
360␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
361␉}␊
362␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
363␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
364␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
365␉}␊
366␊
367␉tscFrequency = measure_tsc_frequency();␊
368␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
369␉/* if usual method failed */␊
370␉if ( tscFrequency < 1000 )//TEST␊
371␉{␊
372␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
373␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
374␉}␊
375␉else{␊
376␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
377␉}␊
378␉fsbFrequency = 0;␊
379␉cpuFrequency = 0;␊
380␊
381␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
382␉{␊
383␉␉int intelCPU = p->CPU.Model;␊
384␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
385␉␉{␊
386␉␉␉/* Nehalem CPU model */␊
387␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
388␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊
389␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊
390␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
391␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
392␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
393␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
394␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
395␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊
396␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉))␊
397␉␉␉{␊
398␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
399␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
400␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
401␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
402␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
403␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
404␉␉␉␉if (bitfield(msr, 16, 16)) {␊
405␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
406␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
407␉␉␉␉␉ where the cpu multipler can't be changed to␊
408␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
409␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
410␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
411␉␉␉␉␉ causing the system to crash since tscGranularity␊
412␉␉␉␉␉ is inadvertently set to 0.␊
413␉␉␉␉␉ */␊
414␉␉␉␉␉if (flex_ratio == 0) {␊
415␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
416␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
417␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
418␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
419␉␉␉␉␉} else {␊
420␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
421␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
422␉␉␉␉␉␉}␊
423␉␉␉␉␉}␊
424␉␉␉␉}␊
425␊
426␉␉␉␉if (bus_ratio_max)␊
427␉␉␉␉{␊
428␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
429␉␉␉␉}␊
430␉␉␉␉//valv: Turbo Ratio Limit␊
431␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
432␉␉␉␉{␊
433␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
434␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
435␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
436␉␉␉␉} else {␊
437␉␉␉␉␉cpuFrequency = tscFrequency;␊
438␉␉␉␉}␊
439␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
440␉␉␉␉{␊
441␉␉␉␉␉max_ratio = atoi(newratio);␊
442␉␉␉␉␉max_ratio = (max_ratio * 10);␊
443␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
444␊
445␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
446␊
447␉␉␉␉␉// extreme overclockers may love 320 ;)␊
448␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
449␉␉␉␉␉{␊
450␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
451␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
452␉␉␉␉␉␉else maxdiv = 0;␊
453␉␉␉␉␉} else {␊
454␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
455␉␉␉␉␉}␊
456␉␉␉␉}␊
457␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
458␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
459␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
460␉␉␉␉p->CPU.MinRatio = min_ratio;␊
461␊
462␉␉␉␉myfsb = fsbFrequency / 1000000;␊
463␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
464␉␉␉␉currcoef = bus_ratio_max;␊
465␉␉␉} else {␊
466␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
467␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
468␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
469␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
470␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
471␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
472␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
473␊
474␉␉␉␉// This will always be model >= 3␊
475␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
476␉␉␉␉{␊
477␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
478␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
479␉␉␉␉} else {␊
480␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
481␉␉␉␉␉/* XXX */␊
482␉␉␉␉␉maxcoef = currcoef;␊
483␉␉␉␉}␊
484␊
485␉␉␉␉if (maxcoef)␊
486␉␉␉␉{␊
487␉␉␉␉␉if (maxdiv)␊
488␉␉␉␉␉{␊
489␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
490␉␉␉␉␉} else {␊
491␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
492␉␉␉␉␉}␊
493␉␉␉␉␉if (currdiv)␊
494␉␉␉␉␉{␊
495␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
496␉␉␉␉␉} else {␊
497␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
498␉␉␉␉␉}␊
499␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
500␉␉␉␉}␊
501␉␉␉}␊
502␉␉}␊
503␉␉/* Mobile CPU */␊
504␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
505␉␉{␊
506␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
507␉␉}␊
508␉}␊
509␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
510␉{␊
511␉␉switch(p->CPU.ExtFamily)␊
512␉␉{␊
513␉␉␉case 0x00: /* K8 */␊
514␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
515␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
516␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
517␉␉␉␉break;␊
518␊
519␉␉␉case 0x01: /* K10 */␊
520␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
521␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
522␉␉␉␉// EffFreq: effective frequency interface␊
523␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
524␉␉␉␉{␊
525␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
526␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
527␉␉␉␉␉cpuFrequency = aperf;␊
528␉␉␉␉}␊
529␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
530␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
531␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
532␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
533␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
534␊
535␉␉␉␉break;␊
536␊
537␉␉␉case 0x05: /* K14 */␊
538␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
539␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
540␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
541␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
542␊
543␉␉␉␉break;␊
544␊
545␉␉␉case 0x02: /* K11 */␊
546␉␉␉␉// not implimented␊
547␉␉␉␉break;␊
548␉␉}␊
549␊
550␉␉if (maxcoef)␊
551␉␉{␊
552␉␉␉if (currdiv)␊
553␉␉␉{␊
554␉␉␉␉if (!currcoef) currcoef = maxcoef;␊
555␉␉␉␉if (!cpuFrequency)␊
556␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
557␉␉␉␉else␊
558␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
559␊
560␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
561␉␉␉} else {␊
562␉␉␉␉if (!cpuFrequency)␊
563␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
564␉␉␉␉else ␊
565␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
566␉␉␉␉DBG("%d\n", currcoef);␊
567␉␉␉}␊
568␉␉}␊
569␉␉else if (currcoef)␊
570␉␉{␊
571␉␉␉if (currdiv)␊
572␉␉␉{␊
573␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
574␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
575␉␉␉} else {␊
576␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
577␉␉␉␉DBG("%d\n", currcoef);␊
578␉␉␉}␊
579␉␉}␊
580␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
581␉}␊
582␉␊
583#if 0␊
584␉if (!fsbFrequency)␊
585␉{␊
586␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
587␉␉cpuFrequency = tscFrequency;␊
588␉␉DBG("0 ! using the default value for FSB !\n");␊
589␉}␊
590␊
591␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
592␊
593#endif␊
594␊
595␉p->CPU.MaxCoef = maxcoef;␊
596␉p->CPU.MaxDiv = maxdiv;␊
597␉p->CPU.CurrCoef = currcoef;␊
598␉p->CPU.CurrDiv = currdiv;␊
599␉p->CPU.TSCFrequency = tscFrequency;␊
600␉p->CPU.FSBFrequency = fsbFrequency;␊
601␉p->CPU.CPUFrequency = cpuFrequency;␊
602␊
603␉// keep formatted with spaces instead of tabs␊
604␉DBG("\n---------------------------------------------\n");␊
605␉DBG("CPU: Brand String:\t\t\t\t %s\n", p->CPU.BrandString);␊
606␉DBG("CPU: Vendor/Family/ExtFamily:\t 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
607␉DBG("CPU: Model/ExtModel/Stepping:\t 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
608␉DBG("CPU: MaxCoef/CurrCoef:\t\t\t 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
609␉DBG("CPU: MaxDiv/CurrDiv:\t\t\t 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
610␉DBG("CPU: TSCFreq:\t\t\t\t %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
611␉DBG("CPU: FSBFreq:\t\t\t\t\t %dMHz\n", (p->CPU.FSBFrequency + 500000) / 1000000);␊
612␉DBG("CPU: CPUFreq:\t\t\t\t %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
613␉DBG("CPU: Number of CPU Cores:\t\t %d\n", p->CPU.NoCores);␊
614␉DBG("CPU: Number of CPU Threads:\t %d\n", p->CPU.NoThreads);␊
615␉DBG("CPU: Features:\t\t\t\t\t 0x%08x\n", p->CPU.Features);␊
616␉DBG("---------------------------------------------\n");␊
617#if DEBUG_CPU␊
618␉pause();␊
619#endif␊
620}␊
621

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