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Root/branches/ErmaC/Trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72int spd_indexes[] = {␊
73␉SPD_MEMORY_TYPE,␊
74␉SPD_DDR3_MEMORY_BANK,␊
75␉SPD_DDR3_MEMORY_CODE,␊
76␉SPD_NUM_ROWS,␊
77␉SPD_NUM_COLUMNS,␊
78␉SPD_NUM_DIMM_BANKS,␊
79␉SPD_NUM_BANKS_PER_SDRAM,␊
80␉4,7,8,9,12,64, /* TODO: give names to these values */␊
81␉95,96,97,98, 122,123,124,125 /* UIS */␊
82};␊
83#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
84␊
85/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
86␊
87unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
88{␊
89␉int l1, h1, l2, h2;␊
90␉unsigned long long t;␊
91␉␊
92␉outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
93␉outb(base + SMBHSTDAT, 0xff);␊
94␉␊
95␉rdtsc(l1, h1);␊
96␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
97␉{ ␊
98␉␉rdtsc(l2, h2);␊
99␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
100␉␉if (t > 5)␊
101␉␉␉return 0xFF; // break␊
102␉}␊
103␉␊
104␉outb(base + SMBHSTCMD, cmd);␊
105␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
106␉outb(base + SMBHSTCNT, 0x48 );␊
107␉␊
108␉rdtsc(l1, h1);␊
109␉␊
110␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
111␉{␉␊
112␉␉rdtsc(l2, h2);␊
113␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
114␉␉if (t > 5)␊
115␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
116 }␊
117 return inb(base + SMBHSTDAT);␊
118}␊
119␊
120/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
121#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
122␊
123␊
124/** Read from spd *used* values only*/␊
125static void init_spd(char * spd, uint32_t base, int slot)␊
126{␊
127␉int i;␊
128␉for (i=0; i< SPD_INDEXES_SIZE; i++)␊
129␉{␊
130␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
131␉}␊
132}␊
133␊
134/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
135 have different formats, always return a valid ptr.*/␊
136const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
137{␊
138␉uint8_t bank = 0;␊
139␉uint8_t code = 0;␊
140␉int i = 0;␊
141␉uint8_t * spd = (uint8_t *) slot->spd;␊
142␊
143␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
144␉{ // DDR3␊
145␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
146␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
147␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
148␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
149␉␉␉␉return vendorMap[i].name;␊
150␉}␊
151␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
152␉{␊
153␉␉if(spd[64]==0x7f)␊
154␉␉{␊
155␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
156␉␉␉{␊
157␉␉␉␉bank++;␊
158␉␉␉␉READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
159␉␉␉}␊
160␉␉␉READ_SPD(spd, base, slot_num,i);␊
161␉␉␉code = spd[i];␊
162␉␉}␊
163␉␉else␊
164␉␉{␊
165␉␉␉code = spd[64]; ␊
166␉␉␉bank = 0;␊
167␉␉}␊
168␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
169␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
170␉␉␉␉return vendorMap[i].name;␊
171␉}␊
172 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
173 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
174 return "Unifosa";␊
175 return "NoName";␊
176}␊
177␊
178/** Get Default Memory Module Speed (no overclocking handled) */␊
179int getDDRspeedMhz(const char * spd)␊
180{␊
181␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
182␉{ ␊
183␉␉switch(spd[12])␊
184␉␉{␊
185␉␉␉case 0x0f:␊
186␉␉␉␉return 1066;␊
187␉␉␉case 0x0c:␊
188␉␉␉␉return 1333;␊
189␉␉␉case 0x0a:␊
190␉␉␉␉return 1600;␊
191␉␉␉case 0x14:␊
192␉␉␉default:␊
193␉␉␉␉return 800;␊
194␉␉}␊
195␉} ␊
196␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
197␉{␊
198␉␉switch(spd[9])␊
199␉␉{␊
200␉␉␉case 0x50:␊
201␉␉␉␉return 400;␊
202␉␉␉case 0x3d:␊
203␉␉␉␉return 533;␊
204␉␉␉case 0x30:␊
205␉␉␉␉return 667;␊
206␉␉␉case 0x25:␊
207␉␉␉default:␊
208␉␉␉␉return 800;␊
209␉␉}␊
210␉}␊
211␉return 800; // default freq for unknown types␊
212}␊
213␊
214#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
215#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
216␊
217/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
218const char *getDDRSerial(const char* spd)␊
219{␊
220␉static char asciiSerial[16];␊
221 ␊
222␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
223␉{␊
224␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
225␉}␊
226␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
227␉{␊
228␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
229␉}␊
230␊
231␉return strdup(asciiSerial);␊
232}␊
233␊
234/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
235const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
236{␊
237␉static char asciiPartNo[32];␊
238␉int i, start=0, index = 0;␊
239␊
240␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
241␉{␊
242␉␉start = 128;␊
243␉}␊
244␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
245␉{␊
246␉␉start = 73;␊
247␉}␊
248␉␊
249␉// Check that the spd part name is zero terminated and that it is ascii:␊
250␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
251␉char c;␊
252␉for (i=start; i < start + sizeof(asciiPartNo); i++)␊
253␉{␊
254␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
255␉␉c = spd[i];␊
256␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
257␉␉␉asciiPartNo[index++] = c;␊
258␉␉else if (!isascii(c))␊
259␉␉␉break;␊
260␉}␊
261␉␊
262␉return strdup(asciiPartNo);␊
263}␊
264␊
265int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
266␊
267␊
268/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
269static void read_smb_intel(pci_dt_t *smbus_dev)␊
270{ ␊
271␉int i, speed;␊
272␉uint8_t spd_size, spd_type;␊
273␉uint32_t base, mmio, hostc;␊
274//␉bool dump = false;␊
275␉RamSlotInfo_t* slot;␊
276␊
277␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
278␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
279␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
280␊
281␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
282␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
283␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
284␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
285␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
286␊
287//Azi: no use for this!␊
288// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
289␉// needed at least for laptops␊
290␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
291␊
292␉char spdbuf[MAX_SPD_SIZE];␊
293␉// Search MAX_RAM_SLOTS slots␊
294␉for (i = 0; i < MAX_RAM_SLOTS; i++){␊
295␉␉slot = &Platform.RAM.DIMM[i];␊
296␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
297␉␉DBG("SPD[0] (size): 0x%02x @0x%x\n", spd_size, 0x50 + i);␊
298␉// Check spd is present␊
299␉if (spd_size && (spd_size != 0xff))␊
300␉{␊
301␊
302␉␉slot->spd = spdbuf;␊
303␉␉slot->InUse = true;␊
304␊
305␉␉bzero(slot->spd, spd_size);␊
306␊
307␉␉// Copy spd data into buffer␊
308␊
309␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
310␉␉init_spd(slot->spd, base, i);␊
311␊
312␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
313␉␉{␊
314␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
315␊
316␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) * ␊
317␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
318␉␉␉break;␊
319␊
320␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
321␊
322␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
323␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
324␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
325␊
326␉␉␉break;␊
327␉␉}␊
328␊
329␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
330␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
331␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
332␉␉slot->Vendor = getVendorName(slot, base, i);␊
333␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
334␊
335␉␉// determine spd speed␊
336␉␉speed = getDDRspeedMhz(slot->spd);␊
337␉␉if (slot->Frequency<speed) slot->Frequency = speed;␊
338␉␉␉␊
339␉␉␉// pci memory controller if available, is more reliable␊
340␉␉␉if (Platform.RAM.Frequency > 0)␊
341␉␉␉{␊
342␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
343␉␉␉␉// now round off special cases␊
344␉␉␉␉uint32_t fmod100 = freq %100;␊
345␉␉␉␉switch(fmod100) {␊
346␉␉␉␉␉case 1:␉freq--;␉break;␊
347␉␉␉␉␉case 32:␉freq++;␉break;␊
348␉␉␉␉␉case 65:␉freq++; break;␊
349␉␉␉␉␉case 98:␉freq+=2;break;␊
350␉␉␉␉␉case 99:␉freq++; break;␊
351␉␉␉␉}␊
352␉␉␉␉slot->Frequency = freq;␊
353␉␉␉}␊
354␊
355␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
356 i, ␊
357 (int)slot->Type,␊
358 slot->ModuleSize, ␊
359 spd_memory_types[spd_type],␊
360 slot->Frequency,␊
361 slot->Vendor,␊
362 slot->PartNo,␊
363 slot->SerialNo); ␊
364␊
365␊
366␉␉}␊
367␊
368␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
369␉␉Platform.DMI.DIMM[i]= ␊
370 ␉i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ? ␊
371 ␉mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
372␉␉slot->spd = NULL;␊
373␊
374␉} // for␊
375}␊
376␊
377static struct smbus_controllers_t smbus_controllers[] = {␊
378␊
379␉{0x8086, 0x269B, "ESB2",␉␉read_smb_intel },␊
380␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊
381␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊
382␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊
383␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊
384␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊
385␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊
386␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␉␊
387␉{0x8086, 0x3A30, "ICH10R",␉␉read_smb_intel },␊
388␉{0x8086, 0x3A60, "ICH10B",␉␉read_smb_intel },␊
389␉{0x8086, 0x3B30, "5 Series",␉␉read_smb_intel },␊
390␉{0x8086, 0x1C22, "6 Series",␉␉read_smb_intel },␊
391␉{0x8086, 0x1E22, "7 Series",␉␉read_smb_intel },␊
392␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊
393␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel }␊
394␊
395};␊
396␊
397// initial call : pci_dt = root_pci_dev;␊
398// find_and_read_smbus_controller(root_pci_dev);␊
399bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
400{␊
401␉pci_dt_t␉*current = pci_dt;␊
402␉int i;␊
403␊
404␉while (current)␊
405␉{␊
406#if 0␊
407␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
408␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
409␉␉current->class_id, current->vendor_id, current->device_id, ␊
410␉␉get_pci_dev_path(current));␊
411#endif␊
412␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
413␉␉{␊
414␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
415␉␉␉{␊
416␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
417␉␉␉␉return true;␊
418␉␉␉}␊
419␉␉}␊
420␉␉find_and_read_smbus_controller(current->children);␊
421␉␉current = current->next;␊
422␉}␊
423␉return false; // not found␊
424}␊
425␊
426void scan_spd(PlatformInfo_t *p)␊
427{␊
428␉find_and_read_smbus_controller(root_pci_dev);␊
429}␊
430␊
431

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