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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉␉value->word = 0;␊
37␉␉␉␉␉␉break;␊
38␉␉␉␉␉default:␊
39␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
40␉␉␉␉}␊
41␉␉␉}␊
42␉␉␉␉break;␊
43␊
44␉␉␉default:␊
45␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
46␉␉}␊
47␉}␊
48␉else␊
49␉{␊
50␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
51␉}␊
52␊
53␉return true;␊
54}␊
55␊
56bool getProcessorInformationMaximumClock(returnType *value)␊
57{␊
58␉value->word = Platform.CPU.CPUFrequency/1000000;␊
59␉return true;␊
60}␊
61␊
62bool getSMBOemProcessorBusSpeed(returnType *value)␊
63{␊
64␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
65␉{␉␉␊
66␉␉switch (Platform.CPU.Family) ␊
67␉␉{␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model)␊
71␉␉␉␉{␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
80␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_DALES:␊
82␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
83␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
84␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
86␉␉␉␉␉{␊
87␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
88␉␉␉␉␉␉int nhm_bus = 0x3F;␊
89␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
90␉␉␉␉␉␉unsigned long did, vid;␊
91␉␉␉␉␉␉int i;␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉// Nehalem supports Scrubbing␊
94␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
95␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
96␉␉␉␉␉␉{␊
97␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
98␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
99␉␉␉␉␉␉␉vid &= 0xFFFF;␊
100␉␉␉␉␉␉␉did &= 0xFF00;␊
101␉␉␉␉␉␉␉␊
102␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
103␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
104␉␉␉␉␉␉}␊
105␉␉␉␉␉␉␊
106␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
107␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
108␉␉␉␉␉␉qpimult &= 0x7F;␊
109␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
110␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
111␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
112␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
113␉␉␉␉␉␉{␊
114␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
115␉␉␉␉␉␉}␊
116␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
117␉␉␉␉␉␉value->word = qpibusspeed;␊
118␉␉␉␉␉␉return true;␊
119␉␉␉␉␉}␊
120␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
121␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
122␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
123␉␉␉␉␉{␊
124␉␉␉␉␉␉int busspeed;␊
125␉␉␉␉␉␉busspeed = 100;␊
126␉␉␉␉␉␉value->word = busspeed;␊
127␉␉␉␉␉␉return true;␊
128␉␉␉␉␉}␊
129␉␉␉␉}␊
130␉␉␉}␊
131␉␉}␊
132␉}␊
133␉return false;␊
134}␊
135␊
136uint16_t simpleGetSMBOemProcessorType(void)␊
137{␊
138␉if (Platform.CPU.NoCores >= 4) ␊
139␉{␊
140␉␉return 0x0501;␉// Quad-Core Xeon␊
141␉}␊
142␉else if (Platform.CPU.NoCores == 1) ␊
143␉{␊
144␉␉return 0x0201;␉// Core Solo␊
145␉};␊
146␉␊
147␉return 0x0301;␉␉// Core 2 Duo␊
148}␊
149␊
150bool getSMBOemProcessorType(returnType *value)␊
151{␊
152␉static bool done = false;␉␉␊
153␊
154␉value->word = simpleGetSMBOemProcessorType();␊
155␊
156␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
157␉{␊
158␉␉if (!done)␊
159␉␉{␊
160␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
161␉␉␉done = true;␊
162␉␉}␊
163␊
164␉␉switch (Platform.CPU.Family) ␊
165␉␉{␊
166␉␉␉case 0x06:␊
167␉␉␉{␊
168␉␉␉␉switch (Platform.CPU.Model)␊
169␉␉␉␉{␊
170␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
171␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
172␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
173␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
174␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
175␉␉␉␉␉␉return true;␊
176␊
177␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
178␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
179␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
180␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
181␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
182␉␉␉␉␉␉{␊
183␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
184␉␉␉␉␉␉}␊
185␉␉␉␉␉␉else␊
186␉␉␉␉␉␉{␊
187␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
188␉␉␉␉␉␉}␊
189␉␉␉␉␉␉return true;␊
190␊
191␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
192␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
193␉␉␉␉␉␉{␊
194␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
195␉␉␉␉␉␉}␊
196␉␉␉␉␉␉else␊
197␉␉␉␉␉␉{␊
198␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
199␉␉␉␉␉␉␉{␊
200␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
201␉␉␉␉␉␉␉}␊
202␉␉␉␉␉␉␉else␊
203␉␉␉␉␉␉␉{␊
204␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
205␉␉␉␉␉␉␉}␊
206␉␉␉␉␉␉}␊
207␉␉␉␉␉␉return true;␊
208␊
209␉␉␉␉␉case CPU_MODEL_DALES:␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
211␉␉␉␉␉␉{␊
212␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉else␊
215␉␉␉␉␉␉{␊
216␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
217␉␉␉␉␉␉}␊
218␉␉␉␉␉␉return true;␊
219␊
220␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7, Xeon E3-12xx LGA1155 (32nm)␊
221␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
222␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
223␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
224␉␉␉␉␉␉{␊
225␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
226␉␉␉␉␉␉}␊
227␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
228␉␉␉␉␉␉{␊
229␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉// Core i3␊
230␉␉␉␉␉␉}␊
231␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
232␉␉␉␉␉␉{␊
233␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
234␉␉␉␉␉␉}␊
235␉␉␉␉␉␉else␊
236␉␉␉␉␉␉{␊
237␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
238␉␉␉␉␉␉}␊
239␉␉␉␉␉␉return true;␊
240␉␉␉␉}␊
241␉␉␉}␊
242␉␉}␊
243␉}␊
244␉␊
245␉return false;␊
246}␊
247␊
248bool getSMBMemoryDeviceMemoryType(returnType *value)␊
249{␊
250␉static int idx = -1;␊
251␉int␉map;␊
252␊
253␉idx++;␊
254␉if (idx < MAX_RAM_SLOTS)␊
255␉{␊
256␉␉map = Platform.DMI.DIMM[idx];␊
257␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
258␉␉{␊
259␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
260␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
261␉␉␉return true;␊
262␉␉}␊
263␉}␊
264␉␊
265␉return false;␊
266//␉value->byte = SMB_MEM_TYPE_DDR2;␊
267//␉return true;␊
268}␊
269␊
270bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
271{␊
272 value->word = 0xFFFF;␊
273 return true;␊
274}␊
275␊
276bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
277{␊
278␉static int idx = -1;␊
279␉int␉map;␊
280␊
281␉idx++;␊
282␉if (idx < MAX_RAM_SLOTS)␊
283␉{␊
284␉␉map = Platform.DMI.DIMM[idx];␊
285␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
286␉␉{␊
287␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
288␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
289␉␉␉return true;␊
290␉␉}␊
291␉}␊
292␊
293␉return false;␊
294//␉value->dword = 800;␊
295//␉return true;␊
296}␊
297␊
298bool getSMBMemoryDeviceManufacturer(returnType *value)␊
299{␊
300␉static int idx = -1;␊
301␉int␉map;␊
302␊
303␉idx++;␊
304␉if (idx < MAX_RAM_SLOTS)␊
305␉{␊
306␉␉map = Platform.DMI.DIMM[idx];␊
307␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
308␉␉{␊
309␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
310␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
311␉␉␉return true;␊
312␉␉}␊
313␉}␊
314␊
315␉if (!bootInfo->memDetect)␊
316␉{␊
317␉␉return false;␊
318␉}␊
319␉value->string = NOT_AVAILABLE;␊
320␉return true;␊
321}␊
322␉␊
323bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
324{␊
325␉static int idx = -1;␊
326␉int␉map;␊
327␊
328␉idx++;␊
329␊
330 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
331␊
332␉if (idx < MAX_RAM_SLOTS)␊
333␉{␊
334␉␉map = Platform.DMI.DIMM[idx];␊
335␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
336␉␉{␊
337␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
338␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
339␉␉␉return true;␊
340␉␉}␊
341␉}␊
342␊
343␉if (!bootInfo->memDetect)␊
344␉{␊
345␉␉return false;␊
346␉}␊
347␉value->string = NOT_AVAILABLE;␊
348␉return true;␊
349}␊
350␊
351bool getSMBMemoryDevicePartNumber(returnType *value)␊
352{␊
353␉static int idx = -1;␊
354␉int␉map;␊
355␊
356␉idx++;␊
357␉if (idx < MAX_RAM_SLOTS)␊
358␉{␊
359␉␉map = Platform.DMI.DIMM[idx];␊
360␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
361␉␉{␊
362␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
363␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
364␉␉␉return true;␊
365␉␉}␊
366␉}␊
367␊
368␉if (!bootInfo->memDetect)␊
369␉{␊
370␉␉return false;␊
371␉}␊
372␉value->string = NOT_AVAILABLE;␊
373␉return true;␊
374}␊
375␊
376␊
377// getting smbios addr with fast compare ops, late checksum testing ...␊
378#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
379static const char * const SMTAG = "_SM_";␊
380static const char* const DMITAG = "_DMI_";␊
381␊
382SMBEntryPoint *getAddressOfSmbiosTable(void)␊
383{␊
384␉SMBEntryPoint␉*smbios;␊
385␉/* ␊
386␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
387␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
388␉ */␊
389␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
390␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
391␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
392␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
393␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
394␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
395␉ {␊
396␉␉␉return smbios;␊
397␉ }␊
398␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
399␉}␊
400␉printf("ERROR: Unable to find SMBIOS!\n");␊
401␉pause();␊
402␉return NULL;␊
403}␊
404␊
405

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