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Root/branches/ErmaC/Trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72int spd_indexes[] = {␊
73␉SPD_MEMORY_TYPE,␊
74␉SPD_DDR3_MEMORY_BANK,␊
75␉SPD_DDR3_MEMORY_CODE,␊
76␉SPD_NUM_ROWS,␊
77␉SPD_NUM_COLUMNS,␊
78␉SPD_NUM_DIMM_BANKS,␊
79␉SPD_NUM_BANKS_PER_SDRAM,␊
80␉4,7,8,9,12,64, /* TODO: give names to these values */␊
81␉95,96,97,98, 122,123,124,125 /* UIS */␊
82};␊
83#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
84␊
85/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
86␊
87unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
88{␊
89␉int l1, h1, l2, h2;␊
90␉unsigned long long t;␊
91␊
92␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
93␉outb(base + SMBHSTDAT, 0xff);␊
94␊
95␉rdtsc(l1, h1);␊
96␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
97␉{␊
98␉␉rdtsc(l2, h2);␊
99␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
100␉␉if (t > 5)␊
101␉␉{␊
102␉␉␉return 0xFF;␉// break␊
103␉␉}␊
104␉}␊
105␊
106␉outb(base + SMBHSTCMD, cmd);␊
107␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
108␉outb(base + SMBHSTCNT, 0x48 );␊
109␊
110␉rdtsc(l1, h1);␊
111␊
112␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
113␉{␊
114␉␉rdtsc(l2, h2);␊
115␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
116␉␉if (t > 5)␊
117␉␉{␊
118␉␉␉break;␉// break after 5ms␊
119␉␉}␊
120␉}␊
121␉return inb(base + SMBHSTDAT);␊
122}␊
123␊
124/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
125#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
126␊
127␊
128/** Read from spd *used* values only*/␊
129static void init_spd(char * spd, uint32_t base, int slot)␊
130{␊
131␉int i;␊
132␉for (i=0; i< SPD_INDEXES_SIZE; i++)␊
133␉{␊
134␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
135␉}␊
136}␊
137␊
138/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
139 have different formats, always return a valid ptr.*/␊
140const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
141{␊
142␉uint8_t bank = 0;␊
143␉uint8_t code = 0;␊
144␉int i = 0;␊
145␉uint8_t * spd = (uint8_t *) slot->spd;␊
146␊
147␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
148␉{ // DDR3␊
149␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
150␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
151␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
152␉␉{␊
153␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
154␉␉␉{␊
155␉␉␉␉return vendorMap[i].name;␊
156␉␉␉}␊
157␉␉}␊
158␉}␊
159␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
160␉{␊
161␉␉if(spd[64]==0x7f)␊
162␉␉{␊
163␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
164␉␉␉{␊
165␉␉␉␉bank++;␊
166␉␉␉␉READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
167␉␉␉}␊
168␉␉␉READ_SPD(spd, base, slot_num,i);␊
169␉␉␉code = spd[i];␊
170␉␉}␊
171␉␉else␊
172␉␉{␊
173␉␉␉code = spd[64]; ␊
174␉␉␉bank = 0;␊
175␉␉}␊
176␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
177␉␉{␊
178␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
179␉␉␉{␊
180␉␉␉␉return vendorMap[i].name;␊
181␉␉␉}␊
182␉␉}␊
183␉}␊
184␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
185␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
186␉{␊
187␉␉return "Unifosa";␊
188␉}␊
189␉return "NoName";␊
190}␊
191␊
192/* Get Default Memory Module Speed (no overclocking handled) */␊
193int getDDRspeedMhz(const char * spd)␊
194{␊
195␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
196␉{ ␊
197␉␉switch(spd[12])␊
198␉␉{␊
199␉␉␉case 0x0f:␊
200␉␉␉␉return 1066;␊
201␉␉␉case 0x0c:␊
202␉␉␉␉return 1333;␊
203␉␉␉case 0x0a:␊
204␉␉␉␉return 1600;␊
205␉␉␉case 0x14:␊
206␉␉␉default:␊
207␉␉␉␉return 800;␊
208␉␉}␊
209␉} ␊
210␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
211␉{␊
212␉␉switch(spd[9])␊
213␉␉{␊
214␉␉␉case 0x50:␊
215␉␉␉␉return 400;␊
216␉␉␉case 0x3d:␊
217␉␉␉␉return 533;␊
218␉␉␉case 0x30:␊
219␉␉␉␉return 667;␊
220␉␉␉case 0x25:␊
221␉␉␉default:␊
222␉␉␉␉return 800;␊
223␉␉}␊
224␉}␊
225␉return 800; // default freq for unknown types␊
226}␊
227␊
228#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
229#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
230␊
231/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
232const char *getDDRSerial(const char* spd)␊
233{␊
234␉static char asciiSerial[16];␊
235 ␊
236␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
237␉{␊
238␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
239␉}␊
240␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
241␉{␊
242␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
243␉}␊
244␊
245␉return strdup(asciiSerial);␊
246}␊
247␊
248/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
249const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
250{␊
251␉static char asciiPartNo[32];␊
252␉int i, start=0, index = 0;␊
253␊
254␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
255␉{␊
256␉␉start = 128;␊
257␉}␊
258␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
259␉{␊
260␉␉start = 73;␊
261␉}␊
262␉␊
263␉// Check that the spd part name is zero terminated and that it is ascii:␊
264␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
265␉char c;␊
266␉for (i=start; i < start + sizeof(asciiPartNo); i++)␊
267␉{␊
268␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
269␉␉c = spd[i];␊
270␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
271␉␉{␊
272␉␉␉// It seems that System Profiler likes only letters and digits...␊
273␉␉␉asciiPartNo[index++] = c;␊
274␉␉}␊
275␉␉else if (!isascii(c))␊
276␉␉{␊
277␉␉␉break;␊
278␉␉}␊
279␉}␊
280␉␊
281␉return strdup(asciiPartNo);␊
282}␊
283␊
284int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
285␊
286␊
287/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
288static void read_smb_intel(pci_dt_t *smbus_dev)␊
289{ ␊
290␉int i, speed;␊
291␉uint8_t spd_size, spd_type;␊
292␉uint32_t base, mmio, hostc;␊
293//␉bool dump = false;␊
294␉RamSlotInfo_t* slot;␊
295␊
296␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
297␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
298␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
299␊
300␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
301␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
302␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
303␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
304␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
305␊
306␉//Azi: no use for this!␊
307␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
308␉// needed at least for laptops␊
309␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
310␊
311␉char spdbuf[MAX_SPD_SIZE];␊
312␉// Search MAX_RAM_SLOTS slots␊
313␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
314␉{␊
315␉␉slot = &Platform.RAM.DIMM[i];␊
316␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
317␉␉DBG("SPD[0] (size): 0x%02x @0x%x\n", spd_size, 0x50 + i);␊
318␉␉// Check spd is present␊
319␉␉if (spd_size && (spd_size != 0xff))␊
320␉␉{␊
321␊
322␉␉␉slot->spd = spdbuf;␊
323␉␉␉slot->InUse = true;␊
324␊
325␉␉␉bzero(slot->spd, spd_size);␊
326␊
327␉␉␉// Copy spd data into buffer␊
328␊
329␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
330␉␉␉init_spd(slot->spd, base, i);␊
331␊
332␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
333␉␉␉{␊
334␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
335␊
336␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) * ␊
337␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
338␉␉␉␉break;␊
339␊
340␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
341␊
342␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
343␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
344␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
345␊
346␉␉␉␉break;␊
347␉␉␉}␊
348␊
349␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
350␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
351␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
352␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
353␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
354␊
355␉␉␉// determine spd speed␊
356␉␉␉speed = getDDRspeedMhz(slot->spd);␊
357␉␉␉if (slot->Frequency<speed)␊
358␉␉␉{␊
359␉␉␉␉slot->Frequency = speed;␊
360␉␉␉}␊
361␉␉␉␊
362␉␉␉// pci memory controller if available, is more reliable␊
363␉␉␉if (Platform.RAM.Frequency > 0)␊
364␉␉␉{␊
365␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
366␉␉␉␉// now round off special cases␊
367␉␉␉␉uint32_t fmod100 = freq %100;␊
368␉␉␉␉switch(fmod100)␊
369␉␉␉␉{␊
370␉␉␉␉␉case 1:␉freq--;␉break;␊
371␉␉␉␉␉case 32:␉freq++;␉break;␊
372␉␉␉␉␉case 65:␉freq++; break;␊
373␉␉␉␉␉case 98:␉freq+=2;break;␊
374␉␉␉␉␉case 99:␉freq++; break;␊
375␉␉␉␉}␊
376␉␉␉␉slot->Frequency = freq;␊
377␉␉␉}␊
378␊
379␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
380 i, ␊
381 (int)slot->Type,␊
382 slot->ModuleSize, ␊
383 spd_memory_types[spd_type],␊
384 slot->Frequency,␊
385 slot->Vendor,␊
386 slot->PartNo,␊
387 slot->SerialNo); ␊
388␊
389␊
390␉␉}␊
391␊
392␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
393␉␉Platform.DMI.DIMM[i]= ␊
394 ␉i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ? ␊
395 ␉mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
396␉␉slot->spd = NULL;␊
397␊
398␉} // for␊
399}␊
400␊
401static struct smbus_controllers_t smbus_controllers[] = {␊
402// Info from here: http://cateee.net/lkddb/web-lkddb/I2C_I801.html␊
403␊
404␉{0x8086, 0x1C22, "6 Series", read_smb_intel },␊
405␉{0x8086, 0x1D22, "C600/X79 Series", read_smb_intel },␊
406␉{0x8086, 0x1D70, "C600/X79 Series", read_smb_intel },␊
407␉{0x8086, 0x1D71, "C608/C606/X79 Series", read_smb_intel },␊
408␉{0x8086, 0x1D72, "C608", read_smb_intel },␊
409␉{0x8086, 0x1E22, "7 Series/C210 Series", read_smb_intel },␊
410␉{0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
411␉{0x8086, 0x2413, "82801AA", read_smb_intel },␊
412␉{0x8086, 0x2423, "82801BA/BAM", read_smb_intel },␊
413␉{0x8086, 0x2443, "82801BA/BAM", read_smb_intel },␊
414␉{0x8086, 0x2483, "82801CA/CAM", read_smb_intel },␊
415␉{0x8086, 0x24C3, "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)", read_smb_intel },␊
416␉{0x8086, 0x24D3, "82801EB/ER (ICH5/ICH5R)", read_smb_intel },␊
417␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
418␉{0x8086, 0x266A, "82801FB/FBM/FR/FW/FRW (ICH6 Family)", read_smb_intel },␊
419␉{0x8086, 0x269B, "631xESB/632xESB/3100", read_smb_intel },␊
420␉{0x8086, 0x27DA, "N10/ICH 7 Family", read_smb_intel },␊
421␉{0x8086, 0x283E, "82801H (ICH8 Family) ", read_smb_intel },␊
422␉{0x8086, 0x2930, "82801I (ICH9 Family)", read_smb_intel },␉␊
423␉{0x8086, 0x3A30, "82801JI (ICH10 Family)", read_smb_intel },␊
424␉{0x8086, 0x3A60, "82801JD/DO (ICH10 Family)", read_smb_intel },␊
425␉{0x8086, 0x3B30, "5 Series/3400 Series", read_smb_intel },␊
426␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
427␊
428};␊
429␊
430// initial call : pci_dt = root_pci_dev;␊
431// find_and_read_smbus_controller(root_pci_dev);␊
432bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
433{␊
434␉pci_dt_t␉*current = pci_dt;␊
435␉int i;␊
436␊
437␉while (current)␊
438␉{␊
439#if 0␊
440␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
441␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
442␉␉current->class_id, current->vendor_id, current->device_id, ␊
443␉␉get_pci_dev_path(current));␊
444#endif␊
445␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
446␉␉{␊
447␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
448␉␉␉{␊
449␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
450␉␉␉␉return true;␊
451␉␉␉}␊
452␉␉}␊
453␉␉find_and_read_smbus_controller(current->children);␊
454␉␉current = current->next;␊
455␉}␊
456␉return false; // not found␊
457}␊
458␊
459void scan_spd(PlatformInfo_t *p)␊
460{␊
461␉find_and_read_smbus_controller(root_pci_dev);␊
462}␊
463␊
464

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