| 1 | /*␊ |
| 2 | * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.␊ |
| 3 | *␊ |
| 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@␊ |
| 5 | * ␊ |
| 6 | * This file contains Original Code and/or Modifications of Original Code␊ |
| 7 | * as defined in and that are subject to the Apple Public Source License␊ |
| 8 | * Version 2.0 (the 'License'). You may not use this file except in␊ |
| 9 | * compliance with the License. The rights granted to you under the License␊ |
| 10 | * may not be used to create, or enable the creation or redistribution of,␊ |
| 11 | * unlawful or unlicensed copies of an Apple operating system, or to␊ |
| 12 | * circumvent, violate, or enable the circumvention or violation of, any␊ |
| 13 | * terms of an Apple operating system software license agreement.␊ |
| 14 | * ␊ |
| 15 | * Please obtain a copy of the License at␊ |
| 16 | * http://www.opensource.apple.com/apsl/ and read it before using this file.␊ |
| 17 | * ␊ |
| 18 | * The Original Code and all software distributed under the License are␊ |
| 19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER␊ |
| 20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,␊ |
| 21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,␊ |
| 22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.␊ |
| 23 | * Please see the License for the specific language governing rights and␊ |
| 24 | * limitations under the License.␊ |
| 25 | * ␊ |
| 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@␊ |
| 27 | */␊ |
| 28 | /*␊ |
| 29 | * @OSF_COPYRIGHT@␊ |
| 30 | */␊ |
| 31 | ␊ |
| 32 | /*␊ |
| 33 | * x86 CPU identification␊ |
| 34 | *␊ |
| 35 | */␊ |
| 36 | ␊ |
| 37 | #ifndef _MACHINE_CPUID_H_␊ |
| 38 | #define _MACHINE_CPUID_H_␊ |
| 39 | ␊ |
| 40 | #include <stdint.h>␊ |
| 41 | ␊ |
| 42 | #define␉CPUID_VID_INTEL␉␉"GenuineIntel"␊ |
| 43 | #define␉CPUID_VID_AMD␉␉"AuthenticAMD"␊ |
| 44 | ␊ |
| 45 | #define CPUID_STRING_UNKNOWN "Unknown CPU Typ"␊ |
| 46 | ␊ |
| 47 | #define _Bit(n)␉␉␉(1ULL << n)␊ |
| 48 | #define _HBit(n)␉␉(1ULL << ((n)+32))␊ |
| 49 | ␊ |
| 50 | /*␊ |
| 51 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
| 52 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
| 53 | */␊ |
| 54 | #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
| 55 | #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
| 56 | #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
| 57 | #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
| 58 | #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
| 59 | #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
| 60 | #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
| 61 | #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
| 62 | #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
| 63 | #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
| 64 | #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
| 65 | #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
| 66 | #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
| 67 | #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
| 68 | #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
| 69 | #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
| 70 | #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
| 71 | #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
| 72 | #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
| 73 | #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
| 74 | #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
| 75 | #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
| 76 | #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
| 77 | #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
| 78 | #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
| 79 | #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
| 80 | #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
| 81 | #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
| 82 | #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
| 83 | ␊ |
| 84 | #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
| 85 | #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
| 86 | #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
| 87 | #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
| 88 | #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
| 89 | #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
| 90 | #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
| 91 | #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
| 92 | #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
| 93 | #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
| 94 | #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
| 95 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
| 96 | #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
| 97 | #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
| 98 | #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
| 99 | ␊ |
| 100 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
| 101 | #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
| 102 | #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
| 103 | #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
| 104 | #define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */␊ |
| 105 | #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
| 106 | #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
| 107 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
| 108 | #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
| 109 | #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
| 110 | #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
| 111 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
| 112 | #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
| 113 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
| 114 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
| 115 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
| 116 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
| 117 | #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
| 118 | #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
| 119 | ␊ |
| 120 | /*␊ |
| 121 | * Leaf 7, subleaf 0 additional features.␊ |
| 122 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
| 123 | */␊ |
| 124 | #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
| 125 | #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
| 126 | #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
| 127 | ␊ |
| 128 | /*␊ |
| 129 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 130 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
| 131 | */␊ |
| 132 | #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
| 133 | #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
| 134 | ␊ |
| 135 | #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
| 136 | #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
| 137 | #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
| 138 | ␊ |
| 139 | #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
| 140 | ␊ |
| 141 | /*␊ |
| 142 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 143 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
| 144 | */␊ |
| 145 | #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
| 146 | ␊ |
| 147 | #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
| 148 | ␊ |
| 149 | #define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊ |
| 150 | #define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊ |
| 151 | ␊ |
| 152 | #define CPUID_MODEL_YONAH␉0x0E␊ |
| 153 | #define CPUID_MODEL_MEROM␉0x0F␊ |
| 154 | #define CPUID_MODEL_PENRYN␉0x17␊ |
| 155 | #define CPUID_MODEL_NEHALEM␉0x1A␊ |
| 156 | #define CPUID_MODEL_FIELDS␉0x1E␉/* Lynnfield, Clarksfield, Jasper */␊ |
| 157 | #define CPUID_MODEL_DALES␉0x1F␉/* Havendale, Auburndale */␊ |
| 158 | #define CPUID_MODEL_NEHALEM_EX␉0x2E␊ |
| 159 | #define CPUID_MODEL_DALES_32NM␉0x25␉/* Clarkdale, Arrandale */␊ |
| 160 | #define CPUID_MODEL_WESTMERE␉0x2C␉/* Gulftown, Westmere-EP, Westmere-WS */␊ |
| 161 | #define CPUID_MODEL_WESTMERE_EX␉0x2F␊ |
| 162 | #define CPUID_MODEL_SANDYBRIDGE␉0x2A␊ |
| 163 | #define CPUID_MODEL_JAKETOWN␉0x2D␊ |
| 164 | #define CPUID_MODEL_IVYBRIDGE␉0x3A␊ |
| 165 | ␊ |
| 166 | typedef enum { eax, ebx, ecx, edx } cpuid_register_t;␊ |
| 167 | ␊ |
| 168 | #if UNUSED␊ |
| 169 | static inline void␊ |
| 170 | cpuid(uint32_t *data)␊ |
| 171 | {␊ |
| 172 | ␉asm("cpuid"␊ |
| 173 | ␉␉: "=a" (data[eax]),␊ |
| 174 | ␉␉ "=b" (data[ebx]),␊ |
| 175 | ␉␉ "=c" (data[ecx]),␊ |
| 176 | ␉␉ "=d" (data[edx])␊ |
| 177 | ␉␉: "a" (data[eax]),␊ |
| 178 | ␉␉ "b" (data[ebx]),␊ |
| 179 | ␉␉ "c" (data[ecx]),␊ |
| 180 | ␉␉ "d" (data[edx]));␊ |
| 181 | }␊ |
| 182 | #endif␊ |
| 183 | ␊ |
| 184 | static inline void␊ |
| 185 | do_cpuid(uint32_t selector, uint32_t *data)␊ |
| 186 | {␊ |
| 187 | ␉asm("cpuid"␊ |
| 188 | ␉␉: "=a" (data[0]),␊ |
| 189 | ␉␉ "=b" (data[1]),␊ |
| 190 | ␉␉ "=c" (data[2]),␊ |
| 191 | ␉␉ "=d" (data[3])␊ |
| 192 | ␉␉: "a"(selector),␊ |
| 193 | ␉␉ "b" (0),␊ |
| 194 | ␉␉ "c" (0),␊ |
| 195 | ␉␉ "d" (0));␊ |
| 196 | }␊ |
| 197 | ␊ |
| 198 | /*␊ |
| 199 | * Cache ID descriptor structure, used to parse CPUID leaf 2.␊ |
| 200 | * Note: not used in kernel.␊ |
| 201 | */␊ |
| 202 | typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; ␊ |
| 203 | typedef struct {␊ |
| 204 | ␉unsigned char␉value; /* Descriptor value */␊ |
| 205 | ␉cache_type_t ␉type; /* Cache type */␊ |
| 206 | ␉unsigned int ␉size; /* Cache size */␊ |
| 207 | ␉unsigned int ␉linesize; /* Cache line size */␊ |
| 208 | #ifdef KERNEL␊ |
| 209 | ␉const char␉*description; /* Cache description */␊ |
| 210 | #endif /* KERNEL */␊ |
| 211 | } cpuid_cache_desc_t; ␊ |
| 212 | ␊ |
| 213 | #ifdef KERNEL␊ |
| 214 | #define CACHE_DESC(value,type,size,linesize,text) \␊ |
| 215 | ␉{ value, type, size, linesize, text }␊ |
| 216 | #else␊ |
| 217 | #define CACHE_DESC(value,type,size,linesize,text) \␊ |
| 218 | ␉{ value, type, size, linesize }␊ |
| 219 | #endif /* KERNEL */␊ |
| 220 | ␊ |
| 221 | /* Monitor/mwait Leaf: */␊ |
| 222 | typedef struct {␊ |
| 223 | ␉uint32_t␉linesize_min;␊ |
| 224 | ␉uint32_t␉linesize_max;␊ |
| 225 | ␉uint32_t␉extensions;␊ |
| 226 | ␉uint32_t␉sub_Cstates;␊ |
| 227 | } cpuid_mwait_leaf_t;␊ |
| 228 | ␊ |
| 229 | /* Thermal and Power Management Leaf: */␊ |
| 230 | typedef struct {␊ |
| 231 | ␉boolean_t␉sensor;␊ |
| 232 | ␉boolean_t␉dynamic_acceleration;␊ |
| 233 | ␉boolean_t␉invariant_APIC_timer;␊ |
| 234 | ␉boolean_t␉core_power_limits;␊ |
| 235 | ␉boolean_t␉fine_grain_clock_mod;␊ |
| 236 | ␉boolean_t␉package_thermal_intr;␊ |
| 237 | ␉uint32_t␉thresholds;␊ |
| 238 | ␉boolean_t␉ACNT_MCNT;␊ |
| 239 | ␉boolean_t␉hardware_feedback;␊ |
| 240 | ␉boolean_t␉energy_policy;␊ |
| 241 | } cpuid_thermal_leaf_t;␊ |
| 242 | ␊ |
| 243 | ␊ |
| 244 | /* XSAVE Feature Leaf: */␊ |
| 245 | typedef struct {␊ |
| 246 | ␉uint32_t␉extended_state[4];␉/* eax .. edx */␊ |
| 247 | } cpuid_xsave_leaf_t;␊ |
| 248 | ␊ |
| 249 | ␊ |
| 250 | /* Architectural Performance Monitoring Leaf: */␊ |
| 251 | typedef struct {␊ |
| 252 | ␉uint8_t␉␉version;␊ |
| 253 | ␉uint8_t␉␉number;␊ |
| 254 | ␉uint8_t␉␉width;␊ |
| 255 | ␉uint8_t␉␉events_number;␊ |
| 256 | ␉uint32_t␉events;␊ |
| 257 | ␉uint8_t␉␉fixed_number;␊ |
| 258 | ␉uint8_t␉␉fixed_width;␊ |
| 259 | } cpuid_arch_perf_leaf_t;␊ |
| 260 | ␊ |
| 261 | /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */␊ |
| 262 | typedef struct {␊ |
| 263 | ␉char␉␉cpuid_vendor[16];␊ |
| 264 | ␉char␉␉cpuid_brand_string[48];␊ |
| 265 | ␉const char␉*cpuid_model_string;␊ |
| 266 | ␊ |
| 267 | ␉cpu_type_t␉cpuid_type;␉/* this is *not* a cpu_type_t in our <mach/machine.h> */␊ |
| 268 | ␉uint8_t␉␉cpuid_family;␊ |
| 269 | ␉uint8_t␉␉cpuid_model;␊ |
| 270 | ␉uint8_t␉␉cpuid_extmodel;␊ |
| 271 | ␉uint8_t␉␉cpuid_extfamily;␊ |
| 272 | ␉uint8_t␉␉cpuid_stepping;␊ |
| 273 | ␉uint64_t␉cpuid_features;␊ |
| 274 | ␉uint64_t␉cpuid_extfeatures;␊ |
| 275 | ␉uint32_t␉cpuid_signature;␊ |
| 276 | ␉uint8_t ␉cpuid_brand; ␊ |
| 277 | uint8_t␉␉cpuid_processor_flag;␊ |
| 278 | ␊ |
| 279 | ␉uint32_t␉cache_size[LCACHE_MAX];␊ |
| 280 | ␉uint32_t␉cache_linesize;␊ |
| 281 | ␊ |
| 282 | ␉uint8_t␉␉cache_info[64]; /* list of cache descriptors */␊ |
| 283 | ␊ |
| 284 | ␉uint32_t␉cpuid_cores_per_package;␊ |
| 285 | ␉uint32_t␉cpuid_logical_per_package;␊ |
| 286 | ␉uint32_t␉cache_sharing[LCACHE_MAX];␊ |
| 287 | ␉uint32_t␉cache_partitions[LCACHE_MAX];␊ |
| 288 | ␊ |
| 289 | ␉cpu_type_t␉cpuid_cpu_type;␉␉␉/* <mach/machine.h> */␊ |
| 290 | ␉cpu_subtype_t␉cpuid_cpu_subtype;␉␉/* <mach/machine.h> */␉␊ |
| 291 | ␊ |
| 292 | ␉/* Per-vendor info */␊ |
| 293 | ␉cpuid_mwait_leaf_t␉cpuid_mwait_leaf;␉␊ |
| 294 | #define cpuid_mwait_linesize_max␉cpuid_mwait_leaf.linesize_max␊ |
| 295 | #define cpuid_mwait_linesize_min␉cpuid_mwait_leaf.linesize_min␊ |
| 296 | #define cpuid_mwait_extensions␉␉cpuid_mwait_leaf.extensions␊ |
| 297 | #define cpuid_mwait_sub_Cstates␉␉cpuid_mwait_leaf.sub_Cstates␊ |
| 298 | ␉cpuid_thermal_leaf_t␉cpuid_thermal_leaf;␊ |
| 299 | ␉cpuid_arch_perf_leaf_t␉cpuid_arch_perf_leaf;␊ |
| 300 | ␉cpuid_xsave_leaf_t␉cpuid_xsave_leaf;␊ |
| 301 | ␊ |
| 302 | ␉/* Cache details: */␊ |
| 303 | ␉uint32_t␉cpuid_cache_linesize;␊ |
| 304 | ␉uint32_t␉cpuid_cache_L2_associativity;␊ |
| 305 | ␉uint32_t␉cpuid_cache_size;␊ |
| 306 | ␊ |
| 307 | ␉/* Virtual and physical address aize: */␊ |
| 308 | ␉uint32_t␉cpuid_address_bits_physical;␊ |
| 309 | ␉uint32_t␉cpuid_address_bits_virtual;␊ |
| 310 | ␊ |
| 311 | ␉uint32_t␉cpuid_microcode_version;␊ |
| 312 | ␊ |
| 313 | ␉/* Numbers of tlbs per processor [i|d, small|large, level0|level1] */␊ |
| 314 | ␉uint32_t␉cpuid_tlb[2][2][2];␊ |
| 315 | ␉␉␉#define␉TLB_INST␉0␊ |
| 316 | ␉␉␉#define␉TLB_DATA␉1␊ |
| 317 | ␉␉␉#define␉TLB_SMALL␉0␊ |
| 318 | ␉␉␉#define␉TLB_LARGE␉1␊ |
| 319 | ␉uint32_t␉cpuid_stlb;␊ |
| 320 | ␊ |
| 321 | ␉uint32_t␉core_count;␊ |
| 322 | ␉uint32_t␉thread_count;␊ |
| 323 | ␊ |
| 324 | ␉/* Max leaf ids available from CPUID */␊ |
| 325 | ␉uint32_t␉cpuid_max_basic;␊ |
| 326 | ␉uint32_t␉cpuid_max_ext;␊ |
| 327 | ␊ |
| 328 | ␉/* Family-specific info links */␊ |
| 329 | ␉uint32_t␉␉cpuid_cpufamily;␊ |
| 330 | ␉cpuid_mwait_leaf_t␉*cpuid_mwait_leafp;␉␊ |
| 331 | ␉cpuid_thermal_leaf_t␉*cpuid_thermal_leafp;␊ |
| 332 | ␉cpuid_arch_perf_leaf_t␉*cpuid_arch_perf_leafp;␊ |
| 333 | ␉cpuid_xsave_leaf_t␉*cpuid_xsave_leafp;␊ |
| 334 | uint32_t␉␉cpuid_leaf7_features;␊ |
| 335 | } i386_cpu_info_t;␊ |
| 336 | ␊ |
| 337 | ␊ |
| 338 | #endif /* _MACHINE_CPUID_H_ */␊ |
| 339 | |
