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Root/branches/mozodojo/i386/libsaio/spd.c

1/*
2 * spd.c - serial presence detect memory information
3 * (restored from pcefi10.5)
4 */
5
6#include "libsaio.h"
7#include "pci.h"
8#include "platform.h"
9#include "spd.h"
10#include "saio_internal.h"
11#include "bootstruct.h"
12#include "memvendors.h"
13
14#ifndef DEBUG_SPD
15#define DEBUG_SPD 0
16#endif
17
18#if DEBUG_SPD
19#define DBG(x...)printf(x)
20#else
21#define DBG(x...)
22#endif
23
24static const char *spd_memory_types[] =
25{
26"RAM", /* 00h Undefined */
27"FPM", /* 01h FPM */
28"EDO", /* 02h EDO */
29"",/* 03h PIPELINE NIBBLE */
30"SDRAM", /* 04h SDRAM */
31"",/* 05h MULTIPLEXED ROM */
32"DDR SGRAM",/* 06h SGRAM DDR */
33"DDR SDRAM",/* 07h SDRAM DDR */
34"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
35"",/* 09h Undefined */
36"",/* 0Ah Undefined */
37"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */
38};
39
40#define UNKNOWN_MEM_TYPE 2
41static uint8_t spd_mem_to_smbios[] =
42{
43UNKNOWN_MEM_TYPE, /* 00h Undefined */
44UNKNOWN_MEM_TYPE, /* 01h FPM */
45UNKNOWN_MEM_TYPE, /* 02h EDO */
46UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */
47SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */
48SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */
49SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */
50SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */
51SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */
52UNKNOWN_MEM_TYPE, /* 09h Undefined */
53UNKNOWN_MEM_TYPE, /* 0Ah Undefined */
54SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */
55};
56#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))
57
58#define rdtsc(low,high) \
59__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
60
61#define SMBHSTSTS 0
62#define SMBHSTCNT 2
63#define SMBHSTCMD 3
64#define SMBHSTADD 4
65#define SMBHSTDAT 5
66#define SBMBLKDAT 7
67
68/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */
69unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)
70{
71 int l1, h1, l2, h2;
72 unsigned long long t;
73
74 outb(base + SMBHSTSTS, 0x1f);// reset SMBus Controller
75 outb(base + SMBHSTDAT, 0xff);
76
77 while( inb(base + SMBHSTSTS) & 0x01);// wait until ready
78
79 outb(base + SMBHSTCMD, cmd);
80 outb(base + SMBHSTADD, (adr << 1) | 0x01 );
81 outb(base + SMBHSTCNT, 0x48 );
82
83 rdtsc(l1, h1);
84
85 while (!( inb(base + SMBHSTSTS) & 0x02))// wait til command finished
86{
87rdtsc(l2, h2);
88t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 40);
89if (t > 10)
90break;// break after 10ms
91 }
92 return inb(base + SMBHSTDAT);
93}
94
95/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2,
96 have different formats, always return a valid ptr.*/
97const char * getVendorName(RamSlotInfo_t* slot)
98{
99 uint8_t bank = 0;
100 uint8_t code = 0;
101 int i = 0;
102 const char * spd = slot->spd;
103
104 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3
105 bank = spd[0x75];
106 code = spd[0x76];
107 for (i=0; i < VEN_MAP_SIZE; i++)
108 if (bank==vendorMap[i].bank && code==vendorMap[i].code)
109 return vendorMap[i].name;
110 }
111 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
112 if(spd[0x40]==0x7f) {
113 for (i=0x40; i<0x48 && spd[i]==0x7f;i++) bank++;
114 code = spd[i];
115 } else {
116 code = spd[0x40];
117 bank = 0;
118 }
119 for (i=0; i < VEN_MAP_SIZE; i++)
120 if (bank==vendorMap[i].bank && code==vendorMap[i].code)
121 return vendorMap[i].name;
122 }
123 /* OK there is no vendor id here lets try to match the partnum if it exists */
124 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint
125 return "Unifosa";
126 return "NoName";
127}
128
129/** Get Default Memory Module Speed (no overclocking handled) */
130int getDDRspeedMhz(const char * spd)
131{
132 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {
133 switch(spd[12]) {
134 case 0x0f:
135 return 1066;
136 case 0x0c:
137 return 1333;
138 case 0x0a:
139 return 1600;
140 case 0x14:
141 default:
142 return 800;
143 }
144 }
145 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
146 switch(spd[9]) {
147 case 0x50:
148 return 400;
149 case 0x3d:
150 return 533;
151 case 0x30:
152 return 667;
153 case 0x25:
154 default:
155 return 800;
156 }
157 }
158 return 800; // default freq for unknown types
159}
160
161#define UIS(a) ((uint32_t)spd[a])
162
163/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */
164const char *getDDRSerial(const char* spd)
165{
166 static char asciiSerial[16];
167
168if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3
169{
170sprintf(asciiSerial, "%c%c%c%c", spd[125] & 0x7f, spd[124], spd[123], spd[122]);
171 }
172 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR
173{
174sprintf(asciiSerial, "%c%c%c%c", spd[98] & 0x7f, spd[97], spd[96], spd[95]);
175 }
176
177return strdup(asciiSerial);
178}
179
180/** Get DDR3 or DDR2 Part Number, always return a valid ptr */
181const char * getDDRPartNum(const char* spd)
182{
183static char asciiPartNo[32];
184 const char * sPart = NULL;
185int i, index = 0;
186
187 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {
188sPart = &spd[128];
189}
190 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {
191sPart = &spd[73];
192}
193
194 if (sPart) { // Check that the spd part name is zero terminated and that it is ascii:
195bzero(asciiPartNo, 32);
196 for (i=0; i<32; i++) {
197char c = sPart[i];
198 if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...
199asciiPartNo[index++] = c;
200else if (!isascii(c))
201break;
202}
203
204return strdup(asciiPartNo);
205 }
206 return NULL;
207}
208
209int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};
210
211/** Read from smbus the SPD content and interpret it for detecting memory attributes */
212static void read_smb_intel(pci_dt_t *smbus_dev)
213{
214 int i, x, speed;
215 uint8_t spd_size, spd_type;
216 uint32_t base;
217 bool dump = false;
218 RamSlotInfo_t* slot;
219
220 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
221 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);
222
223 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);
224 bool fullBanks = // needed at least for laptops
225 Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;
226 // Search MAX_RAM_SLOTS slots
227 for (i = 0; i < MAX_RAM_SLOTS; i++){
228 slot = &Platform.RAM.DIMM[i];
229 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
230
231 // Check spd is present
232 if (spd_size && (spd_size != 0xff) ) {
233 slot->spd = malloc(spd_size);
234 if (slot->spd == NULL) continue;
235
236 slot->InUse = true;
237
238 bzero(slot->spd, spd_size);
239
240 // Copy spd data into buffer
241 for (x = 0; x < spd_size; x++)
242 slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);
243
244 switch (slot->spd[SPD_MEMORY_TYPE]) {
245 case SPD_MEMORY_TYPE_SDRAM_DDR2:
246
247 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) *
248 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);
249 break;
250
251 case SPD_MEMORY_TYPE_SDRAM_DDR3:
252
253 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );
254 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;
255 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));
256
257 break;
258 }
259
260 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);
261 slot->Type = spd_mem_to_smbios[spd_type];
262 slot->PartNo = getDDRPartNum(slot->spd);
263 slot->Vendor = getVendorName(slot);
264 slot->SerialNo = getDDRSerial(slot->spd);
265
266 // determine spd speed
267 speed = getDDRspeedMhz(slot->spd);
268 if (speed > slot->Frequency) slot->Frequency = speed; // just in case dmi wins on spd
269 if(dump) {
270 printf("Slot %d Type %d %dMB (%s) %dMHz Vendor=%s, PartNo=%s SerialNo=%s\n",
271 i,
272 (int)slot->Type,
273 slot->ModuleSize,
274 spd_memory_types[spd_type],
275 slot->Frequency,
276 slot->Vendor,
277 slot->PartNo,
278 slot->SerialNo);
279 dumpPhysAddr("spd content: ",slot->spd, spd_size);
280 getc();
281 }
282 }
283
284 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:
285 Platform.DMI.DIMM[i]=
286 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ?
287 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this
288
289 if (slot->spd) {
290 free(slot->spd);
291 slot->spd = NULL;
292 }
293
294 } // for
295}
296
297static struct smbus_controllers_t smbus_controllers[] = {
298
299{0x8086, 0x269B, "ESB2", read_smb_intel },
300{0x8086, 0x25A4, "6300ESB", read_smb_intel },
301{0x8086, 0x24C3, "ICH4", read_smb_intel },
302{0x8086, 0x24D3, "ICH5", read_smb_intel },
303{0x8086, 0x266A, "ICH6", read_smb_intel },
304{0x8086, 0x27DA, "ICH7", read_smb_intel },
305{0x8086, 0x283E, "ICH8", read_smb_intel },
306{0x8086, 0x2930, "ICH9", read_smb_intel },
307{0x8086, 0x3A30, "ICH10R", read_smb_intel },
308{0x8086, 0x3A60, "ICH10B", read_smb_intel },
309{0x8086, 0x3B30, "P55", read_smb_intel },
310{0x8086, 0x5032, "EP80579", read_smb_intel }
311
312};
313
314// initial call : pci_dt = root_pci_dev;
315// find_and_read_smbus_controller(root_pci_dev);
316bool find_and_read_smbus_controller(pci_dt_t* pci_dt)
317{
318 pci_dt_t*current = pci_dt;
319 int i;
320
321 while (current) {
322#if DEBUG_SPD
323 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n",
324 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func,
325 current->class_id, current->vendor_id, current->device_id,
326 get_pci_dev_path(current));
327#endif
328for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )
329 {
330 if (current->vendor_id == smbus_controllers[i].vendor &&
331 current->device_id == smbus_controllers[i].device)
332 {
333 smbus_controllers[i].read_smb(current); // read smb
334 return true;
335 }
336 }
337 find_and_read_smbus_controller(current->children);
338 current = current->next;
339 }
340 return false; // not found
341}
342
343void scan_spd(PlatformInfo_t *p)
344{
345 find_and_read_smbus_controller(root_pci_dev);
346}
347

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