| 1 | /*␊ |
| 2 | * resolution.h␊ |
| 3 | * ␊ |
| 4 | *␉NOTE: I don't beleive this code is production ready / should be in trunk␊ |
| 5 | * Atleast, not in it's current state. ␊ |
| 6 | *␊ |
| 7 | * Created by Evan Lojewski on 3/4/10.␊ |
| 8 | * Copyright 2009. All rights reserved.␊ |
| 9 | *␊ |
| 10 | */␊ |
| 11 | ␊ |
| 12 | #include "libsaio.h"␊ |
| 13 | #include "edid.h"␊ |
| 14 | #include "915resolution.h"␊ |
| 15 | ␊ |
| 16 | ␊ |
| 17 | void patchVideoBios()␊ |
| 18 | {␉␉␊ |
| 19 | ␉UInt32 x = 0, y = 0, bp = 0;␊ |
| 20 | ␉␊ |
| 21 | ␉getResolution(&x, &y, &bp);␊ |
| 22 | ␉␊ |
| 23 | ␉␊ |
| 24 | ␉if (x != 0 &&␊ |
| 25 | ␉␉y != 0 && ␊ |
| 26 | ␉␉bp != 0)␊ |
| 27 | ␉{␊ |
| 28 | ␉␉vbios_map * map;␊ |
| 29 | ␉␉␊ |
| 30 | ␉␉map = open_vbios(CT_UNKWN);␊ |
| 31 | ␉␉if(map)␊ |
| 32 | ␉␉{␊ |
| 33 | ␉␉␉unlock_vbios(map);␊ |
| 34 | ␉␉␉␊ |
| 35 | ␉␉␉set_mode(map, x, y, bp, 0, 0);␊ |
| 36 | ␉␉␉␊ |
| 37 | ␉␉␉relock_vbios(map);␊ |
| 38 | ␉␉␉␊ |
| 39 | ␉␉␉close_vbios(map);␊ |
| 40 | ␉␉}␊ |
| 41 | ␉}␉␉␊ |
| 42 | ␉␊ |
| 43 | }␊ |
| 44 | ␊ |
| 45 | ␊ |
| 46 | /* Copied from 915 resolution created by steve tomljenovic␊ |
| 47 | *␊ |
| 48 | * This code is based on the techniques used in :␊ |
| 49 | *␊ |
| 50 | * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊ |
| 51 | * for demonstrating how to shadow the VBIOS into system RAM␊ |
| 52 | * and then modify it.␊ |
| 53 | *␊ |
| 54 | * - 1280patch by Andrew Tipton (andrewtipton null li).␊ |
| 55 | *␊ |
| 56 | * - 855resolution by Alain Poirier␊ |
| 57 | *␊ |
| 58 | * This source code is into the public domain.␊ |
| 59 | */␊ |
| 60 | ␊ |
| 61 | /**␊ |
| 62 | **␊ |
| 63 | **/␊ |
| 64 | ␊ |
| 65 | #define CONFIG_MECH_ONE_ADDR␉0xCF8␊ |
| 66 | #define CONFIG_MECH_ONE_DATA␉0xCFC␊ |
| 67 | ␊ |
| 68 | int freqs[] = { 60, 75, 85 };␊ |
| 69 | ␊ |
| 70 | UInt32 get_chipset_id(void)␊ |
| 71 | {␊ |
| 72 | ␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊ |
| 73 | ␉return inl(CONFIG_MECH_ONE_DATA);␊ |
| 74 | }␊ |
| 75 | ␊ |
| 76 | chipset_type get_chipset(UInt32 id)␊ |
| 77 | {␊ |
| 78 | ␉chipset_type type;␊ |
| 79 | ␉␉␊ |
| 80 | ␉switch (id) {␊ |
| 81 | ␉␉case 0x35758086:␊ |
| 82 | ␉␉␉type = CT_830;␊ |
| 83 | ␉␉␉break;␊ |
| 84 | ␉␉␉␊ |
| 85 | ␉␉case 0x25608086:␊ |
| 86 | ␉␉␉type = CT_845G;␊ |
| 87 | ␉␉␉break;␊ |
| 88 | ␉␉␉␊ |
| 89 | ␉␉case 0x35808086:␊ |
| 90 | ␉␉␉type = CT_855GM;␊ |
| 91 | ␉␉␉break;␊ |
| 92 | ␉␉␉␊ |
| 93 | ␉␉case 0x25708086:␊ |
| 94 | ␉␉␉type = CT_865G;␊ |
| 95 | ␉␉␉break;␊ |
| 96 | ␉␉␉␊ |
| 97 | ␉␉case 0x25808086:␊ |
| 98 | ␉␉␉type = CT_915G;␊ |
| 99 | ␉␉␉break;␊ |
| 100 | ␉␉␉␊ |
| 101 | ␉␉case 0x25908086:␊ |
| 102 | ␉␉␉type = CT_915GM;␊ |
| 103 | ␉␉␉break;␊ |
| 104 | ␉␉␉␊ |
| 105 | ␉␉case 0x27708086:␊ |
| 106 | ␉␉␉type = CT_945G;␊ |
| 107 | ␉␉␉break;␊ |
| 108 | ␉␉␉␊ |
| 109 | ␉␉case 0x27a08086:␊ |
| 110 | ␉␉␉type = CT_945GM;␊ |
| 111 | ␉␉␉break;␊ |
| 112 | ␉␉␉␊ |
| 113 | ␉␉case 0x27ac8086:␊ |
| 114 | ␉␉␉type = CT_945GME;␊ |
| 115 | ␉␉␉break;␊ |
| 116 | ␉␉␉␊ |
| 117 | ␉␉case 0x29708086:␊ |
| 118 | ␉␉␉type = CT_946GZ;␊ |
| 119 | ␉␉␉break;␊ |
| 120 | ␉␉␉␊ |
| 121 | ␉␉case 0x27748086:␊ |
| 122 | ␉␉␉type = CT_955X;␊ |
| 123 | ␉␉␉break;␊ |
| 124 | ␉␉␉␊ |
| 125 | ␉␉case 0x277c8086:␊ |
| 126 | ␉␉␉type = CT_975X;␊ |
| 127 | ␉␉␉break;␊ |
| 128 | ␊ |
| 129 | ␉␉case 0x29a08086:␊ |
| 130 | ␉␉␉type = CT_G965;␊ |
| 131 | ␉␉␉break;␊ |
| 132 | ␉␉␉␊ |
| 133 | ␉␉case 0x29908086:␊ |
| 134 | ␉␉␉type = CT_Q965;␊ |
| 135 | ␉␉␉break;␊ |
| 136 | ␉␉␉␊ |
| 137 | ␉␉case 0x81008086:␊ |
| 138 | ␉␉␉type = CT_500;␊ |
| 139 | ␉␉␉break;␊ |
| 140 | ␉␉␉␊ |
| 141 | ␉␉case 0x2e108086:␊ |
| 142 | ␉␉case 0X2e908086:␊ |
| 143 | ␉␉␉type = CT_B43;␊ |
| 144 | ␉␉␉break;␊ |
| 145 | ␊ |
| 146 | ␉␉case 0x2e208086:␊ |
| 147 | ␉␉␉type = CT_P45;␊ |
| 148 | ␉␉␉break;␊ |
| 149 | ␊ |
| 150 | ␉␉case 0x2e308086:␊ |
| 151 | ␉␉␉type = CT_G41;␊ |
| 152 | ␉␉␉break;␊ |
| 153 | ␉␉␉␉␉␊ |
| 154 | ␉␉case 0x29c08086:␊ |
| 155 | ␉␉␉type = CT_G31;␊ |
| 156 | ␉␉␉break;␊ |
| 157 | ␉␉␉␊ |
| 158 | ␉␉case 0x29208086:␊ |
| 159 | ␉␉␉type = CT_G45;␊ |
| 160 | ␉␉␉break;␊ |
| 161 | ␉␉␉␊ |
| 162 | ␉␉case 0xA0108086:␊ |
| 163 | ␉␉␉type = CT_3150;␊ |
| 164 | ␉␉␉break;␊ |
| 165 | ␉␉␉␊ |
| 166 | ␉␉case 0x2a008086:␊ |
| 167 | ␉␉␉type = CT_965GM;␊ |
| 168 | ␉␉␉break;␊ |
| 169 | ␉␉␉␊ |
| 170 | ␉␉case 0x29e08086:␊ |
| 171 | ␉␉␉type = CT_X48;␊ |
| 172 | ␉␉␉break;␉␉␉␊ |
| 173 | ␉␉␉␉␊ |
| 174 | ␉␉case 0x2a408086:␊ |
| 175 | ␉␉␉type = CT_GM45;␊ |
| 176 | ␉␉␉break;␊ |
| 177 | ␉␉␉␊ |
| 178 | ␉␉␉␊ |
| 179 | ␉␉default:␊ |
| 180 | ␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊ |
| 181 | ␉␉␉{␊ |
| 182 | ␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊ |
| 183 | ␉␉␉␉//getc();␊ |
| 184 | ␉␉␉␉type = CT_UNKWN_INTEL;␊ |
| 185 | ␊ |
| 186 | ␉␉␉}␊ |
| 187 | ␉␉␉type = CT_UNKWN;␊ |
| 188 | ␉␉␉break;␊ |
| 189 | ␉}␊ |
| 190 | ␉return type;␊ |
| 191 | }␊ |
| 192 | ␊ |
| 193 | vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊ |
| 194 | {␊ |
| 195 | ␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊ |
| 196 | ␉return ptr;␊ |
| 197 | }␊ |
| 198 | ␊ |
| 199 | vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊ |
| 200 | {␊ |
| 201 | ␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊ |
| 202 | ␉return ptr;␊ |
| 203 | }␊ |
| 204 | ␊ |
| 205 | vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊ |
| 206 | {␊ |
| 207 | ␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊ |
| 208 | ␉return ptr;␊ |
| 209 | }␊ |
| 210 | ␊ |
| 211 | char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊ |
| 212 | {␊ |
| 213 | ␉UInt32 i;␊ |
| 214 | ␉UInt16 r1, r2;␊ |
| 215 | ␉␊ |
| 216 | ␉r1 = r2 = 32000;␊ |
| 217 | ␉␊ |
| 218 | ␉for (i=0; i < map->mode_table_size; i++)␊ |
| 219 | ␉{␊ |
| 220 | ␉␉if (map->mode_table[i].resolution <= r1)␊ |
| 221 | ␉␉{␊ |
| 222 | ␉␉␉r1 = map->mode_table[i].resolution;␊ |
| 223 | ␉␉}␊ |
| 224 | ␉␉else␊ |
| 225 | ␉␉{␊ |
| 226 | ␉␉␉if (map->mode_table[i].resolution <= r2)␊ |
| 227 | ␉␉␉{␊ |
| 228 | ␉␉␉␉r2 = map->mode_table[i].resolution;␊ |
| 229 | ␉␉␉}␊ |
| 230 | ␉␉}␊ |
| 231 | ␉␉␊ |
| 232 | ␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊ |
| 233 | ␉}␊ |
| 234 | ␉␊ |
| 235 | ␉return (r2-r1-6) % entry_size == 0;␊ |
| 236 | }␊ |
| 237 | ␊ |
| 238 | void close_vbios(vbios_map * map);␊ |
| 239 | ␊ |
| 240 | char detect_ati_bios_type(vbios_map * map)␊ |
| 241 | {␉␊ |
| 242 | ␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊ |
| 243 | }␊ |
| 244 | ␊ |
| 245 | ␊ |
| 246 | vbios_map * open_vbios(chipset_type forced_chipset)␊ |
| 247 | {␊ |
| 248 | ␉UInt32 z;␊ |
| 249 | ␉vbios_map * map = malloc(sizeof(vbios_map));␊ |
| 250 | if (!map) {␊ |
| 251 | return 0;␊ |
| 252 | ␊ |
| 253 | }␊ |
| 254 | ␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊ |
| 255 | ␉/*␊ |
| 256 | ␉ * Determine chipset␊ |
| 257 | ␉ */␊ |
| 258 | ␉␊ |
| 259 | ␉if (forced_chipset == CT_UNKWN)␊ |
| 260 | ␉{␊ |
| 261 | ␉␉map->chipset_id = get_chipset_id();␊ |
| 262 | ␉␉map->chipset = get_chipset(map->chipset_id);␊ |
| 263 | ␉}␊ |
| 264 | ␉else if (forced_chipset != CT_UNKWN)␊ |
| 265 | ␉{␊ |
| 266 | ␉␉map->chipset = forced_chipset;␊ |
| 267 | ␉}␊ |
| 268 | ␉␊ |
| 269 | ␉␊ |
| 270 | ␉if (map->chipset == CT_UNKWN)␊ |
| 271 | ␉{␊ |
| 272 | ␉␉//verbose("Unknown chipset type.\n");␊ |
| 273 | ␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊ |
| 274 | ␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊ |
| 275 | ␉␉close_vbios(map);␊ |
| 276 | ␉␉return 0;␊ |
| 277 | ␉}␊ |
| 278 | ␉␊ |
| 279 | ␉␊ |
| 280 | ␉/*␊ |
| 281 | ␉ * Map the video bios to memory␊ |
| 282 | ␉ */␊ |
| 283 | ␉map->bios_ptr=(char*)VBIOS_START;␊ |
| 284 | ␉␊ |
| 285 | ␉/*␊ |
| 286 | ␉ * check if we have ATI Radeon␊ |
| 287 | ␉ */␊ |
| 288 | ␉map->ati_tables.base = map->bios_ptr;␊ |
| 289 | ␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊ |
| 290 | ␉if (strncmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM", sizeof("ATOM")) == 0)␊ |
| 291 | ␉{␊ |
| 292 | ␉␉// ATI Radeon Card␊ |
| 293 | ␉␉map->bios = BT_ATI_1;␊ |
| 294 | ␉␉␊ |
| 295 | ␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊ |
| 296 | ␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊ |
| 297 | ␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊ |
| 298 | ␉␉␊ |
| 299 | ␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊ |
| 300 | ␉␉if (map->ati_mode_table == 0)␊ |
| 301 | ␉␉{␊ |
| 302 | ␉␉␉printf("Unable to locate the mode table.\n");␊ |
| 303 | ␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
| 304 | ␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
| 305 | ␉␉␉printf("Chipset: %d\n", map->chipset);␊ |
| 306 | ␉␉␉close_vbios(map);␊ |
| 307 | ␉␉␉pause();␊ |
| 308 | ␉␉␉return 0;␊ |
| 309 | ␉␉}␊ |
| 310 | ␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊ |
| 311 | ␉␉␊ |
| 312 | ␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊ |
| 313 | ␉␉␊ |
| 314 | ␉}␊ |
| 315 | ␉else {␊ |
| 316 | ␉␉␊ |
| 317 | ␉␉/*␊ |
| 318 | ␉␉ * check if we have NVIDIA␊ |
| 319 | ␉␉ */␊ |
| 320 | ␊ |
| 321 | ␉␉int i = 0;␊ |
| 322 | ␉␉while (i < 512)␊ |
| 323 | ␉␉{ // we don't need to look through the whole bios, just the firs 512 bytes␊ |
| 324 | ␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊ |
| 325 | ␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊ |
| 326 | ␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊ |
| 327 | ␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊ |
| 328 | ␉␉␉{␊ |
| 329 | ␉␉␉␉map->bios = BT_NVDA;␊ |
| 330 | ␉␉␉␉unsigned short nv_data_table_offset = 0;␊ |
| 331 | ␉␉␉␉unsigned short * nv_data_table;␊ |
| 332 | ␉␉␉␉NV_VESA_TABLE * std_vesa;␊ |
| 333 | ␉␉␉␉␊ |
| 334 | ␉␉␉␉int i = 0;␊ |
| 335 | ␉␉␉␉␊ |
| 336 | ␉␉␉␉while (i < 0x300)␊ |
| 337 | ␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊ |
| 338 | ␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊ |
| 339 | ␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊ |
| 340 | ␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊ |
| 341 | ␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊ |
| 342 | ␉␉␉␉␉{␊ |
| 343 | ␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊ |
| 344 | ␉␉␉␉␉␉break;␊ |
| 345 | ␉␉␉␉␉}␊ |
| 346 | ␉␉␉␉␉i++;␊ |
| 347 | ␉␉␉␉}␊ |
| 348 | ␉␉␉␉␊ |
| 349 | ␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊ |
| 350 | ␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊ |
| 351 | ␉␉␉␉␊ |
| 352 | ␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊ |
| 353 | ␉␉␉␉if (map->nv_mode_table == 0)␊ |
| 354 | ␉␉␉␉{␊ |
| 355 | ␉␉␉␉␉printf("Unable to locate the mode table.\n");␊ |
| 356 | ␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
| 357 | ␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
| 358 | ␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊ |
| 359 | ␉␉␉␉␉close_vbios(map);␊ |
| 360 | ␉␉␉␉␉pause();␊ |
| 361 | ␉␉␉␉␉return 0;␊ |
| 362 | ␉␉␉␉}␊ |
| 363 | ␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊ |
| 364 | ␉␉␉␉␊ |
| 365 | ␉␉␉␉break;␊ |
| 366 | ␉␉␉}␊ |
| 367 | ␉␉␉i++;␊ |
| 368 | ␉␉}␊ |
| 369 | ␉}␊ |
| 370 | ␉␊ |
| 371 | ␉␊ |
| 372 | ␉/*␊ |
| 373 | ␉ * check if we have Intel␊ |
| 374 | ␉ */␊ |
| 375 | ␉␊ |
| 376 | ␉/*if (map->chipset == CT_UNKWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊ |
| 377 | ␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊ |
| 378 | ␉ ␊ |
| 379 | ␉ printf("Chipset Id: %x\n", map->chipset_id);␊ |
| 380 | ␉ ␊ |
| 381 | ␉ printf("Please report this problem to stomljen@yahoo.com\n");␊ |
| 382 | ␉ ␊ |
| 383 | ␉ close_vbios(map);␊ |
| 384 | ␉ return 0;␊ |
| 385 | ␉ }*/␊ |
| 386 | ␉␊ |
| 387 | ␉/*␊ |
| 388 | ␉ * check for others␊ |
| 389 | ␉ */␊ |
| 390 | ␉␊ |
| 391 | ␊ |
| 392 | ␉␊ |
| 393 | ␉/*␊ |
| 394 | ␉ * Figure out where the mode table is ␊ |
| 395 | ␉ */␊ |
| 396 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊ |
| 397 | ␉{␊ |
| 398 | ␉␉char* p = map->bios_ptr + 16;␊ |
| 399 | ␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊ |
| 400 | ␉␉␊ |
| 401 | ␉␉while (p < limit && map->mode_table == 0)␊ |
| 402 | ␉␉{␊ |
| 403 | ␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊ |
| 404 | ␉␉␉␊ |
| 405 | ␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊ |
| 406 | ␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊ |
| 407 | ␉␉␉{␊ |
| 408 | ␉␉␉␉map->mode_table = mode_ptr;␊ |
| 409 | ␉␉␉}␊ |
| 410 | ␉␉␉␊ |
| 411 | ␉␉␉p++;␊ |
| 412 | ␉␉}␊ |
| 413 | ␉␉␊ |
| 414 | ␉␉if (map->mode_table == 0) ␊ |
| 415 | ␉␉{␊ |
| 416 | ␉␉␉close_vbios(map);␊ |
| 417 | ␉␉␉return 0;␊ |
| 418 | ␉␉}␊ |
| 419 | ␉}␊ |
| 420 | ␉␊ |
| 421 | ␉␊ |
| 422 | ␉/*␊ |
| 423 | ␉ * Determine size of mode table␊ |
| 424 | ␉ */␊ |
| 425 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
| 426 | ␉{␊ |
| 427 | ␉␉vbios_mode * mode_ptr = map->mode_table;␊ |
| 428 | ␉␉␊ |
| 429 | ␉␉while (mode_ptr->mode != 0xff)␊ |
| 430 | ␉␉{␊ |
| 431 | ␉␉␉map->mode_table_size++;␊ |
| 432 | ␉␉␉mode_ptr++;␊ |
| 433 | ␉␉}␊ |
| 434 | ␉}␊ |
| 435 | ␉␊ |
| 436 | ␉/*␊ |
| 437 | ␉ * Figure out what type of bios we have␊ |
| 438 | ␉ * order of detection is important␊ |
| 439 | ␉ */␊ |
| 440 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
| 441 | ␉{␊ |
| 442 | ␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊ |
| 443 | ␉␉{␊ |
| 444 | ␉␉␉map->bios = BT_3;␊ |
| 445 | ␉␉}␊ |
| 446 | ␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊ |
| 447 | ␉␉{␊ |
| 448 | ␉␉␉map->bios = BT_2;␊ |
| 449 | ␉␉}␊ |
| 450 | ␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊ |
| 451 | ␉␉{␊ |
| 452 | ␉␉␉map->bios = BT_1;␊ |
| 453 | ␉␉}␊ |
| 454 | ␉␉else {␊ |
| 455 | ␉␉␉return 0;␊ |
| 456 | ␉␉}␊ |
| 457 | ␉}␊ |
| 458 | ␉␊ |
| 459 | ␉return map;␊ |
| 460 | }␊ |
| 461 | ␊ |
| 462 | void close_vbios(vbios_map * map)␊ |
| 463 | {␊ |
| 464 | ␉free(map);␊ |
| 465 | }␊ |
| 466 | ␊ |
| 467 | void unlock_vbios(vbios_map * map)␊ |
| 468 | {␊ |
| 469 | ␉␊ |
| 470 | ␉map->unlocked = TRUE;␊ |
| 471 | ␊ |
| 472 | ␉switch (map->chipset) {␊ |
| 473 | ␉␉case CT_UNKWN:␊ |
| 474 | ␉␉␉break;␊ |
| 475 | ␉␉case CT_830:␊ |
| 476 | ␉␉case CT_855GM:␊ |
| 477 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
| 478 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
| 479 | ␉␉␉␊ |
| 480 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
| 481 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
| 482 | ␉␉␉break;␊ |
| 483 | ␉␉case CT_845G:␊ |
| 484 | ␉␉case CT_865G:␊ |
| 485 | ␉␉case CT_915G:␊ |
| 486 | ␉␉case CT_915GM:␊ |
| 487 | ␉␉case CT_945G:␊ |
| 488 | ␉␉case CT_945GM:␊ |
| 489 | ␉␉case CT_945GME:␊ |
| 490 | ␉␉case CT_946GZ:␊ |
| 491 | ␉␉case CT_G965:␊ |
| 492 | ␉␉case CT_Q965:␊ |
| 493 | ␉␉case CT_965GM:␊ |
| 494 | ␉␉case CT_975X:␊ |
| 495 | ␉␉case CT_P35:␊ |
| 496 | ␉␉case CT_955X:␊ |
| 497 | ␉␉case CT_X48:␊ |
| 498 | ␉␉case CT_B43:␊ |
| 499 | ␉␉case CT_Q45:␊ |
| 500 | ␉␉case CT_P45:␊ |
| 501 | ␉␉case CT_GM45:␊ |
| 502 | ␉␉case CT_G45:␊ |
| 503 | ␉␉case CT_G41:␊ |
| 504 | ␉␉case CT_G31:␊ |
| 505 | ␉␉case CT_500:␊ |
| 506 | ␉␉case CT_3150:␊ |
| 507 | ␉␉case CT_UNKWN_INTEL:␉// Assume newer intel chipset is the same as before␊ |
| 508 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
| 509 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
| 510 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
| 511 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
| 512 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
| 513 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
| 514 | ␉␉␉break;␊ |
| 515 | ␉␉default:␊ |
| 516 | ␉␉␉break;␊ |
| 517 | ␉}␊ |
| 518 | ␉␊ |
| 519 | #if DEBUG␊ |
| 520 | ␉{␊ |
| 521 | ␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
| 522 | ␉␉verbose("unlock PAM: (0x%08x)\n", t);␊ |
| 523 | ␉}␊ |
| 524 | #endif␊ |
| 525 | }␊ |
| 526 | ␊ |
| 527 | void relock_vbios(vbios_map * map)␊ |
| 528 | {␊ |
| 529 | ␉␊ |
| 530 | ␉map->unlocked = FALSE;␊ |
| 531 | ␉␊ |
| 532 | ␉switch (map->chipset)␊ |
| 533 | ␉{␊ |
| 534 | ␉␉case CT_UNKWN:␊ |
| 535 | ␉␉␉break;␊ |
| 536 | ␉␉case CT_830:␊ |
| 537 | ␉␉case CT_855GM:␊ |
| 538 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
| 539 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊ |
| 540 | ␉␉␉break;␊ |
| 541 | ␉␉case CT_845G:␊ |
| 542 | ␉␉case CT_865G:␊ |
| 543 | ␉␉case CT_915G:␊ |
| 544 | ␉␉case CT_915GM:␊ |
| 545 | ␉␉case CT_945G:␊ |
| 546 | ␉␉case CT_945GM:␊ |
| 547 | ␉␉case CT_945GME:␊ |
| 548 | ␉␉case CT_946GZ:␊ |
| 549 | ␉␉case CT_G965:␊ |
| 550 | ␉␉case CT_955X:␊ |
| 551 | ␉␉case CT_G45:␊ |
| 552 | ␉␉case CT_Q965:␊ |
| 553 | ␉␉case CT_965GM:␊ |
| 554 | ␉␉case CT_975X:␊ |
| 555 | ␉␉case CT_P35:␊ |
| 556 | ␉␉case CT_X48:␊ |
| 557 | ␉␉case CT_B43:␊ |
| 558 | ␉␉case CT_Q45:␊ |
| 559 | ␉␉case CT_P45:␊ |
| 560 | ␉␉case CT_GM45:␊ |
| 561 | ␉␉case CT_G41:␊ |
| 562 | ␉␉case CT_G31:␊ |
| 563 | ␉␉case CT_500:␊ |
| 564 | ␉␉case CT_3150:␊ |
| 565 | ␉␉case CT_UNKWN_INTEL:␊ |
| 566 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
| 567 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
| 568 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
| 569 | ␉␉␉break;␊ |
| 570 | ␉␉default:␊ |
| 571 | ␉␉␉break;␊ |
| 572 | ␉}␊ |
| 573 | ␉␊ |
| 574 | #if DEBUG␊ |
| 575 | ␉{␊ |
| 576 | UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
| 577 | ␉␉verbose("relock PAM: (0x%08x)\n", t);␊ |
| 578 | ␉}␊ |
| 579 | #endif␊ |
| 580 | }␊ |
| 581 | ␊ |
| 582 | ␊ |
| 583 | int getMode(edid_mode *mode)␊ |
| 584 | {␊ |
| 585 | ␉char* edidInfo = readEDID();␊ |
| 586 | ␉␉␉␊ |
| 587 | ␉if(!edidInfo) return 1;␊ |
| 588 | ␉␉␊ |
| 589 | ␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊ |
| 590 | ␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊ |
| 591 | ␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊ |
| 592 | ␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊ |
| 593 | ␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊ |
| 594 | ␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊ |
| 595 | ␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊ |
| 596 | ␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊ |
| 597 | ␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊ |
| 598 | ␉␉␊ |
| 599 | ␉␉␊ |
| 600 | ␉free( edidInfo );␊ |
| 601 | ␉␉␊ |
| 602 | ␉if(!mode->h_active) return 1;␊ |
| 603 | ␉␊ |
| 604 | ␉return 0;␊ |
| 605 | ␉␉␊ |
| 606 | }␊ |
| 607 | ␊ |
| 608 | ␊ |
| 609 | static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊ |
| 610 | ␉␉␉␉␉␉unsigned long *clock,␊ |
| 611 | ␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊ |
| 612 | ␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊ |
| 613 | {␊ |
| 614 | ␉UInt32 hbl, vbl, vfreq;␊ |
| 615 | ␉␊ |
| 616 | ␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊ |
| 617 | ␉vfreq = vbl * freq;␊ |
| 618 | ␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊ |
| 619 | ␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊ |
| 620 | ␉␊ |
| 621 | ␉*vsyncstart = y;␊ |
| 622 | ␉*vsyncend = y + 3;␊ |
| 623 | ␉*vblank = vbl - 1;␊ |
| 624 | ␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊ |
| 625 | ␉*hsyncend = x + hbl / 2 - 1;␊ |
| 626 | ␉*hblank = x + hbl - 1;␊ |
| 627 | ␉*clock = (x + hbl) * vfreq / 1000;␊ |
| 628 | }␊ |
| 629 | ␊ |
| 630 | void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊ |
| 631 | ␉UInt32 xprev, yprev;␊ |
| 632 | ␉UInt32 i = 0, j;␊ |
| 633 | ␉// patch first available mode␊ |
| 634 | ␉␊ |
| 635 | ␉//␉for (i=0; i < map->mode_table_size; i++) {␊ |
| 636 | ␉//␉␉if (map->mode_table[0].mode == mode) {␊ |
| 637 | ␉switch(map->bios) {␊ |
| 638 | ␉␉case BT_1:␊ |
| 639 | ␉␉{␊ |
| 640 | ␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊ |
| 641 | ␉␉␉␊ |
| 642 | ␉␉␉if (bp) {␊ |
| 643 | ␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊ |
| 644 | ␉␉␉}␊ |
| 645 | ␉␉␉␊ |
| 646 | ␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊ |
| 647 | ␉␉␉res->x1 = (x & 0xff);␊ |
| 648 | ␉␉␉␊ |
| 649 | ␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊ |
| 650 | ␉␉␉res->y1 = (y & 0xff);␊ |
| 651 | ␉␉␉if (htotal)␊ |
| 652 | ␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊ |
| 653 | ␉␉␉␊ |
| 654 | ␉␉␉if (vtotal)␊ |
| 655 | ␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊ |
| 656 | ␉␉␉␊ |
| 657 | ␉␉␉break;␊ |
| 658 | ␉␉}␊ |
| 659 | ␉␉case BT_2:␊ |
| 660 | ␉␉{␊ |
| 661 | ␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊ |
| 662 | ␉␉␉␊ |
| 663 | ␉␉␉res->xchars = x / 8;␊ |
| 664 | ␉␉␉res->ychars = y / 16 - 1;␊ |
| 665 | ␉␉␉xprev = res->modelines[0].x1;␊ |
| 666 | ␉␉␉yprev = res->modelines[0].y1;␊ |
| 667 | ␉␉␉␊ |
| 668 | ␉␉␉for(j=0; j < 3; j++) {␊ |
| 669 | ␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊ |
| 670 | ␉␉␉␉␊ |
| 671 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
| 672 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
| 673 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
| 674 | ␉␉␉␉␉␊ |
| 675 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
| 676 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
| 677 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
| 678 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
| 679 | ␉␉␉␉␉␊ |
| 680 | ␉␉␉␉␉if (htotal)␊ |
| 681 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
| 682 | ␉␉␉␉␉else␊ |
| 683 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
| 684 | ␉␉␉␉␉␊ |
| 685 | ␉␉␉␉␉if (vtotal)␊ |
| 686 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
| 687 | ␉␉␉␉␉else␊ |
| 688 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
| 689 | ␉␉␉␉}␊ |
| 690 | ␉␉␉}␊ |
| 691 | ␉␉␉break;␊ |
| 692 | ␉␉}␊ |
| 693 | ␉␉case BT_3:␊ |
| 694 | ␉␉{␊ |
| 695 | ␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊ |
| 696 | ␉␉␉␊ |
| 697 | ␉␉␉xprev = res->modelines[0].x1;␊ |
| 698 | ␉␉␉yprev = res->modelines[0].y1;␊ |
| 699 | ␉␉␉␊ |
| 700 | ␉␉␉for (j=0; j < 3; j++) {␊ |
| 701 | ␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊ |
| 702 | ␉␉␉␉␊ |
| 703 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
| 704 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
| 705 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
| 706 | ␉␉␉␉␉␊ |
| 707 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
| 708 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
| 709 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
| 710 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
| 711 | ␉␉␉␉␉if (htotal)␊ |
| 712 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
| 713 | ␉␉␉␉␉else␊ |
| 714 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
| 715 | ␉␉␉␉␉if (vtotal)␊ |
| 716 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
| 717 | ␉␉␉␉␉else␊ |
| 718 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
| 719 | ␉␉␉␉␉␊ |
| 720 | ␉␉␉␉␉modeline->timing_h = y-1;␊ |
| 721 | ␉␉␉␉␉modeline->timing_v = x-1;␊ |
| 722 | ␉␉␉␉}␊ |
| 723 | ␉␉␉}␊ |
| 724 | ␉␉␉break;␊ |
| 725 | ␉␉}␊ |
| 726 | ␉␉case BT_ATI_1:␊ |
| 727 | ␉␉{␊ |
| 728 | ␉␉␉edid_mode mode;␊ |
| 729 | ␉␉␉␉␊ |
| 730 | ␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊ |
| 731 | ␊ |
| 732 | ␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊ |
| 733 | ␉␉␉if (!getMode(&mode)) {␊ |
| 734 | ␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊ |
| 735 | ␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊ |
| 736 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
| 737 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊ |
| 738 | ␉␉␉␉␉␊ |
| 739 | ␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊ |
| 740 | ␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊ |
| 741 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
| 742 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊ |
| 743 | ␊ |
| 744 | ␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊ |
| 745 | ␉␉␉}␊ |
| 746 | ␉␉␉/*else␊ |
| 747 | ␉␉␉{␊ |
| 748 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
| 749 | ␊ |
| 750 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
| 751 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
| 752 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
| 753 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
| 754 | ␊ |
| 755 | ␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊ |
| 756 | ␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊ |
| 757 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊ |
| 758 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
| 759 | ␊ |
| 760 | ␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊ |
| 761 | ␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊ |
| 762 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊ |
| 763 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊ |
| 764 | ␉␉␉␉␉␉␉␉␉␉␉␉␊ |
| 765 | ␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊ |
| 766 | ␉␉␉ }*/␊ |
| 767 | ␉␊ |
| 768 | ␉␉␉break;␊ |
| 769 | ␉␉}␊ |
| 770 | ␉␉case BT_ATI_2:␊ |
| 771 | ␉␉{␊ |
| 772 | ␉␉␉edid_mode mode;␊ |
| 773 | ␉␉␉␉␉␉␊ |
| 774 | ␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊ |
| 775 | ␉␉␉␊ |
| 776 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
| 777 | ␉␉␉if (!getMode(&mode)) {␊ |
| 778 | ␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊ |
| 779 | ␉␉␉␉mode_timing->usHActive = mode.h_active;␊ |
| 780 | ␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊ |
| 781 | ␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊ |
| 782 | ␉␉␉␉␉␉␉␉␉␉␊ |
| 783 | ␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊ |
| 784 | ␉␉␉␉mode_timing->usVActive = mode.v_active;␊ |
| 785 | ␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊ |
| 786 | ␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊ |
| 787 | ␉␉␉␉␉␉␉␉␉␉␊ |
| 788 | ␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊ |
| 789 | ␉␉␉}␊ |
| 790 | ␉␉␉/*else␊ |
| 791 | ␉␉␉{␊ |
| 792 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
| 793 | ␉␉␉␊ |
| 794 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
| 795 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
| 796 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
| 797 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
| 798 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
| 799 | ␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊ |
| 800 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊ |
| 801 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊ |
| 802 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
| 803 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
| 804 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊ |
| 805 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊ |
| 806 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊ |
| 807 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
| 808 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
| 809 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊ |
| 810 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊ |
| 811 | ␉␉␉␉␊ |
| 812 | ␉␉␉␊ |
| 813 | ␉␉␉break;␊ |
| 814 | ␉␉}␊ |
| 815 | ␉␉case BT_NVDA:␊ |
| 816 | ␉␉{␊ |
| 817 | ␉␉␉edid_mode mode;␊ |
| 818 | ␉␉␉␊ |
| 819 | ␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊ |
| 820 | ␉␉␉␊ |
| 821 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
| 822 | ␉␉␉if (!getMode(&mode)) {␊ |
| 823 | ␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊ |
| 824 | ␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊ |
| 825 | ␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
| 826 | ␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊ |
| 827 | ␉␉␉␉␊ |
| 828 | ␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊ |
| 829 | ␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊ |
| 830 | ␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
| 831 | ␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊ |
| 832 | ␉␉␉␉␊ |
| 833 | ␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊ |
| 834 | ␉␉␉}␊ |
| 835 | ␉␉␉/*else␊ |
| 836 | ␉␉␉ {␊ |
| 837 | ␉␉␉ vbios_modeline_type2 modeline;␊ |
| 838 | ␉␉␉ ␊ |
| 839 | ␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
| 840 | ␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊ |
| 841 | ␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊ |
| 842 | ␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊ |
| 843 | ␉␉␉ ␊ |
| 844 | ␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊ |
| 845 | ␉␉␉ mode_timing[i].usH_Active = x;␊ |
| 846 | ␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊ |
| 847 | ␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊ |
| 848 | ␉␉␉ ␊ |
| 849 | ␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊ |
| 850 | ␉␉␉ mode_timing[i].usV_Active = y;␊ |
| 851 | ␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊ |
| 852 | ␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊ |
| 853 | ␉␉␉ ␊ |
| 854 | ␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊ |
| 855 | ␉␉␉ }*/␊ |
| 856 | ␉␉␉break;␊ |
| 857 | ␉␉}␊ |
| 858 | ␉␉case BT_UNKWN:␊ |
| 859 | ␉␉{␊ |
| 860 | ␉␉␉break;␊ |
| 861 | ␉␉}␊ |
| 862 | ␉␉default:␊ |
| 863 | ␉␉␉break;␊ |
| 864 | ␉}␊ |
| 865 | ␉//␉␉}␊ |
| 866 | ␉//␉}␊ |
| 867 | }␊ |
| 868 | |
