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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#ifndef __LIBSAIO_CPU_H␊
7#define __LIBSAIO_CPU_H␊
8␊
9#include "platform.h"␊
10␊
11extern void scan_cpu(PlatformInfo_t *);␊
12␊
13#define bit(n)␉␉␉(1ULL << (n))␊
14#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
15#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
16␊
17#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
18␊
19#define MSR_IA32_PLATFORM_ID 0x17␊
20#define␉MSR_IA32_PERF_STATUS 0x198␊
21#define MSR_IA32_PERF_CONTROL 0x199␊
22#define MSR_IA32_EXT_CONFIG 0xEE␊
23#define MSR_FLEX_RATIO 0x194␊
24#define MSR_TURBO_RATIO_LIMIT 0x1AD␊
25#define␉MSR_PLATFORM_INFO 0xCE␊
26#define MSR_CORE_THREAD_COUNT 0x35␉␉␉// Undocumented␊
27␊
28#define K8_FIDVID_STATUS 0xC0010042␊
29#define K10_COFVID_STATUS 0xC0010071␊
30␊
31#define MSR_AMD_MPERF 0x000000E7␊
32#define MSR_AMD_APERF 0x000000E8␊
33␊
34#define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊
35␊
36// DFE: This constant comes from older xnu:␊
37#define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊
38␊
39// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊
40#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
41#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
42␊
43// CPUID Values␊
44␊
45#define CPUID_MODEL_PRESCOTT␉␉3 // 0x03 Celeron D, Pentium 4 (90nm)␊
46#define CPUID_MODEL_NOCONA␉␉4 // 0x04 Xeon Nocona, Irwindale (90nm)␊
47#define CPUID_MODEL_PRESLER␉␉6 // 0x06 Pentium 4, Pentium D (65nm)␊
48#define CPUID_MODEL_PENTIUM_M␉␉9 // 0x09␊
49#define CPUID_MODEL_DOTHAN␉␉13 // 0x0D Dothan␊
50#define CPUID_MODEL_YONAH␉␉14 // 0x0E Intel Mobile Core Solo, Duo␊
51#define CPUID_MODEL_MEROM␉␉15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
52#define CPUID_MODEL_CONROE␉␉15 // 0x0F␊
53#define CPUID_MODEL_CELERON␉␉22 // 0x16␊
54#define CPUID_MODEL_PENRYN␉␉23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
55#define CPUID_MODEL_WOLFDALE␉␉23 // 0x17␊
56#define CPUID_MODEL_NEHALEM␉␉26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
57#define CPUID_MODEL_ATOM␉␉28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne␊
58#define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊
59#define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊
60#define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊
61#define CPUID_MODEL_CLARKDALE␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
62#define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊
63#define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊
64#define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊
65#define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
66#define CPUID_MODEL_JAKETOWN␉␉45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
67#define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
68#define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊
69#define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊
70#define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊
71#define CPUID_MODEL_HASWELL␉␉60 // 0x3C␊
72#define CPUID_MODEL_IVY_BRIDGE_E5␉62 // 0x3E␊
73␊
74static inline uint64_t rdtsc64(void)␊
75{␊
76␉uint64_t ret;␊
77␉__asm__ volatile("rdtsc" : "=A" (ret));␊
78␉return ret;␊
79}␊
80␊
81static inline uint64_t rdmsr64(uint32_t msr)␊
82{␊
83 uint64_t ret;␊
84 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊
85 return ret;␊
86}␊
87␊
88static inline void wrmsr64(uint32_t msr, uint64_t val)␊
89{␊
90␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊
91}␊
92␊
93static inline void intel_waitforsts(void) {␊
94␉uint32_t inline_timeout = 100000;␊
95␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊
96}␊
97␊
98static inline void do_cpuid(uint32_t selector, uint32_t *data)␊
99{␊
100␉asm volatile ("cpuid"␊
101␉␉␉␉ : "=a" (data[0]),␊
102␉␉␉␉ "=b" (data[1]),␊
103␉␉␉␉ "=c" (data[2]),␊
104␉␉␉␉ "=d" (data[3])␊
105␉␉␉␉ : "a" (selector));␊
106}␊
107␊
108static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊
109{␊
110␉asm volatile ("cpuid"␊
111␉␉␉␉ : "=a" (data[0]),␊
112␉␉␉␉ "=b" (data[1]),␊
113␉␉␉␉ "=c" (data[2]),␊
114␉␉␉␉ "=d" (data[3])␊
115␉␉␉␉ : "a" (selector), "c" (selector2));␊
116}␊
117␊
118// DFE: enable_PIT2 and disable_PIT2 come from older xnu␊
119␊
120/*␊
121 * Enable or disable timer 2.␊
122 * Port 0x61 controls timer 2:␊
123 * bit 0 gates the clock,␊
124 * bit 1 gates output to speaker.␊
125 */␊
126static inline void enable_PIT2(void)␊
127{␊
128 /* Enable gate, disable speaker */␊
129 __asm__ volatile(␊
130␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
131␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊
132␉␉␉␉␉ " or $1,%%al \n\t"␊
133␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
134␉␉␉␉␉ : : : "%al" );␊
135}␊
136␊
137static inline void disable_PIT2(void)␊
138{␊
139 /* Disable gate and output to speaker */␊
140 __asm__ volatile(␊
141␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
142␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊
143␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
144␉␉␉␉␉ : : : "%al" );␊
145}␊
146␊
147// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊
148// roughly based on Linux code␊
149␊
150/* Set the 8254 channel 2 to mode 0 with the specified value.␊
151 In mode 0, the counter will initially set its gate low when the␊
152 timer expires. For this to be useful, you ought to set it high␊
153 before calling this function. The enable_PIT2 function does this.␊
154 */␊
155static inline void set_PIT2_mode0(uint16_t value)␊
156{␊
157 __asm__ volatile(␊
158␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊
159␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊
160␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊
161␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊
162␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊
163␉␉␉␉␉ " outb␉%%al,$0x42"␊
164␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊
165}␊
166␊
167/* Returns the number of times the loop ran before the PIT2 signaled */␊
168static inline unsigned long poll_PIT2_gate(void)␊
169{␊
170 unsigned long count = 0;␊
171 unsigned char nmi_sc_val;␊
172 do {␊
173 ++count;␊
174 __asm__ volatile(␊
175␉␉␉␉␉␉ "inb␉$0x61,%0"␊
176␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊
177 } while( (nmi_sc_val & 0x20) == 0);␊
178 return count;␊
179}␊
180␊
181inline static void␊
182set_PIT2(int value)␊
183{␊
184/*␊
185 * First, tell the clock we are going to write 16 bits to the counter␊
186 * and enable one-shot mode (command 0xB8 to port 0x43)␊
187 * Then write the two bytes into the PIT2 clock register (port 0x42).␊
188 * Loop until the value is "realized" in the clock,␊
189 * this happens on the next tick.␊
190 */␊
191 asm volatile(␊
192 " movb $0xB8,%%al \n\t"␊
193 " outb %%al,$0x43 \n\t"␊
194 " movb %%dl,%%al \n\t"␊
195 " outb %%al,$0x42 \n\t"␊
196 " movb %%dh,%%al \n\t"␊
197 " outb %%al,$0x42 \n"␊
198"1: inb $0x42,%%al \n\t" ␊
199 " inb $0x42,%%al \n\t"␊
200 " cmp %%al,%%dh \n\t"␊
201 " jne 1b"␊
202 : : "d"(value) : "%al");␊
203}␊
204␊
205␊
206inline static uint64_t␊
207get_PIT2(unsigned int *value)␊
208{␊
209 register uint64_t result;␊
210/*␊
211 * This routine first latches the time (command 0x80 to port 0x43),␊
212 * then gets the time stamp so we know how long the read will take later.␊
213 * Read (from port 0x42) and return the current value of the timer.␊
214 */␊
215#ifdef __i386__␊
216 asm volatile(␊
217 " xorl %%ecx,%%ecx \n\t"␊
218 " movb $0x80,%%al \n\t"␊
219 " outb %%al,$0x43 \n\t"␊
220 " rdtsc \n\t"␊
221 " pushl %%eax \n\t"␊
222 " inb $0x42,%%al \n\t"␊
223 " movb %%al,%%cl \n\t"␊
224 " inb $0x42,%%al \n\t"␊
225 " movb %%al,%%ch \n\t"␊
226 " popl %%eax "␊
227 : "=A"(result), "=c"(*value));␊
228#else /* __x86_64__ */␊
229 asm volatile(␊
230␉␉" xorq %%rcx,%%rcx \n\t"␊
231␉␉" movb $0x80,%%al \n\t"␊
232␉␉" outb %%al,$0x43 \n\t"␊
233␉␉" rdtsc \n\t"␊
234␉␉" pushq %%rax \n\t"␊
235␉␉" inb $0x42,%%al \n\t"␊
236␉␉" movb %%al,%%cl \n\t"␊
237␉␉" inb $0x42,%%al \n\t"␊
238␉␉" movb %%al,%%ch \n\t"␊
239␉␉" popq %%rax "␊
240␉␉: "=A"(result), "=c"(*value));␊
241#endif␊
242␊
243 return result;␊
244}␊
245␊
246#endif /* !__LIBSAIO_CPU_H */␊
247

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