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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊
36␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
37␉␉␉␉␉␉value->word = 0;␊
38␉␉␉␉␉␉break;␊
39␉␉␉␉␉default:␊
40␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
41␉␉␉␉}␊
42␉␉␉}␊
43␉␉␉␉break;␊
44␊
45␉␉␉default:␊
46␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
47␉␉}␊
48␉}␊
49␉else␊
50␉{␊
51␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
52␉}␊
53␊
54␉return true;␊
55}␊
56␊
57bool getProcessorInformationMaximumClock(returnType *value)␊
58{␊
59␉value->word = Platform.CPU.CPUFrequency/1000000;␊
60␉return true;␊
61}␊
62␊
63bool getSMBOemProcessorBusSpeed(returnType *value)␊
64{␊
65␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
66␉{␉␉␊
67␉␉switch (Platform.CPU.Family) ␊
68␉␉{␊
69␉␉␉case 0x06:␊
70␉␉␉{␊
71␉␉␉␉switch (Platform.CPU.Model)␊
72␉␉␉␉{␊
73␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
74␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
75␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
76␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
77␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
78␉␉␉␉␉␉return false;␊
79␊
80␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_DALES:␊
83␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
84␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
86␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
87␉␉␉␉␉{␊
88␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
89␉␉␉␉␉␉int nhm_bus = 0x3F;␊
90␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
91␉␉␉␉␉␉unsigned long did, vid;␊
92␉␉␉␉␉␉int i;␊
93␉␉␉␉␉␉␊
94␉␉␉␉␉␉// Nehalem supports Scrubbing␊
95␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
96␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
97␉␉␉␉␉␉{␊
98␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
99␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
100␉␉␉␉␉␉␉vid &= 0xFFFF;␊
101␉␉␉␉␉␉␉did &= 0xFF00;␊
102␉␉␉␉␉␉␉␊
103␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
104␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
105␉␉␉␉␉␉}␊
106␉␉␉␉␉␉␊
107␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
108␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
109␉␉␉␉␉␉qpimult &= 0x7F;␊
110␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
111␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
112␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
113␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
114␉␉␉␉␉␉{␊
115␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
116␉␉␉␉␉␉}␊
117␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
118␉␉␉␉␉␉value->word = qpibusspeed;␊
119␉␉␉␉␉␉return true;␊
120␉␉␉␉␉}␊
121␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
122␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
123␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊
124␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
125␉␉␉␉␉{␊
126␉␉␉␉␉␉int busspeed;␊
127␉␉␉␉␉␉busspeed = 100;␊
128␉␉␉␉␉␉value->word = busspeed;␊
129␉␉␉␉␉␉return true;␊
130␉␉␉␉␉}␊
131␉␉␉␉}␊
132␉␉␉}␊
133␉␉}␊
134␉}␊
135␉return false;␊
136}␊
137␊
138uint16_t simpleGetSMBOemProcessorType(void)␊
139{␊
140␉if (Platform.CPU.NoCores >= 4) ␊
141␉{␊
142␉␉return 0x0501;␉// Quad-Core Xeon␊
143␉}␊
144␉else if (Platform.CPU.NoCores == 1) ␊
145␉{␊
146␉␉return 0x0201;␉// Core Solo␊
147␉};␊
148␉␊
149␉return 0x0301;␉␉// Core 2 Duo␊
150}␊
151␊
152bool getSMBOemProcessorType(returnType *value)␊
153{␊
154␉static bool done = false;␉␉␊
155␊
156␉value->word = simpleGetSMBOemProcessorType();␊
157␊
158␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
159␉{␊
160␉␉if (!done)␊
161␉␉{␊
162␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
163␉␉␉done = true;␊
164␉␉}␊
165␊
166␉␉switch (Platform.CPU.Family) ␊
167␉␉{␊
168␉␉␉case 0x06:␊
169␉␉␉{␊
170␉␉␉␉switch (Platform.CPU.Model)␊
171␉␉␉␉{␊
172␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
173␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
174␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
175␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
176␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
177␉␉␉␉␉␉return true;␊
178␊
179␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
180␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
181␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
182␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
183␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
184␉␉␉␉␉␉{␊
185␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
186␉␉␉␉␉␉}␊
187␉␉␉␉␉␉else␊
188␉␉␉␉␉␉{␊
189␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
190␉␉␉␉␉␉}␊
191␉␉␉␉␉␉return true;␊
192␊
193␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
194␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
195␉␉␉␉␉␉{␊
196␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
197␉␉␉␉␉␉}␊
198␉␉␉␉␉␉else␊
199␉␉␉␉␉␉{␊
200␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
201␉␉␉␉␉␉␉{␊
202␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
203␉␉␉␉␉␉␉}␊
204␉␉␉␉␉␉␉else␊
205␉␉␉␉␉␉␉{␊
206␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
207␉␉␉␉␉␉␉}␊
208␉␉␉␉␉␉}␊
209␉␉␉␉␉␉return true;␊
210␊
211␉␉␉␉␉case CPU_MODEL_DALES:␊
212␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
213␉␉␉␉␉␉{␊
214␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
215␉␉␉␉␉␉}␊
216␉␉␉␉␉␉else␊
217␉␉␉␉␉␉{␊
218␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
219␉␉␉␉␉␉}␊
220␉␉␉␉␉␉return true;␊
221␊
222␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7, Xeon E3-12xx LGA1155 (32nm)␊
223␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
224␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊
225␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
226␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
227␉␉␉␉␉␉{␊
228␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
229␉␉␉␉␉␉}␊
230␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
231␉␉␉␉␉␉{␊
232␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉// Core i3␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
235␉␉␉␉␉␉{␊
236␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉else␊
239␉␉␉␉␉␉{␊
240␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉return true;␊
243␉␉␉␉}␊
244␉␉␉}␊
245␉␉}␊
246␉}␊
247␉␊
248␉return false;␊
249}␊
250␊
251bool getSMBMemoryDeviceMemoryType(returnType *value)␊
252{␊
253␉static int idx = -1;␊
254␉int␉map;␊
255␊
256␉idx++;␊
257␉if (idx < MAX_RAM_SLOTS)␊
258␉{␊
259␉␉map = Platform.DMI.DIMM[idx];␊
260␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
261␉␉{␊
262␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
263␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
264␉␉␉return true;␊
265␉␉}␊
266␉}␊
267␉␊
268␉return false;␊
269//␉value->byte = SMB_MEM_TYPE_DDR2;␊
270//␉return true;␊
271}␊
272␊
273bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
274{␊
275 value->word = 0xFFFF;␊
276 return true;␊
277}␊
278␊
279bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
280{␊
281␉static int idx = -1;␊
282␉int␉map;␊
283␊
284␉idx++;␊
285␉if (idx < MAX_RAM_SLOTS)␊
286␉{␊
287␉␉map = Platform.DMI.DIMM[idx];␊
288␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
289␉␉{␊
290␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
291␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
292␉␉␉return true;␊
293␉␉}␊
294␉}␊
295␊
296␉return false;␊
297//␉value->dword = 800;␊
298//␉return true;␊
299}␊
300␊
301bool getSMBMemoryDeviceManufacturer(returnType *value)␊
302{␊
303␉static int idx = -1;␊
304␉int␉map;␊
305␊
306␉idx++;␊
307␉if (idx < MAX_RAM_SLOTS)␊
308␉{␊
309␉␉map = Platform.DMI.DIMM[idx];␊
310␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
311␉␉{␊
312␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
313␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
314␉␉␉return true;␊
315␉␉}␊
316␉}␊
317␊
318␉if (!bootInfo->memDetect)␊
319␉{␊
320␉␉return false;␊
321␉}␊
322␉value->string = NOT_AVAILABLE;␊
323␉return true;␊
324}␊
325␉␊
326bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
327{␊
328␉static int idx = -1;␊
329␉int␉map;␊
330␊
331␉idx++;␊
332␊
333 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
334␊
335␉if (idx < MAX_RAM_SLOTS)␊
336␉{␊
337␉␉map = Platform.DMI.DIMM[idx];␊
338␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
339␉␉{␊
340␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
341␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
342␉␉␉return true;␊
343␉␉}␊
344␉}␊
345␊
346␉if (!bootInfo->memDetect)␊
347␉{␊
348␉␉return false;␊
349␉}␊
350␉value->string = NOT_AVAILABLE;␊
351␉return true;␊
352}␊
353␊
354bool getSMBMemoryDevicePartNumber(returnType *value)␊
355{␊
356␉static int idx = -1;␊
357␉int␉map;␊
358␊
359␉idx++;␊
360␉if (idx < MAX_RAM_SLOTS)␊
361␉{␊
362␉␉map = Platform.DMI.DIMM[idx];␊
363␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
364␉␉{␊
365␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
366␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
367␉␉␉return true;␊
368␉␉}␊
369␉}␊
370␊
371␉if (!bootInfo->memDetect)␊
372␉{␊
373␉␉return false;␊
374␉}␊
375␉value->string = NOT_AVAILABLE;␊
376␉return true;␊
377}␊
378␊
379␊
380// getting smbios addr with fast compare ops, late checksum testing ...␊
381#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
382static const char * const SMTAG = "_SM_";␊
383static const char* const DMITAG = "_DMI_";␊
384␊
385SMBEntryPoint *getAddressOfSmbiosTable(void)␊
386{␊
387␉SMBEntryPoint␉*smbios;␊
388␉/* ␊
389␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
390␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
391␉ */␊
392␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
393␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
394␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
395␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
396␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
397␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
398␉ {␊
399␉␉␉return smbios;␊
400␉ }␊
401␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
402␉}␊
403␉printf("ERROR: Unable to find SMBIOS!\n");␊
404␉pause();␊
405␉return NULL;␊
406}␊
407␊
408

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