| 1 | /*␊ |
| 2 | *␉NVidia injector␊ |
| 3 | *␊ |
| 4 | *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊ |
| 5 | *␊ |
| 6 | *␉NVidia injector modified by Fabio (ErmaC) on May 2012,␊ |
| 7 | *␉for allow the cosmetics injection also based on SubVendorID and SubDeviceID.␊ |
| 8 | *␊ |
| 9 | *␉NVidia injector is free software: you can redistribute it and/or modify␊ |
| 10 | *␉it under the terms of the GNU General Public License as published by␊ |
| 11 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
| 12 | *␉(at your option) any later version.␊ |
| 13 | *␊ |
| 14 | *␉NVidia driver and injector is distributed in the hope that it will be useful,␊ |
| 15 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 16 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 17 | *␉GNU General Public License for more details.␊ |
| 18 | *␊ |
| 19 | *␉You should have received a copy of the GNU General Public License␊ |
| 20 | *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊ |
| 21 | *␊ |
| 22 | *␉Alternatively you can choose to comply with APSL␊ |
| 23 | *␊ |
| 24 | *␉DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
| 25 | *␊ |
| 26 | *␊ |
| 27 | *␉Copyright 2005-2006 Erik Waling␊ |
| 28 | *␉Copyright 2006 Stephane Marchesin␊ |
| 29 | *␉Copyright 2007-2009 Stuart Bennett␊ |
| 30 | *␊ |
| 31 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
| 32 | *␉copy of this software and associated documentation files (the "Software"),␊ |
| 33 | *␉to deal in the Software without restriction, including without limitation␊ |
| 34 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
| 35 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
| 36 | *␉Software is furnished to do so, subject to the following conditions:␊ |
| 37 | *␊ |
| 38 | *␉The above copyright notice and this permission notice shall be included in␊ |
| 39 | *␉all copies or substantial portions of the Software.␊ |
| 40 | *␊ |
| 41 | *␉THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
| 42 | *␉IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
| 43 | *␉FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
| 44 | *␉THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
| 45 | *␉WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
| 46 | *␉OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
| 47 | *␉SOFTWARE.␊ |
| 48 | */␊ |
| 49 | ␊ |
| 50 | #ifndef __LIBSAIO_NVIDIA_H␊ |
| 51 | #define __LIBSAIO_NVIDIA_H␊ |
| 52 | ␊ |
| 53 | struct nvidia_pci_info_t;␊ |
| 54 | ␊ |
| 55 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev);␊ |
| 56 | ␊ |
| 57 | typedef struct {␊ |
| 58 | ␉uint32_t device; // VendorID + DeviceID␊ |
| 59 | ␉char *name;␊ |
| 60 | } nvidia_pci_info_t;␊ |
| 61 | ␊ |
| 62 | struct nvidia_card_info_t;␊ |
| 63 | ␊ |
| 64 | typedef struct {␊ |
| 65 | ␉uint32_t device; // VendorID + DeviceID␊ |
| 66 | ␉uint32_t subdev; // SubdeviceID + SubvendorID␊ |
| 67 | ␉char *name;␊ |
| 68 | ␉//bool kEnableHDMIAudio //␉HDMi␊ |
| 69 | ␉//VRAM␊ |
| 70 | } nvidia_card_info_t;␊ |
| 71 | ␊ |
| 72 | #define DCB_MAX_NUM_ENTRIES 16␊ |
| 73 | #define DCB_MAX_NUM_I2C_ENTRIES 16␊ |
| 74 | ␊ |
| 75 | #define DCB_LOC_ON_CHIP 0␊ |
| 76 | ␊ |
| 77 | struct bios␊ |
| 78 | {␊ |
| 79 | ␉uint16_t␉signature;␉␉/* 0x55AA */␊ |
| 80 | ␉uint8_t␉␉size;␉␉␉/* Size in multiples of 512 */␊ |
| 81 | };␊ |
| 82 | ␊ |
| 83 | #define NVIDIA_ROM_SIZE␉␉␉␉0x20000␊ |
| 84 | #define PATCH_ROM_SUCCESS␉␉␉1␊ |
| 85 | #define PATCH_ROM_SUCCESS_HAS_LVDS␉␉2␊ |
| 86 | #define PATCH_ROM_FAILED␉␉␉0␊ |
| 87 | #define MAX_NUM_DCB_ENTRIES␉␉␉16␊ |
| 88 | #define TYPE_GROUPED␉␉␉␉0xff␊ |
| 89 | #define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊ |
| 90 | #define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊ |
| 91 | #define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊ |
| 92 | #define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊ |
| 93 | #define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊ |
| 94 | ␊ |
| 95 | #define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊ |
| 96 | #define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊ |
| 97 | #define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊ |
| 98 | #define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊ |
| 99 | ␊ |
| 100 | #define NV_PMC_OFFSET␉␉␉␉␉␉␉0x000000␊ |
| 101 | #define NV_PMC_SIZE␉␉␉␉␉␉␉0x2ffff␊ |
| 102 | #define NV_PDISPLAY_OFFSET␉␉␉␉␉␉0x610000␊ |
| 103 | #define NV_PDISPLAY_SIZE␉␉␉␉␉␉0x10000␊ |
| 104 | ␊ |
| 105 | #define NV_PROM_OFFSET␉␉␉␉␉␉␉0x300000␊ |
| 106 | #define NV_PROM_SIZE␉␉␉␉␉␉␉0x0001ffff␊ |
| 107 | #define NV_PRAMIN_OFFSET␉␉␉␉␉␉0x00700000␊ |
| 108 | #define NV_PRAMIN_SIZE␉␉␉␉␉␉␉0x00100000␊ |
| 109 | #define NV04_PFB_FIFO_DATA␉␉␉␉␉␉0x0010020c␊ |
| 110 | #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK␉␉␉␉0xfff00000␊ |
| 111 | #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT␉␉␉␉20␊ |
| 112 | #define NVC0_MEM_CTRLR_COUNT␉␉␉␉␉␉0x00121c74␊ |
| 113 | #define NVC0_MEM_CTRLR_RAM_AMOUNT␉␉␉␉␉0x0010f20c␊ |
| 114 | ␊ |
| 115 | #define NV_PBUS_PCI_NV_20␉␉␉␉␉␉0x00001850␊ |
| 116 | #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED␉(0 << 0)␊ |
| 117 | #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED␉(1 << 0)␊ |
| 118 | ␊ |
| 119 | #define REG8(reg) ((volatile uint8_t *)regs)[(reg)]␊ |
| 120 | #define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]␊ |
| 121 | #define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]␊ |
| 122 | ␊ |
| 123 | #define NV_ARCH_03 0x03␊ |
| 124 | #define NV_ARCH_04 0x04␊ |
| 125 | #define NV_ARCH_10 0x10␊ |
| 126 | #define NV_ARCH_20 0x20␊ |
| 127 | #define NV_ARCH_30 0x30␊ |
| 128 | #define NV_ARCH_40 0x40␊ |
| 129 | #define NV_ARCH_50 0x50␊ |
| 130 | #define NV_ARCH_C0 0xC0␊ |
| 131 | ␊ |
| 132 | #define CHIPSET_NV03 0x0010␊ |
| 133 | #define CHIPSET_NV04 0x0020␊ |
| 134 | #define CHIPSET_NV10 0x0100␊ |
| 135 | #define CHIPSET_NV11 0x0110␊ |
| 136 | #define CHIPSET_NV15 0x0150␊ |
| 137 | #define CHIPSET_NV17 0x0170␊ |
| 138 | #define CHIPSET_NV18 0x0180␊ |
| 139 | #define CHIPSET_NFORCE 0x01A0␊ |
| 140 | #define CHIPSET_NFORCE2 0x01F0␊ |
| 141 | #define CHIPSET_NV20 0x0200␊ |
| 142 | #define CHIPSET_NV25 0x0250␊ |
| 143 | #define CHIPSET_NV28 0x0280␊ |
| 144 | #define CHIPSET_NV30 0x0300␊ |
| 145 | #define CHIPSET_NV31 0x0310␊ |
| 146 | #define CHIPSET_NV34 0x0320␊ |
| 147 | #define CHIPSET_NV35 0x0330␊ |
| 148 | #define CHIPSET_NV36 0x0340␊ |
| 149 | #define CHIPSET_NV40 0x0040␊ |
| 150 | #define CHIPSET_NV41 0x00C0␊ |
| 151 | #define CHIPSET_NV43 0x0140␊ |
| 152 | #define CHIPSET_NV44 0x0160␊ |
| 153 | #define CHIPSET_NV44A 0x0220␊ |
| 154 | #define CHIPSET_NV45 0x0210␊ |
| 155 | #define CHIPSET_NV50 0x0190␊ |
| 156 | #define CHIPSET_NV84 0x0400␊ |
| 157 | #define CHIPSET_MISC_BRIDGED 0x00F0␊ |
| 158 | #define CHIPSET_G70 0x0090␊ |
| 159 | #define CHIPSET_G71 0x0290␊ |
| 160 | #define CHIPSET_G72 0x01D0␊ |
| 161 | #define CHIPSET_G73 0x0390␊ |
| 162 | ␊ |
| 163 | // integrated GeForces (6100, 6150)␊ |
| 164 | #define CHIPSET_C51 0x0240␊ |
| 165 | ␊ |
| 166 | // variant of C51, seems based on a G70 design␊ |
| 167 | #define CHIPSET_C512 0x03D0␊ |
| 168 | #define CHIPSET_G73_BRIDGED 0x02E0␊ |
| 169 | ␊ |
| 170 | extern uint8_t default_NVCAP[];␊ |
| 171 | extern uint8_t default_NVPM[];␊ |
| 172 | extern uint8_t default_dcfg_0[];␊ |
| 173 | extern uint8_t default_dcfg_1[];␊ |
| 174 | ␊ |
| 175 | #endif /* !__LIBSAIO_NVIDIA_H */␊ |
| 176 | |
