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1/*␊
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and␊
3 * VA Linux Systems Inc., Fremont, California.␊
4 *␊
5 * All Rights Reserved.␊
6 *␊
7 * Permission is hereby granted, free of charge, to any person obtaining␊
8 * a copy of this software and associated documentation files (the␊
9 * "Software"), to deal in the Software without restriction, including␊
10 * without limitation on the rights to use, copy, modify, merge,␊
11 * publish, distribute, sublicense, and/or sell copies of the Software,␊
12 * and to permit persons to whom the Software is furnished to do so,␊
13 * subject to the following conditions:␊
14 *␊
15 * The above copyright notice and this permission notice (including the␊
16 * next paragraph) shall be included in all copies or substantial␊
17 * portions of the Software.␊
18 *␊
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,␊
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF␊
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND␊
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR␊
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,␊
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER␊
26 * DEALINGS IN THE SOFTWARE.␊
27 */␊
28␊
29/*␊
30 * Authors:␊
31 * Kevin E. Martin <martin@xfree86.org>␊
32 * Rickard E. Faith <faith@valinux.com>␊
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>␊
34 *␊
35 * References:␊
36 *␊
37 * !!!! FIXME !!!!␊
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical␊
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April␊
40 * 1999.␊
41 *␊
42 * !!!! FIXME !!!!␊
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N␊
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.␊
45 *␊
46 */␊
47␊
48/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h␊
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT␊
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */␊
51␊
52#ifndef _ATI_REG_H_␊
53#define _ATI_REG_H_␊
54␊
55␊
56#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e␊
57#define DATVAL(x)␉␉␉{kPtr, sizeof(x), (uint8_t *)x}␊
58#define STRVAL(x)␉␉␉{kStr, sizeof(x)-1, (uint8_t *)x}␊
59#define BYTVAL(x)␉␉␉{kCst, 1, (uint8_t *)x}␊
60#define WRDVAL(x)␉␉␉{kCst, 2, (uint8_t *)x}␊
61#define DWRVAL(x)␉␉␉{kCst, 4, (uint8_t *)x}␊
62//#define QWRVAL(x)␉␉␉{kCst, 8, (uint8_t *)x}␊
63#define NULVAL␉␉␉␉{kNul, 0, (uint8_t *)NULL}␊
64␊
65typedef enum {␊
66␉kNul,␊
67␉kStr,␊
68␉kPtr,␊
69␉kCst␊
70} type_t;␊
71␊
72typedef enum {␊
73␉CHIP_FAMILY_UNKNOW,␊
74␉/* Old */␊
75␉CHIP_FAMILY_R420,␊
76␉CHIP_FAMILY_RV410,␊
77␉CHIP_FAMILY_RV515,␊
78␉CHIP_FAMILY_R520,␊
79␉CHIP_FAMILY_RV530,␊
80␉CHIP_FAMILY_RV560,␊
81␉CHIP_FAMILY_RV570,␊
82␉CHIP_FAMILY_R580,␊
83␉/* IGP */␊
84␉CHIP_FAMILY_RS600,␊
85␉CHIP_FAMILY_RS690,␊
86␉CHIP_FAMILY_RS740,␊
87␉CHIP_FAMILY_RS780,␊
88␉CHIP_FAMILY_RS880,␊
89␉/* R600 */␊
90␉CHIP_FAMILY_R600,␊
91␉CHIP_FAMILY_RV610,␊
92␉CHIP_FAMILY_RV620,␊
93␉CHIP_FAMILY_RV630,␊
94␉CHIP_FAMILY_RV635,␊
95␉CHIP_FAMILY_RV670,␊
96␉/* R700 */␊
97␉CHIP_FAMILY_RV710,␊
98␉CHIP_FAMILY_RV730,␊
99␉CHIP_FAMILY_RV740,␊
100␉CHIP_FAMILY_RV770,␊
101␉CHIP_FAMILY_RV772,␊
102␉CHIP_FAMILY_RV790,␊
103␉/* Evergreen */␊
104␉CHIP_FAMILY_CEDAR,␊
105␉CHIP_FAMILY_CYPRESS,␊
106␉CHIP_FAMILY_HEMLOCK,␊
107␉CHIP_FAMILY_JUNIPER,␊
108␉CHIP_FAMILY_REDWOOD,␊
109␉CHIP_FAMILY_BROADWAY,␊
110 //␉CHIP_FAMILY_MADISON,␊
111 //␉CHIP_FAMILY_PARK,␊
112␉/* Northern Islands */␊
113 //␉CHIP_FAMILY_ANTILLES,␊
114␉CHIP_FAMILY_BARTS,␊
115␉CHIP_FAMILY_CAICOS,␊
116␉CHIP_FAMILY_CAYMAN,␊
117␉CHIP_FAMILY_TURKS,␊
118␉/* Southern Islands */␊
119␉CHIP_FAMILY_TAHITI,␊
120␉CHIP_FAMILY_PITCAIRN,␊
121 //␉CHIP_FAMILY_VERDE,␊
122 //␉CHIP_FAMILY_THAMES,␊
123 CHIP_FAMILY_LOMBOK,␊
124 //␉CHIP_FAMILY_NEWZEALAND,␊
125␉CHIP_FAMILY_LAST␊
126} ati_chip_family_t;␊
127␊
128typedef struct {␊
129␉const char␉␉*name;␊
130␉uint8_t␉␉␉ports;␊
131} card_config_t;␊
132␊
133typedef enum {␊
134␉kNull,␊
135/* OLDController */␊
136␉kWormy,␊
137␉kAlopias,␊
138␉kCaretta,␊
139␉kKakapo,␊
140␉kKipunji,␊
141␉kPeregrine,␊
142␉kRaven,␊
143␉kSphyrna,␊
144/* AMD2400Controller */␊
145␉kIago,␊
146/* AMD2600Controller */␊
147␉kHypoprion,␊
148␉kLamna,␊
149/* AMD3800Controller */␊
150␉kMegalodon,␊
151␉kTriakis,␊
152/* AMD4600Controller */␊
153␉kFlicker,␊
154␉kGliff,␊
155␉kShrike,␊
156/* AMD4800Controller */␊
157␉kCardinal,␊
158␉kMotmot,␊
159␉kQuail,␊
160/* AMD5000Controller */␊
161␉kDouc,␊
162␉kLangur,␊
163␉kUakari,␊
164␉kZonalis,␊
165␉kAlouatta,␊
166␉kHoolock,␊
167␉kVervet,␊
168␉kBaboon,␊
169␉kEulemur,␊
170␉kGalago,␊
171␉kColobus,␊
172␉kMangabey,␊
173␉kNomascus,␊
174␉kOrangutan,␊
175/* AMD6000Controller */␊
176␉kPithecia,␊
177␉kBulrushes,␊
178␉kCattail,␊
179␉kHydrilla,␊
180␉kDuckweed,␊
181␉kFanwort,␊
182␉kElodea,␊
183␉kKudzu,␊
184␉kGibba,␊
185␉kLotus,␊
186␉kIpomoea,␊
187␉kMuskgrass,␊
188␉kJuncus,␊
189␉kOsmunda,␊
190␉kPondweed,␊
191␉kSpikerush,␊
192␉kTypha,␊
193/* AMD7000Controller */␊
194␉kAji, // TESTING␊
195␉kBuri, // TESTING␊
196␉kChutoro, // TESTING␊
197␉kDashimaki, // TESTING␊
198␉kEbi, // TESTING␊
199␉kGari, // TESTING␊
200␉kFutomaki, // TESTING␊
201␉kHamachi, // TESTING␊
202␉kOPM, // TESTING␊
203␉kIkura, // TESTING␊
204␉kIkuraS, // TESTING␊
205␉kCfgEnd␊
206} config_name_t;␊
207␊
208typedef struct {␊
209␉uint16_t␉␉␉device_id;␊
210␉uint32_t␉␉␉subsys_id;␊
211␉ati_chip_family_t␉␉chip_family;␊
212␉const char␉␉␉*model_name;␊
213␉config_name_t␉␉␉cfg_name;␊
214} radeon_card_info_t;␊
215␊
216typedef struct {␊
217␉struct DevPropDevice␉␉*device;␊
218␉radeon_card_info_t␉␉*info;␊
219␉pci_dt_t␉␉␉*pci_dev;␊
220␉uint8_t␉␉␉␉*fb;␊
221␉uint8_t␉␉␉␉*mmio;␊
222␉uint8_t␉␉␉␉*io;␊
223␉uint8_t␉␉␉␉*rom;␊
224␉uint32_t␉␉␉rom_size;␊
225␉uint32_t␉␉␉vram_size;␊
226␉const char␉␉␉*cfg_name;␊
227␉uint8_t␉␉␉␉ports;␊
228␉uint32_t␉␉␉flags;␊
229␉bool␉␉␉␉posted;␊
230} card_t;␊
231card_t *card;␊
232␊
233/* Flags */␊
234#define MKFLAG(n)␉␉␉(1 << n)␊
235#define FLAGTRUE␉␉␉MKFLAG(0)␊
236#define EVERGREEN␉␉␉MKFLAG(1)␊
237#define FLAGMOBILE␉␉␉MKFLAG(2)␊
238␊
239//static uint8_t atN = 0;␊
240␊
241typedef struct {␊
242␉type_t␉␉␉␉type;␊
243␉uint32_t␉␉␉size;␊
244␉uint8_t␉␉␉␉*data;␊
245} value_t;␊
246␊
247typedef struct {␊
248␉uint32_t␉␉␉flags;␊
249␉bool␉␉␉␉all_ports;␊
250␉char␉␉␉␉*name;␊
251␉bool␉␉␉␉(*get_value)(value_t *val);␊
252␉value_t␉␉␉␉default_val;␊
253} dev_prop_t;␊
254␊
255bool get_bootdisplay_val(value_t *val);␊
256bool get_vrammemory_val(value_t *val);␊
257bool get_name_val(value_t *val);␊
258bool get_nameparent_val(value_t *val);␊
259bool get_model_val(value_t *val);␊
260bool get_conntype_val(value_t *val);␊
261bool get_vrammemsize_val(value_t *val);␊
262bool get_binimage_val(value_t *val);␊
263bool get_romrevision_val(value_t *val);␊
264bool get_deviceid_val(value_t *val);␊
265bool get_mclk_val(value_t *val);␊
266bool get_sclk_val(value_t *val);␊
267bool get_refclk_val(value_t *val);␊
268bool get_platforminfo_val(value_t *val);␊
269bool get_vramtotalsize_val(value_t *val);␊
270bool get_hdmiaudio(value_t * val);␊
271␊
272#define ATI_DATATYPE_VQ␉␉␉␉0␊
273#define ATI_DATATYPE_CI4␉␉␉1␊
274#define ATI_DATATYPE_CI8␉␉␉2␊
275#define ATI_DATATYPE_ARGB1555␉␉␉3␊
276#define ATI_DATATYPE_RGB565␉␉␉4␊
277#define ATI_DATATYPE_RGB888␉␉␉5␊
278#define ATI_DATATYPE_ARGB8888␉␉␉6␊
279#define ATI_DATATYPE_RGB332␉␉␉7␊
280#define ATI_DATATYPE_Y8␉␉␉␉8␊
281#define ATI_DATATYPE_RGB8␉␉␉9␊
282#define ATI_DATATYPE_CI16␉␉␉10␊
283#define ATI_DATATYPE_VYUY_422␉␉␉11␊
284#define ATI_DATATYPE_YVYU_422␉␉␉12␊
285#define ATI_DATATYPE_AYUV_444␉␉␉14␊
286#define ATI_DATATYPE_ARGB4444␉␉␉15␊
287␊
288␉␉␉␉/* Registers for 2D/Video/Overlay */␊
289#define RADEON_ADAPTER_ID 0x0f2c /* PCI */␊
290#define RADEON_AGP_BASE 0x0170␊
291#define RADEON_AGP_CNTL 0x0174␊
292# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)␊
293# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)␊
294# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)␊
295# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)␊
296# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)␊
297# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)␊
298# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)␊
299# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)␊
300#define RADEON_STATUS_PCI_CONFIG 0x06␊
301# define RADEON_CAP_LIST 0x100000␊
302#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/␊
303# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */␊
304# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */␊
305# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */␊
306# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */␊
307#define RADEON_AGP_COMMAND 0x0f60 /* PCI */␊
308#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/␊
309# define RADEON_AGP_ENABLE (1<<8)␊
310#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */␊
311#define RADEON_AGP_STATUS 0x0f5c /* PCI */␊
312# define RADEON_AGP_1X_MODE 0x01␊
313# define RADEON_AGP_2X_MODE 0x02␊
314# define RADEON_AGP_4X_MODE 0x04␊
315# define RADEON_AGP_FW_MODE 0x10␊
316# define RADEON_AGP_MODE_MASK 0x17␊
317# define RADEON_AGPv3_MODE 0x08␊
318# define RADEON_AGPv3_4X_MODE 0x01␊
319# define RADEON_AGPv3_8X_MODE 0x02␊
320#define RADEON_ATTRDR 0x03c1 /* VGA */␊
321#define RADEON_ATTRDW 0x03c0 /* VGA */␊
322#define RADEON_ATTRX 0x03c0 /* VGA */␊
323#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8␊
324#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc␊
325␊
326#define RADEON_BASE_CODE 0x0f0b␊
327#define RADEON_BIOS_0_SCRATCH 0x0010␊
328# define RADEON_FP_PANEL_SCALABLE (1 << 16)␊
329# define RADEON_FP_PANEL_SCALE_EN (1 << 17)␊
330# define RADEON_FP_CHIP_SCALE_EN (1 << 18)␊
331# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)␊
332# define RADEON_DISPLAY_ROT_MASK (3 << 28)␊
333# define RADEON_DISPLAY_ROT_00 (0 << 28)␊
334# define RADEON_DISPLAY_ROT_90 (1 << 28)␊
335# define RADEON_DISPLAY_ROT_180 (2 << 28)␊
336# define RADEON_DISPLAY_ROT_270 (3 << 28)␊
337#define RADEON_BIOS_1_SCRATCH 0x0014␊
338#define RADEON_BIOS_2_SCRATCH 0x0018␊
339#define RADEON_BIOS_3_SCRATCH 0x001c␊
340#define RADEON_BIOS_4_SCRATCH 0x0020␊
341# define RADEON_CRT1_ATTACHED_MASK (3 << 0)␊
342# define RADEON_CRT1_ATTACHED_MONO (1 << 0)␊
343# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)␊
344# define RADEON_LCD1_ATTACHED (1 << 2)␊
345# define RADEON_DFP1_ATTACHED (1 << 3)␊
346# define RADEON_TV1_ATTACHED_MASK (3 << 4)␊
347# define RADEON_TV1_ATTACHED_COMP (1 << 4)␊
348# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)␊
349# define RADEON_CRT2_ATTACHED_MASK (3 << 8)␊
350# define RADEON_CRT2_ATTACHED_MONO (1 << 8)␊
351# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)␊
352# define RADEON_DFP2_ATTACHED (1 << 11)␊
353#define RADEON_BIOS_5_SCRATCH 0x0024␊
354# define RADEON_LCD1_ON (1 << 0)␊
355# define RADEON_CRT1_ON (1 << 1)␊
356# define RADEON_TV1_ON (1 << 2)␊
357# define RADEON_DFP1_ON (1 << 3)␊
358# define RADEON_CRT2_ON (1 << 5)␊
359# define RADEON_CV1_ON (1 << 6)␊
360# define RADEON_DFP2_ON (1 << 7)␊
361# define RADEON_LCD1_CRTC_MASK (1 << 8)␊
362# define RADEON_LCD1_CRTC_SHIFT 8␊
363# define RADEON_CRT1_CRTC_MASK (1 << 9)␊
364# define RADEON_CRT1_CRTC_SHIFT 9␊
365# define RADEON_TV1_CRTC_MASK (1 << 10)␊
366# define RADEON_TV1_CRTC_SHIFT 10␊
367# define RADEON_DFP1_CRTC_MASK (1 << 11)␊
368# define RADEON_DFP1_CRTC_SHIFT 11␊
369# define RADEON_CRT2_CRTC_MASK (1 << 12)␊
370# define RADEON_CRT2_CRTC_SHIFT 12␊
371# define RADEON_CV1_CRTC_MASK (1 << 13)␊
372# define RADEON_CV1_CRTC_SHIFT 13␊
373# define RADEON_DFP2_CRTC_MASK (1 << 14)␊
374# define RADEON_DFP2_CRTC_SHIFT 14␊
375#define RADEON_BIOS_6_SCRATCH 0x0028␊
376# define RADEON_ACC_MODE_CHANGE (1 << 2)␊
377# define RADEON_EXT_DESKTOP_MODE (1 << 3)␊
378# define RADEON_LCD_DPMS_ON (1 << 20)␊
379# define RADEON_CRT_DPMS_ON (1 << 21)␊
380# define RADEON_TV_DPMS_ON (1 << 22)␊
381# define RADEON_DFP_DPMS_ON (1 << 23)␊
382# define RADEON_DPMS_MASK (3 << 24)␊
383# define RADEON_DPMS_ON (0 << 24)␊
384# define RADEON_DPMS_STANDBY (1 << 24)␊
385# define RADEON_DPMS_SUSPEND (2 << 24)␊
386# define RADEON_DPMS_OFF (3 << 24)␊
387# define RADEON_SCREEN_BLANKING (1 << 26)␊
388# define RADEON_DRIVER_CRITICAL (1 << 27)␊
389# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)␊
390#define RADEON_BIOS_7_SCRATCH 0x002c␊
391# define RADEON_SYS_HOTKEY (1 << 10)␊
392# define RADEON_DRV_LOADED (1 << 12)␊
393#define RADEON_BIOS_ROM 0x0f30 /* PCI */␊
394#define RADEON_BIST 0x0f0f /* PCI */␊
395#define RADEON_BRUSH_DATA0 0x1480␊
396#define RADEON_BRUSH_DATA1 0x1484␊
397#define RADEON_BRUSH_DATA10 0x14a8␊
398#define RADEON_BRUSH_DATA11 0x14ac␊
399#define RADEON_BRUSH_DATA12 0x14b0␊
400#define RADEON_BRUSH_DATA13 0x14b4␊
401#define RADEON_BRUSH_DATA14 0x14b8␊
402#define RADEON_BRUSH_DATA15 0x14bc␊
403#define RADEON_BRUSH_DATA16 0x14c0␊
404#define RADEON_BRUSH_DATA17 0x14c4␊
405#define RADEON_BRUSH_DATA18 0x14c8␊
406#define RADEON_BRUSH_DATA19 0x14cc␊
407#define RADEON_BRUSH_DATA2 0x1488␊
408#define RADEON_BRUSH_DATA20 0x14d0␊
409#define RADEON_BRUSH_DATA21 0x14d4␊
410#define RADEON_BRUSH_DATA22 0x14d8␊
411#define RADEON_BRUSH_DATA23 0x14dc␊
412#define RADEON_BRUSH_DATA24 0x14e0␊
413#define RADEON_BRUSH_DATA25 0x14e4␊
414#define RADEON_BRUSH_DATA26 0x14e8␊
415#define RADEON_BRUSH_DATA27 0x14ec␊
416#define RADEON_BRUSH_DATA28 0x14f0␊
417#define RADEON_BRUSH_DATA29 0x14f4␊
418#define RADEON_BRUSH_DATA3 0x148c␊
419#define RADEON_BRUSH_DATA30 0x14f8␊
420#define RADEON_BRUSH_DATA31 0x14fc␊
421#define RADEON_BRUSH_DATA32 0x1500␊
422#define RADEON_BRUSH_DATA33 0x1504␊
423#define RADEON_BRUSH_DATA34 0x1508␊
424#define RADEON_BRUSH_DATA35 0x150c␊
425#define RADEON_BRUSH_DATA36 0x1510␊
426#define RADEON_BRUSH_DATA37 0x1514␊
427#define RADEON_BRUSH_DATA38 0x1518␊
428#define RADEON_BRUSH_DATA39 0x151c␊
429#define RADEON_BRUSH_DATA4 0x1490␊
430#define RADEON_BRUSH_DATA40 0x1520␊
431#define RADEON_BRUSH_DATA41 0x1524␊
432#define RADEON_BRUSH_DATA42 0x1528␊
433#define RADEON_BRUSH_DATA43 0x152c␊
434#define RADEON_BRUSH_DATA44 0x1530␊
435#define RADEON_BRUSH_DATA45 0x1534␊
436#define RADEON_BRUSH_DATA46 0x1538␊
437#define RADEON_BRUSH_DATA47 0x153c␊
438#define RADEON_BRUSH_DATA48 0x1540␊
439#define RADEON_BRUSH_DATA49 0x1544␊
440#define RADEON_BRUSH_DATA5 0x1494␊
441#define RADEON_BRUSH_DATA50 0x1548␊
442#define RADEON_BRUSH_DATA51 0x154c␊
443#define RADEON_BRUSH_DATA52 0x1550␊
444#define RADEON_BRUSH_DATA53 0x1554␊
445#define RADEON_BRUSH_DATA54 0x1558␊
446#define RADEON_BRUSH_DATA55 0x155c␊
447#define RADEON_BRUSH_DATA56 0x1560␊
448#define RADEON_BRUSH_DATA57 0x1564␊
449#define RADEON_BRUSH_DATA58 0x1568␊
450#define RADEON_BRUSH_DATA59 0x156c␊
451#define RADEON_BRUSH_DATA6 0x1498␊
452#define RADEON_BRUSH_DATA60 0x1570␊
453#define RADEON_BRUSH_DATA61 0x1574␊
454#define RADEON_BRUSH_DATA62 0x1578␊
455#define RADEON_BRUSH_DATA63 0x157c␊
456#define RADEON_BRUSH_DATA7 0x149c␊
457#define RADEON_BRUSH_DATA8 0x14a0␊
458#define RADEON_BRUSH_DATA9 0x14a4␊
459#define RADEON_BRUSH_SCALE 0x1470␊
460#define RADEON_BRUSH_Y_X 0x1474␊
461#define RADEON_BUS_CNTL 0x0030␊
462# define RADEON_BUS_MASTER_DIS (1 << 6)␊
463# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)␊
464# define RADEON_BUS_RD_DISCARD_EN (1 << 24)␊
465# define RADEON_BUS_RD_ABORT_EN (1 << 25)␊
466# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)␊
467# define RADEON_BUS_WRT_BURST (1 << 29)␊
468# define RADEON_BUS_READ_BURST (1 << 30)␊
469#define RADEON_BUS_CNTL1 0x0034␊
470# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)␊
471␊
472#define RADEON_PCIE_INDEX 0x0030␊
473#define RADEON_PCIE_DATA 0x0034␊
474#define R600_PCIE_PORT_INDEX 0x0038␊
475#define R600_PCIE_PORT_DATA 0x003c␊
476/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */␊
477#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */␊
478# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0␊
479# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7␊
480# define RADEON_PCIE_LC_LINK_WIDTH_X0 0␊
481# define RADEON_PCIE_LC_LINK_WIDTH_X1 1␊
482# define RADEON_PCIE_LC_LINK_WIDTH_X2 2␊
483# define RADEON_PCIE_LC_LINK_WIDTH_X4 3␊
484# define RADEON_PCIE_LC_LINK_WIDTH_X8 4␊
485# define RADEON_PCIE_LC_LINK_WIDTH_X12 5␊
486# define RADEON_PCIE_LC_LINK_WIDTH_X16 6␊
487# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4␊
488# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70␊
489# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)␊
490# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)␊
491# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)␊
492# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)␊
493# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)␊
494# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)␊
495#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c␊
496#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c␊
497␊
498#define RADEON_CACHE_CNTL 0x1724␊
499#define RADEON_CACHE_LINE 0x0f0c /* PCI */␊
500#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */␊
501#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */␊
502#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */␊
503# define RADEON_DONT_USE_XTALIN (1 << 4)␊
504# define RADEON_SCLK_DYN_START_CNTL (1 << 15)␊
505#define RADEON_CLOCK_CNTL_DATA 0x000c␊
506#define RADEON_CLOCK_CNTL_INDEX 0x0008␊
507# define RADEON_PLL_WR_EN (1 << 7)␊
508# define RADEON_PLL_DIV_SEL (3 << 8)␊
509# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)␊
510#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */␊
511# define RADEON_M_SPLL_REF_DIV_MASK 0xff␊
512# define RADEON_M_SPLL_REF_DIV_SHIFT 0␊
513# define RADEON_MPLL_FB_DIV_MASK 0xff␊
514# define RADEON_MPLL_FB_DIV_SHIFT 8␊
515# define RADEON_SPLL_FB_DIV_MASK 0xff␊
516# define RADEON_SPLL_FB_DIV_SHIFT 16␊
517#define RADEON_SPLL_CNTL 0x000c /* PLL */␊
518# define RADEON_SPLL_SLEEP (1 << 0)␊
519# define RADEON_SPLL_RESET (1 << 1)␊
520# define RADEON_SPLL_PCP_MASK 0x7␊
521# define RADEON_SPLL_PCP_SHIFT 8␊
522# define RADEON_SPLL_PVG_MASK 0x7␊
523# define RADEON_SPLL_PVG_SHIFT 11␊
524# define RADEON_SPLL_PDC_MASK 0x3␊
525# define RADEON_SPLL_PDC_SHIFT 14␊
526#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */␊
527# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)␊
528# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)␊
529# define RADEON_ACTIVE_HILO_LAT_SHIFT 13␊
530# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)␊
531# define RADEON_MC_BUSY (1 << 16)␊
532# define RADEON_DLL_READY (1 << 19)␊
533# define RADEON_CG_NO1_DEBUG_0 (1 << 24)␊
534# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)␊
535# define RADEON_DYN_STOP_MODE_MASK (7 << 21)␊
536# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)␊
537# define RADEON_TVCLK_TURNOFF (1 << 31)␊
538#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */␊
539# define RADEON_TCL_BYPASS_DISABLE (1 << 20)␊
540#define RADEON_CLR_CMP_CLR_3D 0x1a24␊
541#define RADEON_CLR_CMP_CLR_DST 0x15c8␊
542#define RADEON_CLR_CMP_CLR_SRC 0x15c4␊
543#define RADEON_CLR_CMP_CNTL 0x15c0␊
544# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)␊
545# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)␊
546# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)␊
547#define RADEON_CLR_CMP_MASK 0x15cc␊
548# define RADEON_CLR_CMP_MSK 0xffffffff␊
549#define RADEON_CLR_CMP_MASK_3D 0x1A28␊
550#define RADEON_COMMAND 0x0f04 /* PCI */␊
551#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c␊
552#define RADEON_CONFIG_APER_0_BASE 0x0100␊
553#define RADEON_CONFIG_APER_1_BASE 0x0104␊
554#define RADEON_CONFIG_APER_SIZE 0x0108␊
555#define RADEON_CONFIG_BONDS 0x00e8␊
556#define RADEON_CONFIG_CNTL 0x00e0␊
557# define RADEON_CFG_ATI_REV_A11 (0 << 16)␊
558# define RADEON_CFG_ATI_REV_A12 (1 << 16)␊
559# define RADEON_CFG_ATI_REV_A13 (2 << 16)␊
560# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)␊
561#define RADEON_CONFIG_MEMSIZE 0x00f8␊
562#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114␊
563#define RADEON_CONFIG_REG_1_BASE 0x010c␊
564#define RADEON_CONFIG_REG_APER_SIZE 0x0110␊
565#define RADEON_CONFIG_XSTRAP 0x00e4␊
566#define RADEON_CONSTANT_COLOR_C 0x1d34␊
567# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff␊
568# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff␊
569# define RADEON_CONSTANT_COLOR_ZERO 0x00000000␊
570#define RADEON_CRC_CMDFIFO_ADDR 0x0740␊
571#define RADEON_CRC_CMDFIFO_DOUT 0x0744␊
572#define RADEON_GRPH_BUFFER_CNTL 0x02f0␊
573# define RADEON_GRPH_START_REQ_MASK (0x7f)␊
574# define RADEON_GRPH_START_REQ_SHIFT 0␊
575# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)␊
576# define RADEON_GRPH_STOP_REQ_SHIFT 8␊
577# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)␊
578# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16␊
579# define RADEON_GRPH_CRITICAL_CNTL (1<<28)␊
580# define RADEON_GRPH_BUFFER_SIZE (1<<29)␊
581# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)␊
582# define RADEON_GRPH_STOP_CNTL (1<<31)␊
583#define RADEON_GRPH2_BUFFER_CNTL 0x03f0␊
584# define RADEON_GRPH2_START_REQ_MASK (0x7f)␊
585# define RADEON_GRPH2_START_REQ_SHIFT 0␊
586# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)␊
587# define RADEON_GRPH2_STOP_REQ_SHIFT 8␊
588# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)␊
589# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16␊
590# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)␊
591# define RADEON_GRPH2_BUFFER_SIZE (1<<29)␊
592# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)␊
593# define RADEON_GRPH2_STOP_CNTL (1<<31)␊
594#define RADEON_CRTC_CRNT_FRAME 0x0214␊
595#define RADEON_CRTC_EXT_CNTL 0x0054␊
596# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)␊
597# define RADEON_VGA_ATI_LINEAR (1 << 3)␊
598# define RADEON_XCRT_CNT_EN (1 << 6)␊
599# define RADEON_CRTC_HSYNC_DIS (1 << 8)␊
600# define RADEON_CRTC_VSYNC_DIS (1 << 9)␊
601# define RADEON_CRTC_DISPLAY_DIS (1 << 10)␊
602# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)␊
603# define RADEON_CRTC_CRT_ON (1 << 15)␊
604#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055␊
605# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)␊
606# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)␊
607# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)␊
608#define RADEON_CRTC_GEN_CNTL 0x0050␊
609# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)␊
610# define RADEON_CRTC_INTERLACE_EN (1 << 1)␊
611# define RADEON_CRTC_CSYNC_EN (1 << 4)␊
612# define RADEON_CRTC_ICON_EN (1 << 15)␊
613# define RADEON_CRTC_CUR_EN (1 << 16)␊
614# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)␊
615# define RADEON_CRTC_EXT_DISP_EN (1 << 24)␊
616# define RADEON_CRTC_EN (1 << 25)␊
617# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)␊
618#define RADEON_CRTC2_GEN_CNTL 0x03f8␊
619# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)␊
620# define RADEON_CRTC2_INTERLACE_EN (1 << 1)␊
621# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)␊
622# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)␊
623# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)␊
624# define RADEON_CRTC2_CRT2_ON (1 << 7)␊
625# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8␊
626# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)␊
627# define RADEON_CRTC2_ICON_EN (1 << 15)␊
628# define RADEON_CRTC2_CUR_EN (1 << 16)␊
629# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)␊
630# define RADEON_CRTC2_DISP_DIS (1 << 23)␊
631# define RADEON_CRTC2_EN (1 << 25)␊
632# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)␊
633# define RADEON_CRTC2_CSYNC_EN (1 << 27)␊
634# define RADEON_CRTC2_HSYNC_DIS (1 << 28)␊
635# define RADEON_CRTC2_VSYNC_DIS (1 << 29)␊
636#define RADEON_CRTC_MORE_CNTL 0x27c␊
637# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)␊
638# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)␊
639# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)␊
640# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)␊
641#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218␊
642# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0␊
643# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15)␊
644# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16␊
645# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30)␊
646#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204␊
647# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)␊
648# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)␊
649# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3␊
650# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)␊
651# define RADEON_CRTC_H_SYNC_WID_SHIFT 16␊
652# define RADEON_CRTC_H_SYNC_POL (1 << 23)␊
653#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304␊
654# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)␊
655# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)␊
656# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3␊
657# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)␊
658# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16␊
659# define RADEON_CRTC2_H_SYNC_POL (1 << 23)␊
660#define RADEON_CRTC_H_TOTAL_DISP 0x0200␊
661# define RADEON_CRTC_H_TOTAL (0x03ff << 0)␊
662# define RADEON_CRTC_H_TOTAL_SHIFT 0␊
663# define RADEON_CRTC_H_DISP (0x01ff << 16)␊
664# define RADEON_CRTC_H_DISP_SHIFT 16␊
665#define RADEON_CRTC2_H_TOTAL_DISP 0x0300␊
666# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)␊
667# define RADEON_CRTC2_H_TOTAL_SHIFT 0␊
668# define RADEON_CRTC2_H_DISP (0x01ff << 16)␊
669# define RADEON_CRTC2_H_DISP_SHIFT 16␊
670␊
671#define RADEON_CRTC_OFFSET_RIGHT␉ 0x0220␊
672#define RADEON_CRTC_OFFSET 0x0224␊
673#␉define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)␊
674#␉define RADEON_CRTC_OFFSET__OFFSET_LOCK ␉ (1<<31)␊
675␊
676#define RADEON_CRTC2_OFFSET 0x0324␊
677#␉define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)␊
678#␉define RADEON_CRTC2_OFFSET__OFFSET_LOCK␉ (1<<31)␊
679#define RADEON_CRTC_OFFSET_CNTL 0x0228␊
680# define RADEON_CRTC_TILE_LINE_SHIFT 0␊
681# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4␊
682#␉define R300_CRTC_X_Y_MODE_EN_RIGHT␉␉(1 << 6)␊
683#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)␊
684#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)␊
685#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)␊
686#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)␊
687#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)␊
688#␉define R300_CRTC_X_Y_MODE_EN␉␉␉(1 << 9)␊
689#␉define R300_CRTC_MICRO_TILE_BUFFER_MASK ␉(3 << 10)␊
690#␉define R300_CRTC_MICRO_TILE_BUFFER_AUTO ␉(0 << 10)␊
691#␉define R300_CRTC_MICRO_TILE_BUFFER_SINGLE ␉(1 << 10)␊
692#␉define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE ␉(2 << 10)␊
693#␉define R300_CRTC_MICRO_TILE_BUFFER_DIS ␉(3 << 10)␊
694#␉define R300_CRTC_MICRO_TILE_EN_RIGHT␉␉(1 << 12)␊
695#␉define R300_CRTC_MICRO_TILE_EN␉␉␉(1 << 13)␊
696#␉define R300_CRTC_MACRO_TILE_EN_RIGHT␉␉(1 << 14)␊
697# define R300_CRTC_MACRO_TILE_EN (1 << 15)␊
698# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)␊
699# define RADEON_CRTC_TILE_EN (1 << 15)␊
700# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)␊
701# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)␊
702␊
703#define R300_CRTC_TILE_X0_Y0␉ 0x0350␊
704#define R300_CRTC2_TILE_X0_Y0␉ 0x0358␊
705␊
706#define RADEON_CRTC2_OFFSET_CNTL 0x0328␊
707# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)␊
708# define RADEON_CRTC2_TILE_EN (1 << 15)␊
709#define RADEON_CRTC_PITCH 0x022c␊
710#␉define RADEON_CRTC_PITCH__SHIFT␉␉ 0␊
711#␉define RADEON_CRTC_PITCH__RIGHT_SHIFT␉16␊
712␊
713#define RADEON_CRTC2_PITCH 0x032c␊
714#define RADEON_CRTC_STATUS 0x005c␊
715# define RADEON_CRTC_VBLANK_SAVE (1 << 1)␊
716# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)␊
717#define RADEON_CRTC2_STATUS 0x03fc␊
718# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)␊
719# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)␊
720#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c␊
721# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)␊
722# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0␊
723# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)␊
724# define RADEON_CRTC_V_SYNC_WID_SHIFT 16␊
725# define RADEON_CRTC_V_SYNC_POL (1 << 23)␊
726#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c␊
727# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)␊
728# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0␊
729# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)␊
730# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16␊
731# define RADEON_CRTC2_V_SYNC_POL (1 << 23)␊
732#define RADEON_CRTC_V_TOTAL_DISP 0x0208␊
733# define RADEON_CRTC_V_TOTAL (0x07ff << 0)␊
734# define RADEON_CRTC_V_TOTAL_SHIFT 0␊
735# define RADEON_CRTC_V_DISP (0x07ff << 16)␊
736# define RADEON_CRTC_V_DISP_SHIFT 16␊
737#define RADEON_CRTC2_V_TOTAL_DISP 0x0308␊
738# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)␊
739# define RADEON_CRTC2_V_TOTAL_SHIFT 0␊
740# define RADEON_CRTC2_V_DISP (0x07ff << 16)␊
741# define RADEON_CRTC2_V_DISP_SHIFT 16␊
742#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210␊
743# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)␊
744#define RADEON_CRTC2_CRNT_FRAME 0x0314␊
745#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318␊
746#define RADEON_CRTC2_STATUS 0x03fc␊
747#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310␊
748#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */␊
749#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */␊
750#define RADEON_CUR_CLR0 0x026c␊
751#define RADEON_CUR_CLR1 0x0270␊
752#define RADEON_CUR_HORZ_VERT_OFF 0x0268␊
753#define RADEON_CUR_HORZ_VERT_POSN 0x0264␊
754#define RADEON_CUR_OFFSET 0x0260␊
755# define RADEON_CUR_LOCK (1 << 31)␊
756#define RADEON_CUR2_CLR0 0x036c␊
757#define RADEON_CUR2_CLR1 0x0370␊
758#define RADEON_CUR2_HORZ_VERT_OFF 0x0368␊
759#define RADEON_CUR2_HORZ_VERT_POSN 0x0364␊
760#define RADEON_CUR2_OFFSET 0x0360␊
761# define RADEON_CUR2_LOCK (1 << 31)␊
762␊
763#define RADEON_DAC_CNTL 0x0058␊
764# define RADEON_DAC_RANGE_CNTL (3 << 0)␊
765# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)␊
766# define RADEON_DAC_RANGE_CNTL_MASK 0x03␊
767# define RADEON_DAC_BLANKING (1 << 2)␊
768# define RADEON_DAC_CMP_EN (1 << 3)␊
769# define RADEON_DAC_CMP_OUTPUT (1 << 7)␊
770# define RADEON_DAC_8BIT_EN (1 << 8)␊
771# define RADEON_DAC_TVO_EN (1 << 10)␊
772# define RADEON_DAC_VGA_ADR_EN (1 << 13)␊
773# define RADEON_DAC_PDWN (1 << 15)␊
774# define RADEON_DAC_MASK_ALL (0xff << 24)␊
775#define RADEON_DAC_CNTL2 0x007c␊
776# define RADEON_DAC2_TV_CLK_SEL (0 << 1)␊
777# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)␊
778# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)␊
779# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)␊
780# define RADEON_DAC2_CMP_EN (1 << 7)␊
781# define RADEON_DAC2_CMP_OUT_R (1 << 8)␊
782# define RADEON_DAC2_CMP_OUT_G (1 << 9)␊
783# define RADEON_DAC2_CMP_OUT_B (1 << 10)␊
784# define RADEON_DAC2_CMP_OUTPUT (1 << 11)␊
785#define RADEON_DAC_EXT_CNTL 0x0280␊
786# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)␊
787# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)␊
788# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)␊
789# define RADEON_DAC_FORCE_DATA_EN (1 << 5)␊
790# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)␊
791# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)␊
792# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)␊
793# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)␊
794# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)␊
795# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00␊
796# define RADEON_DAC_FORCE_DATA_SHIFT 8␊
797#define RADEON_DAC_MACRO_CNTL 0x0d04␊
798# define RADEON_DAC_PDWN_R (1 << 16)␊
799# define RADEON_DAC_PDWN_G (1 << 17)␊
800# define RADEON_DAC_PDWN_B (1 << 18)␊
801#define RADEON_TV_DAC_CNTL 0x088c␊
802# define RADEON_TV_DAC_NBLANK (1 << 0)␊
803# define RADEON_TV_DAC_NHOLD (1 << 1)␊
804# define RADEON_TV_DAC_PEDESTAL (1 << 2)␊
805# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)␊
806# define RADEON_TV_DAC_CMPOUT (1 << 5)␊
807# define RADEON_TV_DAC_STD_MASK (3 << 8)␊
808# define RADEON_TV_DAC_STD_PAL (0 << 8)␊
809# define RADEON_TV_DAC_STD_NTSC (1 << 8)␊
810# define RADEON_TV_DAC_STD_PS2 (2 << 8)␊
811# define RADEON_TV_DAC_STD_RS343 (3 << 8)␊
812# define RADEON_TV_DAC_BGSLEEP (1 << 6)␊
813# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)␊
814# define RADEON_TV_DAC_BGADJ_SHIFT 16␊
815# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)␊
816# define RADEON_TV_DAC_DACADJ_SHIFT 20␊
817# define RADEON_TV_DAC_RDACPD (1 << 24)␊
818# define RADEON_TV_DAC_GDACPD (1 << 25)␊
819# define RADEON_TV_DAC_BDACPD (1 << 26)␊
820# define RADEON_TV_DAC_RDACDET (1 << 29)␊
821# define RADEON_TV_DAC_GDACDET (1 << 30)␊
822# define RADEON_TV_DAC_BDACDET (1 << 31)␊
823# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)␊
824# define R420_TV_DAC_RDACPD (1 << 25)␊
825# define R420_TV_DAC_GDACPD (1 << 26)␊
826# define R420_TV_DAC_BDACPD (1 << 27)␊
827# define R420_TV_DAC_TVENABLE (1 << 28)␊
828#define RADEON_DISP_HW_DEBUG 0x0d14␊
829# define RADEON_CRT2_DISP1_SEL (1 << 5)␊
830#define RADEON_DISP_OUTPUT_CNTL 0x0d64␊
831# define RADEON_DISP_DAC_SOURCE_MASK 0x03␊
832# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c␊
833# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01␊
834# define RADEON_DISP_DAC_SOURCE_RMX 0x02␊
835# define RADEON_DISP_DAC_SOURCE_LTU 0x03␊
836# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04␊
837# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)␊
838# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0␊
839# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)␊
840# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)␊
841# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)␊
842# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)␊
843# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)␊
844# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)␊
845# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)␊
846# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */␊
847# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */␊
848#define RADEON_DISP_TV_OUT_CNTL 0x0d6c␊
849# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)␊
850# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)␊
851#define RADEON_DAC_CRC_SIG 0x02cc␊
852#define RADEON_DAC_DATA 0x03c9 /* VGA */␊
853#define RADEON_DAC_MASK 0x03c6 /* VGA */␊
854#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */␊
855#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */␊
856#define RADEON_DDA_CONFIG 0x02e0␊
857#define RADEON_DDA_ON_OFF 0x02e4␊
858#define RADEON_DEFAULT_OFFSET 0x16e0␊
859#define RADEON_DEFAULT_PITCH 0x16e4␊
860#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8␊
861# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)␊
862# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)␊
863#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820␊
864#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824␊
865#define RADEON_DEVICE_ID 0x0f02 /* PCI */␊
866#define RADEON_DISP_MISC_CNTL 0x0d00␊
867# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)␊
868#define RADEON_DISP_MERGE_CNTL␉␉ 0x0d60␊
869# define RADEON_DISP_ALPHA_MODE_MASK 0x03␊
870# define RADEON_DISP_ALPHA_MODE_KEY 0␊
871# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1␊
872# define RADEON_DISP_ALPHA_MODE_GLOBAL 2␊
873# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)␊
874# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)␊
875# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)␊
876#␉define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)␊
877#define RADEON_DISP2_MERGE_CNTL␉␉ 0x0d68␊
878# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)␊
879#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80␊
880#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84␊
881#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88␊
882#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c␊
883#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90␊
884#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98␊
885#define RADEON_DP_BRUSH_BKGD_CLR 0x1478␊
886#define RADEON_DP_BRUSH_FRGD_CLR 0x147c␊
887#define RADEON_DP_CNTL 0x16c0␊
888# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)␊
889# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)␊
890# define RADEON_DP_DST_TILE_LINEAR (0 << 3)␊
891# define RADEON_DP_DST_TILE_MACRO (1 << 3)␊
892# define RADEON_DP_DST_TILE_MICRO (2 << 3)␊
893# define RADEON_DP_DST_TILE_BOTH (3 << 3)␊
894#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0␊
895# define RADEON_DST_Y_MAJOR (1 << 2)␊
896# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)␊
897# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)␊
898#define RADEON_DP_DATATYPE 0x16c4␊
899# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)␊
900#define RADEON_DP_GUI_MASTER_CNTL 0x146c␊
901# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)␊
902# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)␊
903# define RADEON_GMC_SRC_CLIPPING (1 << 2)␊
904# define RADEON_GMC_DST_CLIPPING (1 << 3)␊
905# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)␊
906# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)␊
907# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)␊
908# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)␊
909# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)␊
910# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)␊
911# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)␊
912# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)␊
913# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)␊
914# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)␊
915# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)␊
916# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)␊
917# define RADEON_GMC_BRUSH_NONE (15 << 4)␊
918# define RADEON_GMC_DST_8BPP_CI (2 << 8)␊
919# define RADEON_GMC_DST_15BPP (3 << 8)␊
920# define RADEON_GMC_DST_16BPP (4 << 8)␊
921# define RADEON_GMC_DST_24BPP (5 << 8)␊
922# define RADEON_GMC_DST_32BPP (6 << 8)␊
923# define RADEON_GMC_DST_8BPP_RGB (7 << 8)␊
924# define RADEON_GMC_DST_Y8 (8 << 8)␊
925# define RADEON_GMC_DST_RGB8 (9 << 8)␊
926# define RADEON_GMC_DST_VYUY (11 << 8)␊
927# define RADEON_GMC_DST_YVYU (12 << 8)␊
928# define RADEON_GMC_DST_AYUV444 (14 << 8)␊
929# define RADEON_GMC_DST_ARGB4444 (15 << 8)␊
930# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)␊
931# define RADEON_GMC_DST_DATATYPE_SHIFT 8␊
932# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)␊
933# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)␊
934# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)␊
935# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)␊
936# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)␊
937# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)␊
938# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)␊
939# define RADEON_GMC_CONVERSION_TEMP (1 << 15)␊
940# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)␊
941# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)␊
942# define RADEON_GMC_ROP3_MASK (0xff << 16)␊
943# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)␊
944# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)␊
945# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)␊
946# define RADEON_GMC_3D_FCN_EN (1 << 27)␊
947# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)␊
948# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)␊
949# define RADEON_GMC_WR_MSK_DIS (1 << 30)␊
950# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)␊
951# define RADEON_ROP3_ZERO 0x00000000␊
952# define RADEON_ROP3_DSa 0x00880000␊
953# define RADEON_ROP3_SDna 0x00440000␊
954# define RADEON_ROP3_S 0x00cc0000␊
955# define RADEON_ROP3_DSna 0x00220000␊
956# define RADEON_ROP3_D 0x00aa0000␊
957# define RADEON_ROP3_DSx 0x00660000␊
958# define RADEON_ROP3_DSo 0x00ee0000␊
959# define RADEON_ROP3_DSon 0x00110000␊
960# define RADEON_ROP3_DSxn 0x00990000␊
961# define RADEON_ROP3_Dn 0x00550000␊
962# define RADEON_ROP3_SDno 0x00dd0000␊
963# define RADEON_ROP3_Sn 0x00330000␊
964# define RADEON_ROP3_DSno 0x00bb0000␊
965# define RADEON_ROP3_DSan 0x00770000␊
966# define RADEON_ROP3_ONE 0x00ff0000␊
967# define RADEON_ROP3_DPa 0x00a00000␊
968# define RADEON_ROP3_PDna 0x00500000␊
969# define RADEON_ROP3_P 0x00f00000␊
970# define RADEON_ROP3_DPna 0x000a0000␊
971# define RADEON_ROP3_D 0x00aa0000␊
972# define RADEON_ROP3_DPx 0x005a0000␊
973# define RADEON_ROP3_DPo 0x00fa0000␊
974# define RADEON_ROP3_DPon 0x00050000␊
975# define RADEON_ROP3_PDxn 0x00a50000␊
976# define RADEON_ROP3_PDno 0x00f50000␊
977# define RADEON_ROP3_Pn 0x000f0000␊
978# define RADEON_ROP3_DPno 0x00af0000␊
979# define RADEON_ROP3_DPan 0x005f0000␊
980#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84␊
981#define RADEON_DP_MIX 0x16c8␊
982#define RADEON_DP_SRC_BKGD_CLR 0x15dc␊
983#define RADEON_DP_SRC_FRGD_CLR 0x15d8␊
984#define RADEON_DP_WRITE_MASK 0x16cc␊
985#define RADEON_DST_BRES_DEC 0x1630␊
986#define RADEON_DST_BRES_ERR 0x1628␊
987#define RADEON_DST_BRES_INC 0x162c␊
988#define RADEON_DST_BRES_LNTH 0x1634␊
989#define RADEON_DST_BRES_LNTH_SUB 0x1638␊
990#define RADEON_DST_HEIGHT 0x1410␊
991#define RADEON_DST_HEIGHT_WIDTH 0x143c␊
992#define RADEON_DST_HEIGHT_WIDTH_8 0x158c␊
993#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4␊
994#define RADEON_DST_HEIGHT_Y 0x15a0␊
995#define RADEON_DST_LINE_START 0x1600␊
996#define RADEON_DST_LINE_END 0x1604␊
997#define RADEON_DST_LINE_PATCOUNT 0x1608␊
998# define RADEON_BRES_CNTL_SHIFT 8␊
999#define RADEON_DST_OFFSET 0x1404␊
1000#define RADEON_DST_PITCH 0x1408␊
1001#define RADEON_DST_PITCH_OFFSET 0x142c␊
1002#define RADEON_DST_PITCH_OFFSET_C 0x1c80␊
1003# define RADEON_PITCH_SHIFT 21␊
1004# define RADEON_DST_TILE_LINEAR (0 << 30)␊
1005# define RADEON_DST_TILE_MACRO (1 << 30)␊
1006# define RADEON_DST_TILE_MICRO (2 << 30)␊
1007# define RADEON_DST_TILE_BOTH (3 << 30)␊
1008#define RADEON_DST_WIDTH 0x140c␊
1009#define RADEON_DST_WIDTH_HEIGHT 0x1598␊
1010#define RADEON_DST_WIDTH_X 0x1588␊
1011#define RADEON_DST_WIDTH_X_INCY 0x159c␊
1012#define RADEON_DST_X 0x141c␊
1013#define RADEON_DST_X_SUB 0x15a4␊
1014#define RADEON_DST_X_Y 0x1594␊
1015#define RADEON_DST_Y 0x1420␊
1016#define RADEON_DST_Y_SUB 0x15a8␊
1017#define RADEON_DST_Y_X 0x1438␊
1018␊
1019#define RADEON_FCP_CNTL 0x0910␊
1020# define RADEON_FCP0_SRC_PCICLK 0␊
1021# define RADEON_FCP0_SRC_PCLK 1␊
1022# define RADEON_FCP0_SRC_PCLKb 2␊
1023# define RADEON_FCP0_SRC_HREF 3␊
1024# define RADEON_FCP0_SRC_GND 4␊
1025# define RADEON_FCP0_SRC_HREFb 5␊
1026#define RADEON_FLUSH_1 0x1704␊
1027#define RADEON_FLUSH_2 0x1708␊
1028#define RADEON_FLUSH_3 0x170c␊
1029#define RADEON_FLUSH_4 0x1710␊
1030#define RADEON_FLUSH_5 0x1714␊
1031#define RADEON_FLUSH_6 0x1718␊
1032#define RADEON_FLUSH_7 0x171c␊
1033#define RADEON_FOG_3D_TABLE_START 0x1810␊
1034#define RADEON_FOG_3D_TABLE_END 0x1814␊
1035#define RADEON_FOG_3D_TABLE_DENSITY 0x181c␊
1036#define RADEON_FOG_TABLE_INDEX 0x1a14␊
1037#define RADEON_FOG_TABLE_DATA 0x1a18␊
1038#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250␊
1039#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254␊
1040# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff␊
1041# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000␊
1042# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff␊
1043# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000␊
1044# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8␊
1045# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000␊
1046# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff␊
1047# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000␊
1048# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000␊
1049# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010␊
1050# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000␊
1051# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010␊
1052# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003␊
1053# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010␊
1054# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000␊
1055# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010␊
1056#define RADEON_FP_GEN_CNTL 0x0284␊
1057# define RADEON_FP_FPON (1 << 0)␊
1058# define RADEON_FP_BLANK_EN (1 << 1)␊
1059# define RADEON_FP_TMDS_EN (1 << 2)␊
1060# define RADEON_FP_PANEL_FORMAT (1 << 3)␊
1061# define RADEON_FP_EN_TMDS (1 << 7)␊
1062# define RADEON_FP_DETECT_SENSE (1 << 8)␊
1063# define R200_FP_SOURCE_SEL_MASK (3 << 10)␊
1064# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)␊
1065# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)␊
1066# define R200_FP_SOURCE_SEL_RMX (2 << 10)␊
1067# define R200_FP_SOURCE_SEL_TRANS (3 << 10)␊
1068# define RADEON_FP_SEL_CRTC1 (0 << 13)␊
1069# define RADEON_FP_SEL_CRTC2 (1 << 13)␊
1070# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)␊
1071# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)␊
1072# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)␊
1073# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)␊
1074# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)␊
1075# define RADEON_FP_DFP_SYNC_SEL (1 << 21)␊
1076# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)␊
1077# define RADEON_FP_CRT_SYNC_SEL (1 << 23)␊
1078# define RADEON_FP_USE_SHADOW_EN (1 << 24)␊
1079# define RADEON_FP_CRT_SYNC_ALT (1 << 26)␊
1080#define RADEON_FP2_GEN_CNTL 0x0288␊
1081# define RADEON_FP2_BLANK_EN (1 << 1)␊
1082# define RADEON_FP2_ON (1 << 2)␊
1083# define RADEON_FP2_PANEL_FORMAT (1 << 3)␊
1084# define RADEON_FP2_DETECT_SENSE (1 << 8)␊
1085# define R200_FP2_SOURCE_SEL_MASK (3 << 10)␊
1086# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)␊
1087# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)␊
1088# define R200_FP2_SOURCE_SEL_RMX (2 << 10)␊
1089# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)␊
1090# define RADEON_FP2_SRC_SEL_MASK (3 << 13)␊
1091# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)␊
1092# define RADEON_FP2_FP_POL (1 << 16)␊
1093# define RADEON_FP2_LP_POL (1 << 17)␊
1094# define RADEON_FP2_SCK_POL (1 << 18)␊
1095# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)␊
1096# define RADEON_FP2_PAD_FLOP_EN (1 << 22)␊
1097# define RADEON_FP2_CRC_EN (1 << 23)␊
1098# define RADEON_FP2_CRC_READ_EN (1 << 24)␊
1099# define RADEON_FP2_DVO_EN (1 << 25)␊
1100# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)␊
1101# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)␊
1102# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)␊
1103# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)␊
1104#define RADEON_FP_H_SYNC_STRT_WID 0x02c4␊
1105#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4␊
1106#define RADEON_FP_HORZ_STRETCH 0x028c␊
1107#define RADEON_FP_HORZ2_STRETCH 0x038c␊
1108# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff␊
1109# define RADEON_HORZ_STRETCH_RATIO_MAX 4096␊
1110# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)␊
1111# define RADEON_HORZ_PANEL_SHIFT 16␊
1112# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)␊
1113# define RADEON_HORZ_STRETCH_BLEND (1 << 26)␊
1114# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)␊
1115# define RADEON_HORZ_AUTO_RATIO (1 << 27)␊
1116# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)␊
1117# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)␊
1118#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278␊
1119#define RADEON_FP_V_SYNC_STRT_WID 0x02c8␊
1120#define RADEON_FP_VERT_STRETCH 0x0290␊
1121#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8␊
1122#define RADEON_FP_VERT2_STRETCH 0x0390␊
1123# define RADEON_VERT_PANEL_SIZE (0xfff << 12)␊
1124# define RADEON_VERT_PANEL_SHIFT 12␊
1125# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff␊
1126# define RADEON_VERT_STRETCH_RATIO_SHIFT 0␊
1127# define RADEON_VERT_STRETCH_RATIO_MAX 4096␊
1128# define RADEON_VERT_STRETCH_ENABLE (1 << 25)␊
1129# define RADEON_VERT_STRETCH_LINEREP (0 << 26)␊
1130# define RADEON_VERT_STRETCH_BLEND (1 << 26)␊
1131# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)␊
1132#␉define RADEON_VERT_AUTO_RATIO_INC (1 << 31)␊
1133# define RADEON_VERT_STRETCH_RESERVED 0x71000000␊
1134#define RS400_FP_2ND_GEN_CNTL 0x0384␊
1135# define RS400_FP_2ND_ON (1 << 0)␊
1136# define RS400_FP_2ND_BLANK_EN (1 << 1)␊
1137# define RS400_TMDS_2ND_EN (1 << 2)␊
1138# define RS400_PANEL_FORMAT_2ND (1 << 3)␊
1139# define RS400_FP_2ND_EN_TMDS (1 << 7)␊
1140# define RS400_FP_2ND_DETECT_SENSE (1 << 8)␊
1141# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)␊
1142# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)␊
1143# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)␊
1144# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)␊
1145# define RS400_FP_2ND_DETECT_EN (1 << 12)␊
1146# define RS400_HPD_2ND_SEL (1 << 13)␊
1147#define RS400_FP2_2_GEN_CNTL 0x0388␊
1148# define RS400_FP2_2_BLANK_EN (1 << 1)␊
1149# define RS400_FP2_2_ON (1 << 2)␊
1150# define RS400_FP2_2_PANEL_FORMAT (1 << 3)␊
1151# define RS400_FP2_2_DETECT_SENSE (1 << 8)␊
1152# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)␊
1153# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)␊
1154# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)␊
1155# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)␊
1156# define RS400_FP2_2_DVO2_EN (1 << 25)␊
1157#define RS400_TMDS2_CNTL 0x0394␊
1158#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4␊
1159# define RS400_TMDS2_PLLEN (1 << 0)␊
1160# define RS400_TMDS2_PLLRST (1 << 1)␊
1161␊
1162#define RADEON_GEN_INT_CNTL 0x0040␊
1163#define RADEON_GEN_INT_STATUS 0x0044␊
1164# define RADEON_VSYNC_INT_AK (1 << 2)␊
1165# define RADEON_VSYNC_INT (1 << 2)␊
1166# define RADEON_VSYNC2_INT_AK (1 << 6)␊
1167# define RADEON_VSYNC2_INT (1 << 6)␊
1168#define RADEON_GENENB 0x03c3 /* VGA */␊
1169#define RADEON_GENFC_RD 0x03ca /* VGA */␊
1170#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */␊
1171#define RADEON_GENMO_RD 0x03cc /* VGA */␊
1172#define RADEON_GENMO_WT 0x03c2 /* VGA */␊
1173#define RADEON_GENS0 0x03c2 /* VGA */␊
1174#define RADEON_GENS1 0x03da /* VGA, 0x03ba */␊
1175#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */␊
1176#define RADEON_GPIO_MONIDB 0x006c␊
1177#define RADEON_GPIO_CRT2_DDC 0x006c␊
1178#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */␊
1179#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */␊
1180# define RADEON_GPIO_A_0 (1 << 0)␊
1181# define RADEON_GPIO_A_1 (1 << 1)␊
1182# define RADEON_GPIO_Y_0 (1 << 8)␊
1183# define RADEON_GPIO_Y_1 (1 << 9)␊
1184# define RADEON_GPIO_Y_SHIFT_0 8␊
1185# define RADEON_GPIO_Y_SHIFT_1 9␊
1186# define RADEON_GPIO_EN_0 (1 << 16)␊
1187# define RADEON_GPIO_EN_1 (1 << 17)␊
1188# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/␊
1189# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/␊
1190#define RADEON_GRPH8_DATA 0x03cf /* VGA */␊
1191#define RADEON_GRPH8_IDX 0x03ce /* VGA */␊
1192#define RADEON_GUI_SCRATCH_REG0 0x15e0␊
1193#define RADEON_GUI_SCRATCH_REG1 0x15e4␊
1194#define RADEON_GUI_SCRATCH_REG2 0x15e8␊
1195#define RADEON_GUI_SCRATCH_REG3 0x15ec␊
1196#define RADEON_GUI_SCRATCH_REG4 0x15f0␊
1197#define RADEON_GUI_SCRATCH_REG5 0x15f4␊
1198␊
1199#define RADEON_HEADER 0x0f0e /* PCI */␊
1200#define RADEON_HOST_DATA0 0x17c0␊
1201#define RADEON_HOST_DATA1 0x17c4␊
1202#define RADEON_HOST_DATA2 0x17c8␊
1203#define RADEON_HOST_DATA3 0x17cc␊
1204#define RADEON_HOST_DATA4 0x17d0␊
1205#define RADEON_HOST_DATA5 0x17d4␊
1206#define RADEON_HOST_DATA6 0x17d8␊
1207#define RADEON_HOST_DATA7 0x17dc␊
1208#define RADEON_HOST_DATA_LAST 0x17e0␊
1209#define RADEON_HOST_PATH_CNTL 0x0130␊
1210# define RADEON_HDP_SOFT_RESET (1 << 26)␊
1211# define RADEON_HDP_APER_CNTL (1 << 23)␊
1212#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */␊
1213# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)␊
1214#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */␊
1215␊
1216 /* Multimedia I2C bus */␊
1217#define RADEON_I2C_CNTL_0␉␉ 0x0090␊
1218#define RADEON_I2C_DONE (1 << 0)␊
1219#define RADEON_I2C_NACK (1 << 1)␊
1220#define RADEON_I2C_HALT (1 << 2)␊
1221#define RADEON_I2C_SOFT_RST (1 << 5)␊
1222#define RADEON_I2C_DRIVE_EN (1 << 6)␊
1223#define RADEON_I2C_DRIVE_SEL (1 << 7)␊
1224#define RADEON_I2C_START (1 << 8)␊
1225#define RADEON_I2C_STOP (1 << 9)␊
1226#define RADEON_I2C_RECEIVE (1 << 10)␊
1227#define RADEON_I2C_ABORT (1 << 11)␊
1228#define RADEON_I2C_GO (1 << 12)␊
1229#define RADEON_I2C_CNTL_1 0x0094␊
1230#define RADEON_I2C_SEL (1 << 16)␊
1231#define RADEON_I2C_EN (1 << 17)␊
1232#define RADEON_I2C_DATA␉␉␉ 0x0098␊
1233␊
1234#define RADEON_DVI_I2C_CNTL_0␉␉ 0x02e0␊
1235# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)␊
1236# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */␊
1237# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */␊
1238# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */␊
1239#define RADEON_DVI_I2C_CNTL_1 0x02e4␊
1240#define RADEON_DVI_I2C_DATA␉␉ 0x02e8␊
1241␊
1242#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */␊
1243#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */␊
1244#define RADEON_IO_BASE 0x0f14 /* PCI */␊
1245␊
1246#define RADEON_LATENCY 0x0f0d /* PCI */␊
1247#define RADEON_LEAD_BRES_DEC 0x1608␊
1248#define RADEON_LEAD_BRES_LNTH 0x161c␊
1249#define RADEON_LEAD_BRES_LNTH_SUB 0x1624␊
1250#define RADEON_LVDS_GEN_CNTL 0x02d0␊
1251# define RADEON_LVDS_ON (1 << 0)␊
1252# define RADEON_LVDS_DISPLAY_DIS (1 << 1)␊
1253# define RADEON_LVDS_PANEL_TYPE (1 << 2)␊
1254# define RADEON_LVDS_PANEL_FORMAT (1 << 3)␊
1255# define RADEON_LVDS_RST_FM (1 << 6)␊
1256# define RADEON_LVDS_EN (1 << 7)␊
1257# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8␊
1258# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)␊
1259# define RADEON_LVDS_BL_MOD_EN (1 << 16)␊
1260# define RADEON_LVDS_DIGON (1 << 18)␊
1261# define RADEON_LVDS_BLON (1 << 19)␊
1262# define RADEON_LVDS_SEL_CRTC2 (1 << 23)␊
1263#define RADEON_LVDS_PLL_CNTL 0x02d4␊
1264# define RADEON_HSYNC_DELAY_SHIFT 28␊
1265# define RADEON_HSYNC_DELAY_MASK (0xf << 28)␊
1266# define RADEON_LVDS_PLL_EN (1 << 16)␊
1267# define RADEON_LVDS_PLL_RESET (1 << 17)␊
1268# define R300_LVDS_SRC_SEL_MASK (3 << 18)␊
1269# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)␊
1270# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)␊
1271# define R300_LVDS_SRC_SEL_RMX (2 << 18)␊
1272␊
1273#define RADEON_MAX_LATENCY 0x0f3f /* PCI */␊
1274#define RADEON_MC_AGP_LOCATION 0x014c␊
1275#define RADEON_MC_FB_LOCATION 0x0148␊
1276#define RADEON_DISPLAY_BASE_ADDR 0x23c␊
1277#define RADEON_DISPLAY2_BASE_ADDR 0x33c␊
1278#define RADEON_OV0_BASE_ADDR 0x43c␊
1279#define RADEON_NB_TOM 0x15c␊
1280#define R300_MC_INIT_MISC_LAT_TIMER 0x180␊
1281# define R300_MC_DISP0R_INIT_LAT_SHIFT 8␊
1282# define R300_MC_DISP0R_INIT_LAT_MASK 0xf␊
1283# define R300_MC_DISP1R_INIT_LAT_SHIFT 12␊
1284# define R300_MC_DISP1R_INIT_LAT_MASK 0xf␊
1285#define RADEON_MCLK_CNTL 0x0012 /* PLL */␊
1286# define RADEON_FORCEON_MCLKA (1 << 16)␊
1287# define RADEON_FORCEON_MCLKB (1 << 17)␊
1288# define RADEON_FORCEON_YCLKA (1 << 18)␊
1289# define RADEON_FORCEON_YCLKB (1 << 19)␊
1290# define RADEON_FORCEON_MC (1 << 20)␊
1291# define RADEON_FORCEON_AIC (1 << 21)␊
1292# define R300_DISABLE_MC_MCLKA (1 << 21)␊
1293# define R300_DISABLE_MC_MCLKB (1 << 21)␊
1294#define RADEON_MCLK_MISC 0x001f /* PLL */␊
1295# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)␊
1296# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)␊
1297# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)␊
1298# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)␊
1299#define RADEON_LCD_GPIO_MASK 0x01a0␊
1300#define RADEON_GPIOPAD_EN 0x01a0␊
1301#define RADEON_LCD_GPIO_Y_REG 0x01a4␊
1302#define RADEON_MDGPIO_A_REG 0x01ac␊
1303#define RADEON_MDGPIO_EN_REG 0x01b0␊
1304#define RADEON_MDGPIO_MASK 0x0198␊
1305#define RADEON_GPIOPAD_MASK 0x0198␊
1306#define RADEON_GPIOPAD_A␉␉ 0x019c␊
1307#define RADEON_MDGPIO_Y_REG 0x01b4␊
1308#define RADEON_MEM_ADDR_CONFIG 0x0148␊
1309#define RADEON_MEM_BASE 0x0f10 /* PCI */␊
1310#define RADEON_MEM_CNTL 0x0140␊
1311# define RADEON_MEM_NUM_CHANNELS_MASK 0x01␊
1312# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)␊
1313# define RV100_HALF_MODE (1 << 3)␊
1314# define R300_MEM_NUM_CHANNELS_MASK 0x03␊
1315# define R300_MEM_USE_CD_CH_ONLY (1 << 2)␊
1316#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */␊
1317#define RADEON_MEM_INIT_LAT_TIMER 0x0154␊
1318#define RADEON_MEM_INTF_CNTL 0x014c␊
1319#define RADEON_MEM_SDRAM_MODE_REG 0x0158␊
1320# define RADEON_SDRAM_MODE_MASK 0xffff0000␊
1321# define RADEON_B3MEM_RESET_MASK 0x6fffffff␊
1322# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)␊
1323#define RADEON_MEM_STR_CNTL 0x0150␊
1324# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)␊
1325# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)␊
1326# define R300_MEM_PWRUP_COMPL_C (1 << 2)␊
1327# define R300_MEM_PWRUP_COMPL_D (1 << 3)␊
1328# define RADEON_MEM_PWRUP_COMPLETE 0x03␊
1329# define R300_MEM_PWRUP_COMPLETE 0x0f␊
1330#define RADEON_MC_STATUS 0x0150␊
1331# define RADEON_MC_IDLE (1 << 2)␊
1332# define R300_MC_IDLE (1 << 4)␊
1333#define RADEON_MEM_VGA_RP_SEL 0x003c␊
1334#define RADEON_MEM_VGA_WP_SEL 0x0038␊
1335#define RADEON_MIN_GRANT 0x0f3e /* PCI */␊
1336#define RADEON_MM_DATA 0x0004␊
1337#define RADEON_MM_INDEX 0x0000␊
1338#define RADEON_MPLL_CNTL 0x000e /* PLL */␊
1339#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */␊
1340#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */␊
1341#define RADEON_SEPROM_CNTL1 0x01c0␊
1342# define RADEON_SCK_PRESCALE_SHIFT 24␊
1343# define RADEON_SCK_PRESCALE_MASK (0xff << 24)␊
1344#define R300_MC_IND_INDEX 0x01f8␊
1345# define R300_MC_IND_ADDR_MASK 0x3f␊
1346# define R300_MC_IND_WR_EN (1 << 8)␊
1347#define R300_MC_IND_DATA 0x01fc␊
1348#define R300_MC_READ_CNTL_AB 0x017c␊
1349# define R300_MEM_RBS_POSITION_A_MASK 0x03␊
1350#define R300_MC_READ_CNTL_CD_mcind␉ 0x24␊
1351# define R300_MEM_RBS_POSITION_C_MASK 0x03␊
1352␊
1353#define RADEON_N_VIF_COUNT 0x0248␊
1354␊
1355#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470␊
1356# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007␊
1357# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008␊
1358# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010␊
1359# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020␊
1360# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040␊
1361# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300␊
1362# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000␊
1363# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000␊
1364# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000␊
1365# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000␊
1366␊
1367#define RADEON_OV0_COLOUR_CNTL 0x04E0␊
1368#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474␊
1369#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408␊
1370# define RADEON_EXCL_HORZ_START_MASK 0x000000ff␊
1371# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00␊
1372# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000␊
1373# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000␊
1374#define RADEON_OV0_EXCLUSIVE_VERT 0x040C␊
1375# define RADEON_EXCL_VERT_START_MASK 0x000003ff␊
1376# define RADEON_EXCL_VERT_END_MASK 0x03ff0000␊
1377#define RADEON_OV0_FILTER_CNTL 0x04A0␊
1378# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0␊
1379# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1␊
1380# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2␊
1381# define RADEON_FILTER_HC_COEF_VERT_Y 0x4␊
1382# define RADEON_FILTER_HC_COEF_VERT_UV 0x8␊
1383# define RADEON_FILTER_HARDCODED_COEF 0xf␊
1384# define RADEON_FILTER_COEF_MASK 0xf␊
1385␊
1386#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0␊
1387#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4␊
1388#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8␊
1389#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC␊
1390#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0␊
1391#define RADEON_OV0_FLAG_CNTL 0x04DC␊
1392#define RADEON_OV0_GAMMA_000_00F 0x0d40␊
1393#define RADEON_OV0_GAMMA_010_01F 0x0d44␊
1394#define RADEON_OV0_GAMMA_020_03F 0x0d48␊
1395#define RADEON_OV0_GAMMA_040_07F 0x0d4c␊
1396#define RADEON_OV0_GAMMA_080_0BF 0x0e00␊
1397#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04␊
1398#define RADEON_OV0_GAMMA_100_13F 0x0e08␊
1399#define RADEON_OV0_GAMMA_140_17F 0x0e0c␊
1400#define RADEON_OV0_GAMMA_180_1BF 0x0e10␊
1401#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14␊
1402#define RADEON_OV0_GAMMA_200_23F 0x0e18␊
1403#define RADEON_OV0_GAMMA_240_27F 0x0e1c␊
1404#define RADEON_OV0_GAMMA_280_2BF 0x0e20␊
1405#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24␊
1406#define RADEON_OV0_GAMMA_300_33F 0x0e28␊
1407#define RADEON_OV0_GAMMA_340_37F 0x0e2c␊
1408#define RADEON_OV0_GAMMA_380_3BF 0x0d50␊
1409#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54␊
1410#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC␊
1411#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0␊
1412#define RADEON_OV0_H_INC 0x0480␊
1413#define RADEON_OV0_KEY_CNTL 0x04F4␊
1414# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L␊
1415# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L␊
1416# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L␊
1417# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L␊
1418# define RADEON_VIDEO_KEY_FN_NE 0x00000003L␊
1419# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L␊
1420# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L␊
1421# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L␊
1422# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L␊
1423# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L␊
1424# define RADEON_CMP_MIX_MASK 0x00000100L␊
1425# define RADEON_CMP_MIX_OR 0x00000000L␊
1426# define RADEON_CMP_MIX_AND 0x00000100L␊
1427#define RADEON_OV0_LIN_TRANS_A 0x0d20␊
1428#define RADEON_OV0_LIN_TRANS_B 0x0d24␊
1429#define RADEON_OV0_LIN_TRANS_C 0x0d28␊
1430#define RADEON_OV0_LIN_TRANS_D 0x0d2c␊
1431#define RADEON_OV0_LIN_TRANS_E 0x0d30␊
1432#define RADEON_OV0_LIN_TRANS_F 0x0d34␊
1433#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430␊
1434# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL␊
1435# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L␊
1436#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488␊
1437#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428␊
1438# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L␊
1439# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L␊
1440#define RADEON_OV0_P1_X_START_END 0x0494␊
1441#define RADEON_OV0_P2_X_START_END 0x0498␊
1442#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434␊
1443# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL␊
1444# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L␊
1445#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C␊
1446#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C␊
1447#define RADEON_OV0_P3_X_START_END 0x049C␊
1448#define RADEON_OV0_REG_LOAD_CNTL 0x0410␊
1449# define RADEON_REG_LD_CTL_LOCK 0x00000001L␊
1450# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L␊
1451# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L␊
1452# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L␊
1453# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L␊
1454#define RADEON_OV0_SCALE_CNTL 0x0420␊
1455# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L␊
1456# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L␊
1457# define RADEON_SCALER_SIGNED_UV 0x00000010L␊
1458# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L␊
1459# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L␊
1460# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L␊
1461# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L␊
1462# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L␊
1463# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L␊
1464# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L␊
1465# define RADEON_SCALER_SOURCE_15BPP 0x00000300L␊
1466# define RADEON_SCALER_SOURCE_16BPP 0x00000400L␊
1467# define RADEON_SCALER_SOURCE_32BPP 0x00000600L␊
1468# define RADEON_SCALER_SOURCE_YUV9 0x00000900L␊
1469# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L␊
1470# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L␊
1471# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L␊
1472# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L␊
1473# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L␊
1474# define RADEON_SCALER_CRTC_SEL 0x00004000L␊
1475# define RADEON_SCALER_SMART_SWITCH 0x00008000L␊
1476# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L␊
1477# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L␊
1478# define RADEON_SCALER_DIS_LIMIT 0x08000000L␊
1479# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L␊
1480# define RADEON_SCALER_INT_EMU 0x20000000L␊
1481# define RADEON_SCALER_ENABLE 0x40000000L␊
1482# define RADEON_SCALER_SOFT_RESET 0x80000000L␊
1483#define RADEON_OV0_STEP_BY 0x0484␊
1484#define RADEON_OV0_TEST 0x04F8␊
1485#define RADEON_OV0_V_INC 0x0424␊
1486#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460␊
1487#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464␊
1488#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440␊
1489# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L␊
1490# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L␊
1491# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L␊
1492# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L␊
1493#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444␊
1494# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L␊
1495# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L␊
1496# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L␊
1497# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L␊
1498#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448␊
1499# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L␊
1500# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L␊
1501# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L␊
1502# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L␊
1503#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C␊
1504#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450␊
1505#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454␊
1506#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8␊
1507#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4␊
1508#define RADEON_OV0_Y_X_START 0x0400␊
1509#define RADEON_OV0_Y_X_END 0x0404␊
1510#define RADEON_OV1_Y_X_START 0x0600␊
1511#define RADEON_OV1_Y_X_END 0x0604␊
1512#define RADEON_OVR_CLR 0x0230␊
1513#define RADEON_OVR_WID_LEFT_RIGHT 0x0234␊
1514#define RADEON_OVR_WID_TOP_BOTTOM 0x0238␊
1515␊
1516/* first capture unit */␊
1517␊
1518#define RADEON_CAP0_BUF0_OFFSET 0x0920␊
1519#define RADEON_CAP0_BUF1_OFFSET 0x0924␊
1520#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928␊
1521#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C␊
1522␊
1523#define RADEON_CAP0_BUF_PITCH 0x0930␊
1524#define RADEON_CAP0_V_WINDOW 0x0934␊
1525#define RADEON_CAP0_H_WINDOW 0x0938␊
1526#define RADEON_CAP0_VBI0_OFFSET 0x093C␊
1527#define RADEON_CAP0_VBI1_OFFSET 0x0940␊
1528#define RADEON_CAP0_VBI_V_WINDOW 0x0944␊
1529#define RADEON_CAP0_VBI_H_WINDOW 0x0948␊
1530#define RADEON_CAP0_PORT_MODE_CNTL 0x094C␊
1531#define RADEON_CAP0_TRIG_CNTL 0x0950␊
1532#define RADEON_CAP0_DEBUG 0x0954␊
1533#define RADEON_CAP0_CONFIG 0x0958␊
1534# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001␊
1535# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002␊
1536# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004␊
1537# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008␊
1538# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010␊
1539# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020␊
1540# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040␊
1541# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080␊
1542# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100␊
1543# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200␊
1544# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400␊
1545# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800␊
1546# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000␊
1547# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000␊
1548# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000␊
1549# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000␊
1550# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000␊
1551# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000␊
1552# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000␊
1553# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000␊
1554# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000␊
1555# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000␊
1556# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000␊
1557# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000␊
1558# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000␊
1559# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000␊
1560# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000␊
1561# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000␊
1562# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000␊
1563# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000␊
1564# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000␊
1565# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000␊
1566# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000␊
1567#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C␊
1568#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960␊
1569#define RADEON_CAP0_ANC_H_WINDOW 0x0964␊
1570#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968␊
1571#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C␊
1572#define RADEON_CAP0_BUF_STATUS 0x0970␊
1573/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */␊
1574/* #define RADEON_CAP0_XSHARPNESS 0x097C */␊
1575#define RADEON_CAP0_VBI2_OFFSET 0x0980␊
1576#define RADEON_CAP0_VBI3_OFFSET 0x0984␊
1577#define RADEON_CAP0_ANC2_OFFSET 0x0988␊
1578#define RADEON_CAP0_ANC3_OFFSET 0x098C␊
1579#define RADEON_VID_BUFFER_CONTROL 0x0900␊
1580␊
1581/* second capture unit */␊
1582␊
1583#define RADEON_CAP1_BUF0_OFFSET 0x0990␊
1584#define RADEON_CAP1_BUF1_OFFSET 0x0994␊
1585#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998␊
1586#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C␊
1587␊
1588#define RADEON_CAP1_BUF_PITCH 0x09A0␊
1589#define RADEON_CAP1_V_WINDOW 0x09A4␊
1590#define RADEON_CAP1_H_WINDOW 0x09A8␊
1591#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC␊
1592#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0␊
1593#define RADEON_CAP1_VBI_V_WINDOW 0x09B4␊
1594#define RADEON_CAP1_VBI_H_WINDOW 0x09B8␊
1595#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC␊
1596#define RADEON_CAP1_TRIG_CNTL 0x09C0␊
1597#define RADEON_CAP1_DEBUG 0x09C4␊
1598#define RADEON_CAP1_CONFIG 0x09C8␊
1599#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC␊
1600#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0␊
1601#define RADEON_CAP1_ANC_H_WINDOW 0x09D4␊
1602#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8␊
1603#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC␊
1604#define RADEON_CAP1_BUF_STATUS 0x09E0␊
1605#define RADEON_CAP1_DWNSC_XRATIO 0x09E8␊
1606#define RADEON_CAP1_XSHARPNESS 0x09EC␊
1607␊
1608/* misc multimedia registers */␊
1609␊
1610#define RADEON_IDCT_RUNS 0x1F80␊
1611#define RADEON_IDCT_LEVELS 0x1F84␊
1612#define RADEON_IDCT_CONTROL 0x1FBC␊
1613#define RADEON_IDCT_AUTH_CONTROL 0x1F88␊
1614#define RADEON_IDCT_AUTH 0x1F8C␊
1615␊
1616#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */␊
1617# define RADEON_P2PLL_RESET (1 << 0)␊
1618# define RADEON_P2PLL_SLEEP (1 << 1)␊
1619# define RADEON_P2PLL_PVG_MASK (7 << 11)␊
1620# define RADEON_P2PLL_PVG_SHIFT 11␊
1621# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)␊
1622# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)␊
1623# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)␊
1624#define RADEON_P2PLL_DIV_0 0x002c␊
1625# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff␊
1626# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000␊
1627#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */␊
1628# define RADEON_P2PLL_REF_DIV_MASK 0x03ff␊
1629# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */␊
1630# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */␊
1631# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)␊
1632# define R300_PPLL_REF_DIV_ACC_SHIFT 18␊
1633#define RADEON_PALETTE_DATA 0x00b4␊
1634#define RADEON_PALETTE_30_DATA 0x00b8␊
1635#define RADEON_PALETTE_INDEX 0x00b0␊
1636#define RADEON_PCI_GART_PAGE 0x017c␊
1637#define RADEON_PIXCLKS_CNTL 0x002d␊
1638# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03␊
1639# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00␊
1640# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01␊
1641# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02␊
1642# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03␊
1643# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)␊
1644# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)␊
1645# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)␊
1646# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)␊
1647# define R300_DVOCLK_ALWAYS_ONb (1 << 10)␊
1648# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)␊
1649# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)␊
1650# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)␊
1651# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)␊
1652# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)␊
1653# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)␊
1654# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)␊
1655# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)␊
1656# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)␊
1657# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)␊
1658# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)␊
1659#define RADEON_PLANE_3D_MASK_C 0x1d44␊
1660#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */␊
1661# define RADEON_PLL_MASK_READ_B (1 << 9)␊
1662#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */␊
1663#define RADEON_PMI_DATA 0x0f63 /* PCI */␊
1664#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */␊
1665#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */␊
1666#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */␊
1667#define RADEON_PMI_REGISTER 0x0f5c /* PCI */␊
1668#define RADEON_PPLL_CNTL 0x0002 /* PLL */␊
1669# define RADEON_PPLL_RESET (1 << 0)␊
1670# define RADEON_PPLL_SLEEP (1 << 1)␊
1671# define RADEON_PPLL_PVG_MASK (7 << 11)␊
1672# define RADEON_PPLL_PVG_SHIFT 11␊
1673# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)␊
1674# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)␊
1675# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)␊
1676#define RADEON_PPLL_DIV_0 0x0004 /* PLL */␊
1677#define RADEON_PPLL_DIV_1 0x0005 /* PLL */␊
1678#define RADEON_PPLL_DIV_2 0x0006 /* PLL */␊
1679#define RADEON_PPLL_DIV_3 0x0007 /* PLL */␊
1680# define RADEON_PPLL_FB3_DIV_MASK 0x07ff␊
1681# define RADEON_PPLL_POST3_DIV_MASK 0x00070000␊
1682#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */␊
1683# define RADEON_PPLL_REF_DIV_MASK 0x03ff␊
1684# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */␊
1685# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */␊
1686#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */␊
1687␊
1688#define RADEON_RBBM_GUICNTL 0x172c␊
1689# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)␊
1690# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)␊
1691# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)␊
1692# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)␊
1693#define RADEON_RBBM_SOFT_RESET 0x00f0␊
1694# define RADEON_SOFT_RESET_CP (1 << 0)␊
1695# define RADEON_SOFT_RESET_HI (1 << 1)␊
1696# define RADEON_SOFT_RESET_SE (1 << 2)␊
1697# define RADEON_SOFT_RESET_RE (1 << 3)␊
1698# define RADEON_SOFT_RESET_PP (1 << 4)␊
1699# define RADEON_SOFT_RESET_E2 (1 << 5)␊
1700# define RADEON_SOFT_RESET_RB (1 << 6)␊
1701# define RADEON_SOFT_RESET_HDP (1 << 7)␊
1702#define RADEON_RBBM_STATUS 0x0e40␊
1703# define RADEON_RBBM_FIFOCNT_MASK 0x007f␊
1704# define RADEON_RBBM_ACTIVE (1 << 31)␊
1705#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c␊
1706# define RADEON_RB2D_DC_FLUSH (3 << 0)␊
1707# define RADEON_RB2D_DC_FREE (3 << 2)␊
1708# define RADEON_RB2D_DC_FLUSH_ALL 0xf␊
1709# define RADEON_RB2D_DC_BUSY (1 << 31)␊
1710#define RADEON_RB2D_DSTCACHE_MODE 0x3428␊
1711#define RADEON_DSTCACHE_CTLSTAT 0x1714␊
1712␊
1713#define RADEON_RB3D_ZCACHE_MODE 0x3250␊
1714#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254␊
1715# define RADEON_RB3D_ZC_FLUSH_ALL 0x5␊
1716#define RADEON_RB3D_DSTCACHE_MODE 0x3258␊
1717# define RADEON_RB3D_DC_CACHE_ENABLE (0)␊
1718# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)␊
1719# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)␊
1720# define RADEON_RB3D_DC_CACHE_DISABLE (3)␊
1721# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)␊
1722# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)␊
1723# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)␊
1724# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)␊
1725# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)␊
1726# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)␊
1727# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)␊
1728# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)␊
1729# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)␊
1730␊
1731#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C␊
1732# define RADEON_RB3D_DC_FLUSH (3 << 0)␊
1733# define RADEON_RB3D_DC_FREE (3 << 2)␊
1734# define RADEON_RB3D_DC_FLUSH_ALL 0xf␊
1735# define RADEON_RB3D_DC_BUSY (1 << 31)␊
1736␊
1737#define RADEON_REG_BASE 0x0f18 /* PCI */␊
1738#define RADEON_REGPROG_INF 0x0f09 /* PCI */␊
1739#define RADEON_REVISION_ID 0x0f08 /* PCI */␊
1740␊
1741#define RADEON_SC_BOTTOM 0x164c␊
1742#define RADEON_SC_BOTTOM_RIGHT 0x16f0␊
1743#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c␊
1744#define RADEON_SC_LEFT 0x1640␊
1745#define RADEON_SC_RIGHT 0x1644␊
1746#define RADEON_SC_TOP 0x1648␊
1747#define RADEON_SC_TOP_LEFT 0x16ec␊
1748#define RADEON_SC_TOP_LEFT_C 0x1c88␊
1749# define RADEON_SC_SIGN_MASK_LO 0x8000␊
1750# define RADEON_SC_SIGN_MASK_HI 0x80000000␊
1751#define RADEON_SCLK_CNTL 0x000d /* PLL */␊
1752# define RADEON_SCLK_SRC_SEL_MASK 0x0007␊
1753# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8␊
1754# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008␊
1755# define RADEON_SCLK_FORCEON_MASK 0xffff8000␊
1756# define RADEON_SCLK_FORCE_DISP2 (1<<15)␊
1757# define RADEON_SCLK_FORCE_CP (1<<16)␊
1758# define RADEON_SCLK_FORCE_HDP (1<<17)␊
1759# define RADEON_SCLK_FORCE_DISP1 (1<<18)␊
1760# define RADEON_SCLK_FORCE_TOP (1<<19)␊
1761# define RADEON_SCLK_FORCE_E2 (1<<20)␊
1762# define RADEON_SCLK_FORCE_SE (1<<21)␊
1763# define RADEON_SCLK_FORCE_IDCT (1<<22)␊
1764# define RADEON_SCLK_FORCE_VIP (1<<23)␊
1765# define RADEON_SCLK_FORCE_RE (1<<24)␊
1766# define RADEON_SCLK_FORCE_PB (1<<25)␊
1767# define RADEON_SCLK_FORCE_TAM (1<<26)␊
1768# define RADEON_SCLK_FORCE_TDM (1<<27)␊
1769# define RADEON_SCLK_FORCE_RB (1<<28)␊
1770# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)␊
1771# define RADEON_SCLK_FORCE_SUBPIC (1<<30)␊
1772# define RADEON_SCLK_FORCE_OV0 (1<<31)␊
1773# define R300_SCLK_FORCE_VAP (1<<21)␊
1774# define R300_SCLK_FORCE_SR (1<<25)␊
1775# define R300_SCLK_FORCE_PX (1<<26)␊
1776# define R300_SCLK_FORCE_TX (1<<27)␊
1777# define R300_SCLK_FORCE_US (1<<28)␊
1778# define R300_SCLK_FORCE_SU (1<<30)␊
1779#define R300_SCLK_CNTL2 0x1e /* PLL */␊
1780# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)␊
1781# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)␊
1782# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)␊
1783# define R300_SCLK_FORCE_TCL (1<<13)␊
1784# define R300_SCLK_FORCE_CBA (1<<14)␊
1785# define R300_SCLK_FORCE_GA (1<<15)␊
1786#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */␊
1787# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007␊
1788# define RADEON_SCLK_MORE_FORCEON 0x0700␊
1789#define RADEON_SDRAM_MODE_REG 0x0158␊
1790#define RADEON_SEQ8_DATA 0x03c5 /* VGA */␊
1791#define RADEON_SEQ8_IDX 0x03c4 /* VGA */␊
1792#define RADEON_SNAPSHOT_F_COUNT 0x0244␊
1793#define RADEON_SNAPSHOT_VH_COUNTS 0x0240␊
1794#define RADEON_SNAPSHOT_VIF_COUNT 0x024c␊
1795#define RADEON_SRC_OFFSET 0x15ac␊
1796#define RADEON_SRC_PITCH 0x15b0␊
1797#define RADEON_SRC_PITCH_OFFSET 0x1428␊
1798#define RADEON_SRC_SC_BOTTOM 0x165c␊
1799#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4␊
1800#define RADEON_SRC_SC_RIGHT 0x1654␊
1801#define RADEON_SRC_X 0x1414␊
1802#define RADEON_SRC_X_Y 0x1590␊
1803#define RADEON_SRC_Y 0x1418␊
1804#define RADEON_SRC_Y_X 0x1434␊
1805#define RADEON_STATUS 0x0f06 /* PCI */␊
1806#define RADEON_SUBPIC_CNTL 0x0540 /* ? */␊
1807#define RADEON_SUB_CLASS 0x0f0a /* PCI */␊
1808#define RADEON_SURFACE_CNTL 0x0b00␊
1809# define RADEON_SURF_TRANSLATION_DIS (1 << 8)␊
1810# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)␊
1811# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)␊
1812# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)␊
1813# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)␊
1814#define RADEON_SURFACE0_INFO 0x0b0c␊
1815# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)␊
1816# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)␊
1817# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)␊
1818# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)␊
1819# define R200_SURF_TILE_NONE (0 << 16)␊
1820# define R200_SURF_TILE_COLOR_MACRO (1 << 16)␊
1821# define R200_SURF_TILE_COLOR_MICRO (2 << 16)␊
1822# define R200_SURF_TILE_COLOR_BOTH (3 << 16)␊
1823# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)␊
1824# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)␊
1825# define R300_SURF_TILE_NONE (0 << 16)␊
1826# define R300_SURF_TILE_COLOR_MACRO (1 << 16)␊
1827# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)␊
1828# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)␊
1829# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)␊
1830# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)␊
1831# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)␊
1832#define RADEON_SURFACE0_LOWER_BOUND 0x0b04␊
1833#define RADEON_SURFACE0_UPPER_BOUND 0x0b08␊
1834#define RADEON_SURFACE1_INFO 0x0b1c␊
1835#define RADEON_SURFACE1_LOWER_BOUND 0x0b14␊
1836#define RADEON_SURFACE1_UPPER_BOUND 0x0b18␊
1837#define RADEON_SURFACE2_INFO 0x0b2c␊
1838#define RADEON_SURFACE2_LOWER_BOUND 0x0b24␊
1839#define RADEON_SURFACE2_UPPER_BOUND 0x0b28␊
1840#define RADEON_SURFACE3_INFO 0x0b3c␊
1841#define RADEON_SURFACE3_LOWER_BOUND 0x0b34␊
1842#define RADEON_SURFACE3_UPPER_BOUND 0x0b38␊
1843#define RADEON_SURFACE4_INFO 0x0b4c␊
1844#define RADEON_SURFACE4_LOWER_BOUND 0x0b44␊
1845#define RADEON_SURFACE4_UPPER_BOUND 0x0b48␊
1846#define RADEON_SURFACE5_INFO 0x0b5c␊
1847#define RADEON_SURFACE5_LOWER_BOUND 0x0b54␊
1848#define RADEON_SURFACE5_UPPER_BOUND 0x0b58␊
1849#define RADEON_SURFACE6_INFO 0x0b6c␊
1850#define RADEON_SURFACE6_LOWER_BOUND 0x0b64␊
1851#define RADEON_SURFACE6_UPPER_BOUND 0x0b68␊
1852#define RADEON_SURFACE7_INFO 0x0b7c␊
1853#define RADEON_SURFACE7_LOWER_BOUND 0x0b74␊
1854#define RADEON_SURFACE7_UPPER_BOUND 0x0b78␊
1855#define RADEON_SW_SEMAPHORE 0x013c␊
1856␊
1857#define RADEON_TEST_DEBUG_CNTL 0x0120␊
1858#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001␊
1859␊
1860#define RADEON_TEST_DEBUG_MUX 0x0124␊
1861#define RADEON_TEST_DEBUG_OUT 0x012c␊
1862#define RADEON_TMDS_PLL_CNTL 0x02a8␊
1863#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4␊
1864# define RADEON_TMDS_TRANSMITTER_PLLEN 1␊
1865# define RADEON_TMDS_TRANSMITTER_PLLRST 2␊
1866#define RADEON_TRAIL_BRES_DEC 0x1614␊
1867#define RADEON_TRAIL_BRES_ERR 0x160c␊
1868#define RADEON_TRAIL_BRES_INC 0x1610␊
1869#define RADEON_TRAIL_X 0x1618␊
1870#define RADEON_TRAIL_X_SUB 0x1620␊
1871␊
1872#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */␊
1873# define RADEON_VCLK_SRC_SEL_MASK 0x03␊
1874# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00␊
1875# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01␊
1876# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02␊
1877# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03␊
1878# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)␊
1879# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)␊
1880# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)␊
1881␊
1882#define RADEON_VENDOR_ID 0x0f00 /* PCI */␊
1883#define RADEON_VGA_DDA_CONFIG 0x02e8␊
1884#define RADEON_VGA_DDA_ON_OFF 0x02ec␊
1885#define RADEON_VID_BUFFER_CONTROL 0x0900␊
1886#define RADEON_VIDEOMUX_CNTL 0x0190␊
1887␊
1888 /* VIP bus */␊
1889#define RADEON_VIPH_CH0_DATA 0x0c00␊
1890#define RADEON_VIPH_CH1_DATA 0x0c04␊
1891#define RADEON_VIPH_CH2_DATA 0x0c08␊
1892#define RADEON_VIPH_CH3_DATA 0x0c0c␊
1893#define RADEON_VIPH_CH0_ADDR 0x0c10␊
1894#define RADEON_VIPH_CH1_ADDR 0x0c14␊
1895#define RADEON_VIPH_CH2_ADDR 0x0c18␊
1896#define RADEON_VIPH_CH3_ADDR 0x0c1c␊
1897#define RADEON_VIPH_CH0_SBCNT 0x0c20␊
1898#define RADEON_VIPH_CH1_SBCNT 0x0c24␊
1899#define RADEON_VIPH_CH2_SBCNT 0x0c28␊
1900#define RADEON_VIPH_CH3_SBCNT 0x0c2c␊
1901#define RADEON_VIPH_CH0_ABCNT 0x0c30␊
1902#define RADEON_VIPH_CH1_ABCNT 0x0c34␊
1903#define RADEON_VIPH_CH2_ABCNT 0x0c38␊
1904#define RADEON_VIPH_CH3_ABCNT 0x0c3c␊
1905#define RADEON_VIPH_CONTROL 0x0c40␊
1906# define RADEON_VIP_BUSY 0␊
1907# define RADEON_VIP_IDLE 1␊
1908# define RADEON_VIP_RESET 2␊
1909# define RADEON_VIPH_EN (1 << 21)␊
1910#define RADEON_VIPH_DV_LAT 0x0c44␊
1911#define RADEON_VIPH_BM_CHUNK 0x0c48␊
1912#define RADEON_VIPH_DV_INT 0x0c4c␊
1913#define RADEON_VIPH_TIMEOUT_STAT 0x0c50␊
1914#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010␊
1915#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010␊
1916#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000␊
1917␊
1918#define RADEON_VIPH_REG_DATA 0x0084␊
1919#define RADEON_VIPH_REG_ADDR 0x0080␊
1920␊
1921␊
1922#define RADEON_WAIT_UNTIL 0x1720␊
1923# define RADEON_WAIT_CRTC_PFLIP (1 << 0)␊
1924# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)␊
1925# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)␊
1926# define RADEON_WAIT_CRTC_VLINE (1 << 3)␊
1927# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)␊
1928# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)␊
1929# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */␊
1930# define RADEON_WAIT_OV0_FLIP (1 << 11)␊
1931# define RADEON_WAIT_AGP_FLUSH (1 << 13)␊
1932# define RADEON_WAIT_2D_IDLE (1 << 14)␊
1933# define RADEON_WAIT_3D_IDLE (1 << 15)␊
1934# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)␊
1935# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)␊
1936# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)␊
1937# define RADEON_CMDFIFO_ENTRIES_SHIFT 10␊
1938# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f␊
1939# define RADEON_WAIT_VAP_IDLE (1 << 28)␊
1940# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)␊
1941# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)␊
1942# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)␊
1943␊
1944#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */␊
1945#define RADEON_XCLK_CNTL 0x000d /* PLL */␊
1946#define RADEON_XDLL_CNTL 0x000c /* PLL */␊
1947#define RADEON_XPLL_CNTL 0x000b /* PLL */␊
1948␊
1949␊
1950␊
1951␉␉␉␉/* Registers for 3D/TCL */␊
1952#define RADEON_PP_BORDER_COLOR_0 0x1d40␊
1953#define RADEON_PP_BORDER_COLOR_1 0x1d44␊
1954#define RADEON_PP_BORDER_COLOR_2 0x1d48␊
1955#define RADEON_PP_CNTL 0x1c38␊
1956# define RADEON_STIPPLE_ENABLE (1 << 0)␊
1957# define RADEON_SCISSOR_ENABLE (1 << 1)␊
1958# define RADEON_PATTERN_ENABLE (1 << 2)␊
1959# define RADEON_SHADOW_ENABLE (1 << 3)␊
1960# define RADEON_TEX_ENABLE_MASK (0xf << 4)␊
1961# define RADEON_TEX_0_ENABLE (1 << 4)␊
1962# define RADEON_TEX_1_ENABLE (1 << 5)␊
1963# define RADEON_TEX_2_ENABLE (1 << 6)␊
1964# define RADEON_TEX_3_ENABLE (1 << 7)␊
1965# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)␊
1966# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)␊
1967# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)␊
1968# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)␊
1969# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)␊
1970# define RADEON_PLANAR_YUV_ENABLE (1 << 20)␊
1971# define RADEON_SPECULAR_ENABLE (1 << 21)␊
1972# define RADEON_FOG_ENABLE (1 << 22)␊
1973# define RADEON_ALPHA_TEST_ENABLE (1 << 23)␊
1974# define RADEON_ANTI_ALIAS_NONE (0 << 24)␊
1975# define RADEON_ANTI_ALIAS_LINE (1 << 24)␊
1976# define RADEON_ANTI_ALIAS_POLY (2 << 24)␊
1977# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)␊
1978# define RADEON_BUMP_MAP_ENABLE (1 << 26)␊
1979# define RADEON_BUMPED_MAP_T0 (0 << 27)␊
1980# define RADEON_BUMPED_MAP_T1 (1 << 27)␊
1981# define RADEON_BUMPED_MAP_T2 (2 << 27)␊
1982# define RADEON_TEX_3D_ENABLE_0 (1 << 29)␊
1983# define RADEON_TEX_3D_ENABLE_1 (1 << 30)␊
1984# define RADEON_MC_ENABLE (1 << 31)␊
1985#define RADEON_PP_FOG_COLOR 0x1c18␊
1986# define RADEON_FOG_COLOR_MASK 0x00ffffff␊
1987# define RADEON_FOG_VERTEX (0 << 24)␊
1988# define RADEON_FOG_TABLE (1 << 24)␊
1989# define RADEON_FOG_USE_DEPTH (0 << 25)␊
1990# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)␊
1991# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)␊
1992#define RADEON_PP_LUM_MATRIX 0x1d00␊
1993#define RADEON_PP_MISC 0x1c14␊
1994# define RADEON_REF_ALPHA_MASK 0x000000ff␊
1995# define RADEON_ALPHA_TEST_FAIL (0 << 8)␊
1996# define RADEON_ALPHA_TEST_LESS (1 << 8)␊
1997# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)␊
1998# define RADEON_ALPHA_TEST_EQUAL (3 << 8)␊
1999# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)␊
2000# define RADEON_ALPHA_TEST_GREATER (5 << 8)␊
2001# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)␊
2002# define RADEON_ALPHA_TEST_PASS (7 << 8)␊
2003# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)␊
2004# define RADEON_CHROMA_FUNC_FAIL (0 << 16)␊
2005# define RADEON_CHROMA_FUNC_PASS (1 << 16)␊
2006# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)␊
2007# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)␊
2008# define RADEON_CHROMA_KEY_NEAREST (0 << 18)␊
2009# define RADEON_CHROMA_KEY_ZERO (1 << 18)␊
2010# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)␊
2011# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)␊
2012# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)␊
2013# define RADEON_SHADOW_PASS_1 (0 << 22)␊
2014# define RADEON_SHADOW_PASS_2 (1 << 22)␊
2015# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)␊
2016# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)␊
2017#define RADEON_PP_ROT_MATRIX_0 0x1d58␊
2018#define RADEON_PP_ROT_MATRIX_1 0x1d5c␊
2019#define RADEON_PP_TXFILTER_0 0x1c54␊
2020#define RADEON_PP_TXFILTER_1 0x1c6c␊
2021#define RADEON_PP_TXFILTER_2 0x1c84␊
2022# define RADEON_MAG_FILTER_NEAREST (0 << 0)␊
2023# define RADEON_MAG_FILTER_LINEAR (1 << 0)␊
2024# define RADEON_MAG_FILTER_MASK (1 << 0)␊
2025# define RADEON_MIN_FILTER_NEAREST (0 << 1)␊
2026# define RADEON_MIN_FILTER_LINEAR (1 << 1)␊
2027# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)␊
2028# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)␊
2029# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)␊
2030# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)␊
2031# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)␊
2032# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)␊
2033# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)␊
2034# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)␊
2035# define RADEON_MIN_FILTER_MASK (15 << 1)␊
2036# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)␊
2037# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)␊
2038# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)␊
2039# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)␊
2040# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)␊
2041# define RADEON_MAX_ANISO_MASK (7 << 5)␊
2042# define RADEON_LOD_BIAS_MASK (0xff << 8)␊
2043# define RADEON_LOD_BIAS_SHIFT 8␊
2044# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)␊
2045# define RADEON_MAX_MIP_LEVEL_SHIFT 16␊
2046# define RADEON_YUV_TO_RGB (1 << 20)␊
2047# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)␊
2048# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)␊
2049# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)␊
2050# define RADEON_WRAPEN_S (1 << 22)␊
2051# define RADEON_CLAMP_S_WRAP (0 << 23)␊
2052# define RADEON_CLAMP_S_MIRROR (1 << 23)␊
2053# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)␊
2054# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)␊
2055# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)␊
2056# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)␊
2057# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)␊
2058# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)␊
2059# define RADEON_CLAMP_S_MASK (7 << 23)␊
2060# define RADEON_WRAPEN_T (1 << 26)␊
2061# define RADEON_CLAMP_T_WRAP (0 << 27)␊
2062# define RADEON_CLAMP_T_MIRROR (1 << 27)␊
2063# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)␊
2064# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)␊
2065# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)␊
2066# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)␊
2067# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)␊
2068# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)␊
2069# define RADEON_CLAMP_T_MASK (7 << 27)␊
2070# define RADEON_BORDER_MODE_OGL (0 << 31)␊
2071# define RADEON_BORDER_MODE_D3D (1 << 31)␊
2072#define RADEON_PP_TXFORMAT_0 0x1c58␊
2073#define RADEON_PP_TXFORMAT_1 0x1c70␊
2074#define RADEON_PP_TXFORMAT_2 0x1c88␊
2075# define RADEON_TXFORMAT_I8 (0 << 0)␊
2076# define RADEON_TXFORMAT_AI88 (1 << 0)␊
2077# define RADEON_TXFORMAT_RGB332 (2 << 0)␊
2078# define RADEON_TXFORMAT_ARGB1555 (3 << 0)␊
2079# define RADEON_TXFORMAT_RGB565 (4 << 0)␊
2080# define RADEON_TXFORMAT_ARGB4444 (5 << 0)␊
2081# define RADEON_TXFORMAT_ARGB8888 (6 << 0)␊
2082# define RADEON_TXFORMAT_RGBA8888 (7 << 0)␊
2083# define RADEON_TXFORMAT_Y8 (8 << 0)␊
2084# define RADEON_TXFORMAT_VYUY422 (10 << 0)␊
2085# define RADEON_TXFORMAT_YVYU422 (11 << 0)␊
2086# define RADEON_TXFORMAT_DXT1 (12 << 0)␊
2087# define RADEON_TXFORMAT_DXT23 (14 << 0)␊
2088# define RADEON_TXFORMAT_DXT45 (15 << 0)␊
2089# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)␊
2090# define RADEON_TXFORMAT_FORMAT_SHIFT 0␊
2091# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)␊
2092# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)␊
2093# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)␊
2094# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)␊
2095# define RADEON_TXFORMAT_WIDTH_SHIFT 8␊
2096# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)␊
2097# define RADEON_TXFORMAT_HEIGHT_SHIFT 12␊
2098# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)␊
2099# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16␊
2100# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)␊
2101# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20␊
2102# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)␊
2103# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)␊
2104# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)␊
2105# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)␊
2106# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)␊
2107# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)␊
2108# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)␊
2109# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)␊
2110# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)␊
2111# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)␊
2112# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)␊
2113# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)␊
2114#define RADEON_PP_CUBIC_FACES_0 0x1d24␊
2115#define RADEON_PP_CUBIC_FACES_1 0x1d28␊
2116#define RADEON_PP_CUBIC_FACES_2 0x1d2c␊
2117# define RADEON_FACE_WIDTH_1_SHIFT 0␊
2118# define RADEON_FACE_HEIGHT_1_SHIFT 4␊
2119# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)␊
2120# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)␊
2121# define RADEON_FACE_WIDTH_2_SHIFT 8␊
2122# define RADEON_FACE_HEIGHT_2_SHIFT 12␊
2123# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)␊
2124# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)␊
2125# define RADEON_FACE_WIDTH_3_SHIFT 16␊
2126# define RADEON_FACE_HEIGHT_3_SHIFT 20␊
2127# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)␊
2128# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)␊
2129# define RADEON_FACE_WIDTH_4_SHIFT 24␊
2130# define RADEON_FACE_HEIGHT_4_SHIFT 28␊
2131# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)␊
2132# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)␊
2133␊
2134#define RADEON_PP_TXOFFSET_0 0x1c5c␊
2135#define RADEON_PP_TXOFFSET_1 0x1c74␊
2136#define RADEON_PP_TXOFFSET_2 0x1c8c␊
2137# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)␊
2138# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)␊
2139# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)␊
2140# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)␊
2141# define RADEON_TXO_MACRO_LINEAR (0 << 2)␊
2142# define RADEON_TXO_MACRO_TILE (1 << 2)␊
2143# define RADEON_TXO_MICRO_LINEAR (0 << 3)␊
2144# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)␊
2145# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)␊
2146# define RADEON_TXO_OFFSET_MASK 0xffffffe0␊
2147# define RADEON_TXO_OFFSET_SHIFT 5␊
2148␊
2149#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */␊
2150#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4␊
2151#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8␊
2152#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc␊
2153#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0␊
2154#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00␊
2155#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04␊
2156#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08␊
2157#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c␊
2158#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10␊
2159#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14␊
2160#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18␊
2161#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c␊
2162#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20␊
2163#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24␊
2164␊
2165#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */␊
2166#define RADEON_PP_TEX_SIZE_1 0x1d0c␊
2167#define RADEON_PP_TEX_SIZE_2 0x1d14␊
2168# define RADEON_TEX_USIZE_MASK (0x7ff << 0)␊
2169# define RADEON_TEX_USIZE_SHIFT 0␊
2170# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)␊
2171# define RADEON_TEX_VSIZE_SHIFT 16␊
2172# define RADEON_SIGNED_RGB_MASK (1 << 30)␊
2173# define RADEON_SIGNED_RGB_SHIFT 30␊
2174# define RADEON_SIGNED_ALPHA_MASK (1 << 31)␊
2175# define RADEON_SIGNED_ALPHA_SHIFT 31␊
2176#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */␊
2177#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */␊
2178#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */␊
2179/* note: bits 13-5: 32 byte aligned stride of texture map */␊
2180␊
2181#define RADEON_PP_TXCBLEND_0 0x1c60␊
2182#define RADEON_PP_TXCBLEND_1 0x1c78␊
2183#define RADEON_PP_TXCBLEND_2 0x1c90␊
2184# define RADEON_COLOR_ARG_A_SHIFT 0␊
2185# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)␊
2186# define RADEON_COLOR_ARG_A_ZERO (0 << 0)␊
2187# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)␊
2188# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)␊
2189# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)␊
2190# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)␊
2191# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)␊
2192# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)␊
2193# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)␊
2194# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)␊
2195# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)␊
2196# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)␊
2197# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)␊
2198# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)␊
2199# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)␊
2200# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)␊
2201# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)␊
2202# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)␊
2203# define RADEON_COLOR_ARG_B_SHIFT 5␊
2204# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)␊
2205# define RADEON_COLOR_ARG_B_ZERO (0 << 5)␊
2206# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)␊
2207# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)␊
2208# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)␊
2209# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)␊
2210# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)␊
2211# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)␊
2212# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)␊
2213# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)␊
2214# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)␊
2215# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)␊
2216# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)␊
2217# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)␊
2218# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)␊
2219# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)␊
2220# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)␊
2221# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)␊
2222# define RADEON_COLOR_ARG_C_SHIFT 10␊
2223# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)␊
2224# define RADEON_COLOR_ARG_C_ZERO (0 << 10)␊
2225# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)␊
2226# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)␊
2227# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)␊
2228# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)␊
2229# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)␊
2230# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)␊
2231# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)␊
2232# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)␊
2233# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)␊
2234# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)␊
2235# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)␊
2236# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)␊
2237# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)␊
2238# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)␊
2239# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)␊
2240# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)␊
2241# define RADEON_COMP_ARG_A (1 << 15)␊
2242# define RADEON_COMP_ARG_A_SHIFT 15␊
2243# define RADEON_COMP_ARG_B (1 << 16)␊
2244# define RADEON_COMP_ARG_B_SHIFT 16␊
2245# define RADEON_COMP_ARG_C (1 << 17)␊
2246# define RADEON_COMP_ARG_C_SHIFT 17␊
2247# define RADEON_BLEND_CTL_MASK (7 << 18)␊
2248# define RADEON_BLEND_CTL_ADD (0 << 18)␊
2249# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)␊
2250# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)␊
2251# define RADEON_BLEND_CTL_BLEND (3 << 18)␊
2252# define RADEON_BLEND_CTL_DOT3 (4 << 18)␊
2253# define RADEON_SCALE_SHIFT 21␊
2254# define RADEON_SCALE_MASK (3 << 21)␊
2255# define RADEON_SCALE_1X (0 << 21)␊
2256# define RADEON_SCALE_2X (1 << 21)␊
2257# define RADEON_SCALE_4X (2 << 21)␊
2258# define RADEON_CLAMP_TX (1 << 23)␊
2259# define RADEON_T0_EQ_TCUR (1 << 24)␊
2260# define RADEON_T1_EQ_TCUR (1 << 25)␊
2261# define RADEON_T2_EQ_TCUR (1 << 26)␊
2262# define RADEON_T3_EQ_TCUR (1 << 27)␊
2263# define RADEON_COLOR_ARG_MASK 0x1f␊
2264# define RADEON_COMP_ARG_SHIFT 15␊
2265#define RADEON_PP_TXABLEND_0 0x1c64␊
2266#define RADEON_PP_TXABLEND_1 0x1c7c␊
2267#define RADEON_PP_TXABLEND_2 0x1c94␊
2268# define RADEON_ALPHA_ARG_A_SHIFT 0␊
2269# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)␊
2270# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)␊
2271# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)␊
2272# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)␊
2273# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)␊
2274# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)␊
2275# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)␊
2276# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)␊
2277# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)␊
2278# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)␊
2279# define RADEON_ALPHA_ARG_B_SHIFT 4␊
2280# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)␊
2281# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)␊
2282# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)␊
2283# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)␊
2284# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)␊
2285# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)␊
2286# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)␊
2287# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)␊
2288# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)␊
2289# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)␊
2290# define RADEON_ALPHA_ARG_C_SHIFT 8␊
2291# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)␊
2292# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)␊
2293# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)␊
2294# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)␊
2295# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)␊
2296# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)␊
2297# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)␊
2298# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)␊
2299# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)␊
2300# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)␊
2301# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)␊
2302# define RADEON_ALPHA_ARG_MASK 0xf␊
2303␊
2304#define RADEON_PP_TFACTOR_0 0x1c68␊
2305#define RADEON_PP_TFACTOR_1 0x1c80␊
2306#define RADEON_PP_TFACTOR_2 0x1c98␊
2307␊
2308#define RADEON_RB3D_BLENDCNTL 0x1c20␊
2309# define RADEON_COMB_FCN_MASK (3 << 12)␊
2310# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)␊
2311# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)␊
2312# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)␊
2313# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)␊
2314# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)␊
2315# define RADEON_SRC_BLEND_GL_ONE (33 << 16)␊
2316# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)␊
2317# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)␊
2318# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)␊
2319# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)␊
2320# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)␊
2321# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)␊
2322# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)␊
2323# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)␊
2324# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)␊
2325# define RADEON_SRC_BLEND_MASK (63 << 16)␊
2326# define RADEON_DST_BLEND_GL_ZERO (32 << 24)␊
2327# define RADEON_DST_BLEND_GL_ONE (33 << 24)␊
2328# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)␊
2329# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)␊
2330# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)␊
2331# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)␊
2332# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)␊
2333# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)␊
2334# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)␊
2335# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)␊
2336# define RADEON_DST_BLEND_MASK (63 << 24)␊
2337#define RADEON_RB3D_CNTL 0x1c3c␊
2338# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)␊
2339# define RADEON_PLANE_MASK_ENABLE (1 << 1)␊
2340# define RADEON_DITHER_ENABLE (1 << 2)␊
2341# define RADEON_ROUND_ENABLE (1 << 3)␊
2342# define RADEON_SCALE_DITHER_ENABLE (1 << 4)␊
2343# define RADEON_DITHER_INIT (1 << 5)␊
2344# define RADEON_ROP_ENABLE (1 << 6)␊
2345# define RADEON_STENCIL_ENABLE (1 << 7)␊
2346# define RADEON_Z_ENABLE (1 << 8)␊
2347# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)␊
2348# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)␊
2349# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)␊
2350# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)␊
2351# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)␊
2352# define RADEON_COLOR_FORMAT_Y8 (8 << 10)␊
2353# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)␊
2354# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)␊
2355# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)␊
2356# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)␊
2357# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)␊
2358# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)␊
2359#define RADEON_RB3D_COLOROFFSET 0x1c40␊
2360# define RADEON_COLOROFFSET_MASK 0xfffffff0␊
2361#define RADEON_RB3D_COLORPITCH 0x1c48␊
2362# define RADEON_COLORPITCH_MASK 0x000001ff8␊
2363# define RADEON_COLOR_TILE_ENABLE (1 << 16)␊
2364# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)␊
2365# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)␊
2366# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)␊
2367# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)␊
2368#define RADEON_RB3D_DEPTHOFFSET 0x1c24␊
2369#define RADEON_RB3D_DEPTHPITCH 0x1c28␊
2370# define RADEON_DEPTHPITCH_MASK 0x00001ff8␊
2371# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)␊
2372# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)␊
2373# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)␊
2374#define RADEON_RB3D_PLANEMASK 0x1d84␊
2375#define RADEON_RB3D_ROPCNTL 0x1d80␊
2376# define RADEON_ROP_MASK (15 << 8)␊
2377# define RADEON_ROP_CLEAR (0 << 8)␊
2378# define RADEON_ROP_NOR (1 << 8)␊
2379# define RADEON_ROP_AND_INVERTED (2 << 8)␊
2380# define RADEON_ROP_COPY_INVERTED (3 << 8)␊
2381# define RADEON_ROP_AND_REVERSE (4 << 8)␊
2382# define RADEON_ROP_INVERT (5 << 8)␊
2383# define RADEON_ROP_XOR (6 << 8)␊
2384# define RADEON_ROP_NAND (7 << 8)␊
2385# define RADEON_ROP_AND (8 << 8)␊
2386# define RADEON_ROP_EQUIV (9 << 8)␊
2387# define RADEON_ROP_NOOP (10 << 8)␊
2388# define RADEON_ROP_OR_INVERTED (11 << 8)␊
2389# define RADEON_ROP_COPY (12 << 8)␊
2390# define RADEON_ROP_OR_REVERSE (13 << 8)␊
2391# define RADEON_ROP_OR (14 << 8)␊
2392# define RADEON_ROP_SET (15 << 8)␊
2393#define RADEON_RB3D_STENCILREFMASK 0x1d7c␊
2394# define RADEON_STENCIL_REF_SHIFT 0␊
2395# define RADEON_STENCIL_REF_MASK (0xff << 0)␊
2396# define RADEON_STENCIL_MASK_SHIFT 16␊
2397# define RADEON_STENCIL_VALUE_MASK (0xff << 16)␊
2398# define RADEON_STENCIL_WRITEMASK_SHIFT 24␊
2399# define RADEON_STENCIL_WRITE_MASK (0xff << 24)␊
2400#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c␊
2401# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)␊
2402# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)␊
2403# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)␊
2404# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)␊
2405# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)␊
2406# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)␊
2407# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)␊
2408# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)␊
2409# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)␊
2410# define RADEON_Z_TEST_NEVER (0 << 4)␊
2411# define RADEON_Z_TEST_LESS (1 << 4)␊
2412# define RADEON_Z_TEST_LEQUAL (2 << 4)␊
2413# define RADEON_Z_TEST_EQUAL (3 << 4)␊
2414# define RADEON_Z_TEST_GEQUAL (4 << 4)␊
2415# define RADEON_Z_TEST_GREATER (5 << 4)␊
2416# define RADEON_Z_TEST_NEQUAL (6 << 4)␊
2417# define RADEON_Z_TEST_ALWAYS (7 << 4)␊
2418# define RADEON_Z_TEST_MASK (7 << 4)␊
2419# define RADEON_STENCIL_TEST_NEVER (0 << 12)␊
2420# define RADEON_STENCIL_TEST_LESS (1 << 12)␊
2421# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)␊
2422# define RADEON_STENCIL_TEST_EQUAL (3 << 12)␊
2423# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)␊
2424# define RADEON_STENCIL_TEST_GREATER (5 << 12)␊
2425# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)␊
2426# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)␊
2427# define RADEON_STENCIL_TEST_MASK (0x7 << 12)␊
2428# define RADEON_STENCIL_FAIL_KEEP (0 << 16)␊
2429# define RADEON_STENCIL_FAIL_ZERO (1 << 16)␊
2430# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)␊
2431# define RADEON_STENCIL_FAIL_INC (3 << 16)␊
2432# define RADEON_STENCIL_FAIL_DEC (4 << 16)␊
2433# define RADEON_STENCIL_FAIL_INVERT (5 << 16)␊
2434# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)␊
2435# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)␊
2436# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)␊
2437# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)␊
2438# define RADEON_STENCIL_ZPASS_INC (3 << 20)␊
2439# define RADEON_STENCIL_ZPASS_DEC (4 << 20)␊
2440# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)␊
2441# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)␊
2442# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)␊
2443# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)␊
2444# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)␊
2445# define RADEON_STENCIL_ZFAIL_INC (3 << 24)␊
2446# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)␊
2447# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)␊
2448# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)␊
2449# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)␊
2450# define RADEON_FORCE_Z_DIRTY (1 << 29)␊
2451# define RADEON_Z_WRITE_ENABLE (1 << 30)␊
2452#define RADEON_RE_LINE_PATTERN 0x1cd0␊
2453# define RADEON_LINE_PATTERN_MASK 0x0000ffff␊
2454# define RADEON_LINE_REPEAT_COUNT_SHIFT 16␊
2455# define RADEON_LINE_PATTERN_START_SHIFT 24␊
2456# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)␊
2457# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)␊
2458# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)␊
2459#define RADEON_RE_LINE_STATE 0x1cd4␊
2460# define RADEON_LINE_CURRENT_PTR_SHIFT 0␊
2461# define RADEON_LINE_CURRENT_COUNT_SHIFT 8␊
2462#define RADEON_RE_MISC 0x26c4␊
2463# define RADEON_STIPPLE_COORD_MASK 0x1f␊
2464# define RADEON_STIPPLE_X_OFFSET_SHIFT 0␊
2465# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)␊
2466# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8␊
2467# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)␊
2468# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)␊
2469# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)␊
2470#define RADEON_RE_SOLID_COLOR 0x1c1c␊
2471#define RADEON_RE_TOP_LEFT 0x26c0␊
2472# define RADEON_RE_LEFT_SHIFT 0␊
2473# define RADEON_RE_TOP_SHIFT 16␊
2474#define RADEON_RE_WIDTH_HEIGHT 0x1c44␊
2475# define RADEON_RE_WIDTH_SHIFT 0␊
2476# define RADEON_RE_HEIGHT_SHIFT 16␊
2477␊
2478#define RADEON_SE_CNTL 0x1c4c␊
2479# define RADEON_FFACE_CULL_CW (0 << 0)␊
2480# define RADEON_FFACE_CULL_CCW (1 << 0)␊
2481# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)␊
2482# define RADEON_BFACE_CULL (0 << 1)␊
2483# define RADEON_BFACE_SOLID (3 << 1)␊
2484# define RADEON_FFACE_CULL (0 << 3)␊
2485# define RADEON_FFACE_SOLID (3 << 3)␊
2486# define RADEON_FFACE_CULL_MASK (3 << 3)␊
2487# define RADEON_BADVTX_CULL_DISABLE (1 << 5)␊
2488# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)␊
2489# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)␊
2490# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)␊
2491# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)␊
2492# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)␊
2493# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)␊
2494# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)␊
2495# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)␊
2496# define RADEON_ALPHA_SHADE_SOLID (0 << 10)␊
2497# define RADEON_ALPHA_SHADE_FLAT (1 << 10)␊
2498# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)␊
2499# define RADEON_ALPHA_SHADE_MASK (3 << 10)␊
2500# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)␊
2501# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)␊
2502# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)␊
2503# define RADEON_SPECULAR_SHADE_MASK (3 << 12)␊
2504# define RADEON_FOG_SHADE_SOLID (0 << 14)␊
2505# define RADEON_FOG_SHADE_FLAT (1 << 14)␊
2506# define RADEON_FOG_SHADE_GOURAUD (2 << 14)␊
2507# define RADEON_FOG_SHADE_MASK (3 << 14)␊
2508# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)␊
2509# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)␊
2510# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)␊
2511# define RADEON_WIDELINE_ENABLE (1 << 20)␊
2512# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)␊
2513# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)␊
2514# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)␊
2515# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)␊
2516# define RADEON_ROUND_MODE_TRUNC (0 << 28)␊
2517# define RADEON_ROUND_MODE_ROUND (1 << 28)␊
2518# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)␊
2519# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)␊
2520# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)␊
2521# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)␊
2522# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)␊
2523# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)␊
2524#define R200_RE_CNTL␉␉␉␉0x1c50 ␊
2525# define R200_STIPPLE_ENABLE␉␉0x1␊
2526# define R200_SCISSOR_ENABLE␉␉0x2␊
2527# define R200_PATTERN_ENABLE␉␉0x4␊
2528# define R200_PERSPECTIVE_ENABLE␉␉0x8␊
2529# define R200_POINT_SMOOTH␉␉0x20␊
2530# define R200_VTX_STQ0_D3D␉␉0x00010000␊
2531# define R200_VTX_STQ1_D3D␉␉0x00040000␊
2532# define R200_VTX_STQ2_D3D␉␉0x00100000␊
2533# define R200_VTX_STQ3_D3D␉␉0x00400000␊
2534# define R200_VTX_STQ4_D3D␉␉0x01000000␊
2535# define R200_VTX_STQ5_D3D␉␉0x04000000␊
2536#define R200_RE_SCISSOR_TL_0␉␉␉0x1cd8␊
2537#define R200_RE_SCISSOR_BR_0␉␉␉0x1cdc␊
2538#define R200_RE_SCISSOR_TL_1␉␉␉0x1ce0␊
2539#define R200_RE_SCISSOR_BR_1␉␉␉0x1ce4␊
2540#define R200_RE_SCISSOR_TL_2␉␉␉0x1ce8␊
2541#define R200_RE_SCISSOR_BR_2␉␉␉0x1cec␊
2542# define R200_SCISSOR_X_SHIFT␉␉0␊
2543# define R200_SCISSOR_Y_SHIFT␉␉16␊
2544#define RADEON_SE_CNTL_STATUS 0x2140␊
2545# define RADEON_VC_NO_SWAP (0 << 0)␊
2546# define RADEON_VC_16BIT_SWAP (1 << 0)␊
2547# define RADEON_VC_32BIT_SWAP (2 << 0)␊
2548# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)␊
2549# define RADEON_TCL_BYPASS (1 << 8)␊
2550#define RADEON_SE_COORD_FMT 0x1c50␊
2551# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)␊
2552# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)␊
2553# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)␊
2554# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)␊
2555# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)␊
2556# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)␊
2557# define RADEON_VTX_W0_NORMALIZE (1 << 12)␊
2558# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)␊
2559# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)␊
2560# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)␊
2561# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)␊
2562# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)␊
2563# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)␊
2564# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)␊
2565#define RADEON_SE_LINE_WIDTH 0x1db8␊
2566#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c␊
2567# define RADEON_LIGHTING_ENABLE (1 << 0)␊
2568# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)␊
2569# define RADEON_LOCAL_VIEWER (1 << 2)␊
2570# define RADEON_NORMALIZE_NORMALS (1 << 3)␊
2571# define RADEON_RESCALE_NORMALS (1 << 4)␊
2572# define RADEON_SPECULAR_LIGHTS (1 << 5)␊
2573# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)␊
2574# define RADEON_LIGHT_ALPHA (1 << 7)␊
2575# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)␊
2576# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)␊
2577# define RADEON_LM_SOURCE_STATE_PREMULT 0␊
2578# define RADEON_LM_SOURCE_STATE_MULT 1␊
2579# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2␊
2580# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3␊
2581# define RADEON_EMISSIVE_SOURCE_SHIFT 16␊
2582# define RADEON_AMBIENT_SOURCE_SHIFT 18␊
2583# define RADEON_DIFFUSE_SOURCE_SHIFT 20␊
2584# define RADEON_SPECULAR_SOURCE_SHIFT 22␊
2585#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220␊
2586#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224␊
2587#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228␊
2588#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c␊
2589#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230␊
2590#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234␊
2591#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238␊
2592#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c␊
2593#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210␊
2594#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214␊
2595#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218␊
2596#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c␊
2597#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240␊
2598#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244␊
2599#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248␊
2600#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c␊
2601#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c␊
2602# define RADEON_MODELVIEW_0_SHIFT 0␊
2603# define RADEON_MODELVIEW_1_SHIFT 4␊
2604# define RADEON_MODELVIEW_2_SHIFT 8␊
2605# define RADEON_MODELVIEW_3_SHIFT 12␊
2606# define RADEON_IT_MODELVIEW_0_SHIFT 16␊
2607# define RADEON_IT_MODELVIEW_1_SHIFT 20␊
2608# define RADEON_IT_MODELVIEW_2_SHIFT 24␊
2609# define RADEON_IT_MODELVIEW_3_SHIFT 28␊
2610#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260␊
2611# define RADEON_MODELPROJECT_0_SHIFT 0␊
2612# define RADEON_MODELPROJECT_1_SHIFT 4␊
2613# define RADEON_MODELPROJECT_2_SHIFT 8␊
2614# define RADEON_MODELPROJECT_3_SHIFT 12␊
2615# define RADEON_TEXMAT_0_SHIFT 16␊
2616# define RADEON_TEXMAT_1_SHIFT 20␊
2617# define RADEON_TEXMAT_2_SHIFT 24␊
2618# define RADEON_TEXMAT_3_SHIFT 28␊
2619␊
2620␊
2621#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254␊
2622# define RADEON_TCL_VTX_W0 (1 << 0)␊
2623# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)␊
2624# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)␊
2625# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)␊
2626# define RADEON_TCL_VTX_FP_SPEC (1 << 4)␊
2627# define RADEON_TCL_VTX_FP_FOG (1 << 5)␊
2628# define RADEON_TCL_VTX_PK_SPEC (1 << 6)␊
2629# define RADEON_TCL_VTX_ST0 (1 << 7)␊
2630# define RADEON_TCL_VTX_ST1 (1 << 8)␊
2631# define RADEON_TCL_VTX_Q1 (1 << 9)␊
2632# define RADEON_TCL_VTX_ST2 (1 << 10)␊
2633# define RADEON_TCL_VTX_Q2 (1 << 11)␊
2634# define RADEON_TCL_VTX_ST3 (1 << 12)␊
2635# define RADEON_TCL_VTX_Q3 (1 << 13)␊
2636# define RADEON_TCL_VTX_Q0 (1 << 14)␊
2637# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15␊
2638# define RADEON_TCL_VTX_NORM0 (1 << 18)␊
2639# define RADEON_TCL_VTX_XY1 (1 << 27)␊
2640# define RADEON_TCL_VTX_Z1 (1 << 28)␊
2641# define RADEON_TCL_VTX_W1 (1 << 29)␊
2642# define RADEON_TCL_VTX_NORM1 (1 << 30)␊
2643# define RADEON_TCL_VTX_Z0 (1 << 31)␊
2644␊
2645#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258␊
2646# define RADEON_TCL_COMPUTE_XYZW (1 << 0)␊
2647# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)␊
2648# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)␊
2649# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)␊
2650# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)␊
2651# define RADEON_TCL_TEX_INPUT_TEX_0 0␊
2652# define RADEON_TCL_TEX_INPUT_TEX_1 1␊
2653# define RADEON_TCL_TEX_INPUT_TEX_2 2␊
2654# define RADEON_TCL_TEX_INPUT_TEX_3 3␊
2655# define RADEON_TCL_TEX_COMPUTED_TEX_0 8␊
2656# define RADEON_TCL_TEX_COMPUTED_TEX_1 9␊
2657# define RADEON_TCL_TEX_COMPUTED_TEX_2 10␊
2658# define RADEON_TCL_TEX_COMPUTED_TEX_3 11␊
2659# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16␊
2660# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20␊
2661# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24␊
2662# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28␊
2663␊
2664#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270␊
2665# define RADEON_LIGHT_0_ENABLE (1 << 0)␊
2666# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)␊
2667# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)␊
2668# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)␊
2669# define RADEON_LIGHT_0_IS_SPOT (1 << 4)␊
2670# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)␊
2671# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)␊
2672# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)␊
2673# define RADEON_LIGHT_0_SHIFT 0␊
2674# define RADEON_LIGHT_1_ENABLE (1 << 16)␊
2675# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)␊
2676# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)␊
2677# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)␊
2678# define RADEON_LIGHT_1_IS_SPOT (1 << 20)␊
2679# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)␊
2680# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)␊
2681# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)␊
2682# define RADEON_LIGHT_1_SHIFT 16␊
2683#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274␊
2684# define RADEON_LIGHT_2_SHIFT 0␊
2685# define RADEON_LIGHT_3_SHIFT 16␊
2686#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278␊
2687# define RADEON_LIGHT_4_SHIFT 0␊
2688# define RADEON_LIGHT_5_SHIFT 16␊
2689#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c␊
2690# define RADEON_LIGHT_6_SHIFT 0␊
2691# define RADEON_LIGHT_7_SHIFT 16␊
2692␊
2693#define RADEON_SE_TCL_SHININESS 0x2250␊
2694␊
2695#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268␊
2696# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)␊
2697# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)␊
2698# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)␊
2699# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)␊
2700# define RADEON_TEXMAT_0_ENABLE (1 << 4)␊
2701# define RADEON_TEXMAT_1_ENABLE (1 << 5)␊
2702# define RADEON_TEXMAT_2_ENABLE (1 << 6)␊
2703# define RADEON_TEXMAT_3_ENABLE (1 << 7)␊
2704# define RADEON_TEXGEN_INPUT_MASK 0xf␊
2705# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0␊
2706# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1␊
2707# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2␊
2708# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3␊
2709# define RADEON_TEXGEN_INPUT_OBJ 4␊
2710# define RADEON_TEXGEN_INPUT_EYE 5␊
2711# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6␊
2712# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7␊
2713# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8␊
2714# define RADEON_TEXGEN_0_INPUT_SHIFT 16␊
2715# define RADEON_TEXGEN_1_INPUT_SHIFT 20␊
2716# define RADEON_TEXGEN_2_INPUT_SHIFT 24␊
2717# define RADEON_TEXGEN_3_INPUT_SHIFT 28␊
2718␊
2719#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264␊
2720# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)␊
2721# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)␊
2722# define RADEON_UCP_ENABLE_0 (1 << 2)␊
2723# define RADEON_UCP_ENABLE_1 (1 << 3)␊
2724# define RADEON_UCP_ENABLE_2 (1 << 4)␊
2725# define RADEON_UCP_ENABLE_3 (1 << 5)␊
2726# define RADEON_UCP_ENABLE_4 (1 << 6)␊
2727# define RADEON_UCP_ENABLE_5 (1 << 7)␊
2728# define RADEON_TCL_FOG_MASK (3 << 8)␊
2729# define RADEON_TCL_FOG_DISABLE (0 << 8)␊
2730# define RADEON_TCL_FOG_EXP (1 << 8)␊
2731# define RADEON_TCL_FOG_EXP2 (2 << 8)␊
2732# define RADEON_TCL_FOG_LINEAR (3 << 8)␊
2733# define RADEON_RNG_BASED_FOG (1 << 10)␊
2734# define RADEON_LIGHT_TWOSIDE (1 << 11)␊
2735# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)␊
2736# define RADEON_BLEND_OP_COUNT_SHIFT 12␊
2737# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)␊
2738# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)␊
2739# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)␊
2740# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)␊
2741# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)␊
2742# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)␊
2743# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)␊
2744# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)␊
2745# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)␊
2746# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)␊
2747# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)␊
2748# define RADEON_CULL_FRONT_IS_CW (0 << 28)␊
2749# define RADEON_CULL_FRONT_IS_CCW (1 << 28)␊
2750# define RADEON_CULL_FRONT (1 << 29)␊
2751# define RADEON_CULL_BACK (1 << 30)␊
2752# define RADEON_FORCE_W_TO_ONE (1 << 31)␊
2753␊
2754#define RADEON_SE_VPORT_XSCALE 0x1d98␊
2755#define RADEON_SE_VPORT_XOFFSET 0x1d9c␊
2756#define RADEON_SE_VPORT_YSCALE 0x1da0␊
2757#define RADEON_SE_VPORT_YOFFSET 0x1da4␊
2758#define RADEON_SE_VPORT_ZSCALE 0x1da8␊
2759#define RADEON_SE_VPORT_ZOFFSET 0x1dac␊
2760#define RADEON_SE_ZBIAS_FACTOR 0x1db0␊
2761#define RADEON_SE_ZBIAS_CONSTANT 0x1db4␊
2762␊
2763#define RADEON_SE_VTX_FMT 0x2080␊
2764# define RADEON_SE_VTX_FMT_XY 0x00000000␊
2765# define RADEON_SE_VTX_FMT_W0 0x00000001␊
2766# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002␊
2767# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004␊
2768# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008␊
2769# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010␊
2770# define RADEON_SE_VTX_FMT_FPFOG 0x00000020␊
2771# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040␊
2772# define RADEON_SE_VTX_FMT_ST0 0x00000080␊
2773# define RADEON_SE_VTX_FMT_ST1 0x00000100␊
2774# define RADEON_SE_VTX_FMT_Q1 0x00000200␊
2775# define RADEON_SE_VTX_FMT_ST2 0x00000400␊
2776# define RADEON_SE_VTX_FMT_Q2 0x00000800␊
2777# define RADEON_SE_VTX_FMT_ST3 0x00001000␊
2778# define RADEON_SE_VTX_FMT_Q3 0x00002000␊
2779# define RADEON_SE_VTX_FMT_Q0 0x00004000␊
2780# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000␊
2781# define RADEON_SE_VTX_FMT_N0 0x00040000␊
2782# define RADEON_SE_VTX_FMT_XY1 0x08000000␊
2783# define RADEON_SE_VTX_FMT_Z1 0x10000000␊
2784# define RADEON_SE_VTX_FMT_W1 0x20000000␊
2785# define RADEON_SE_VTX_FMT_N1 0x40000000␊
2786# define RADEON_SE_VTX_FMT_Z 0x80000000␊
2787␊
2788#define RADEON_SE_VF_CNTL 0x2084␊
2789# define RADEON_VF_PRIM_TYPE_POINT_LIST 1␊
2790# define RADEON_VF_PRIM_TYPE_LINE_LIST 2␊
2791# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3␊
2792# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4␊
2793# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5␊
2794# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6␊
2795# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7␊
2796# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8␊
2797# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9␊
2798# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10␊
2799# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11␊
2800# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12␊
2801# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13␊
2802# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14␊
2803# define RADEON_VF_PRIM_TYPE_POLYGON 15␊
2804# define RADEON_VF_PRIM_WALK_STATE (0<<4)␊
2805# define RADEON_VF_PRIM_WALK_INDEX (1<<4)␊
2806# define RADEON_VF_PRIM_WALK_LIST (2<<4)␊
2807# define RADEON_VF_PRIM_WALK_DATA (3<<4)␊
2808# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)␊
2809# define RADEON_VF_RADEON_MODE (1<<8)␊
2810# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)␊
2811# define RADEON_VF_PROG_STREAM_ENA (1<<10)␊
2812# define RADEON_VF_INDEX_SIZE_SHIFT 11␊
2813# define RADEON_VF_NUM_VERTICES_SHIFT 16␊
2814␊
2815#define RADEON_SE_PORT_DATA0␉␉␉0x2000␊
2816 ␊
2817#define R200_SE_VAP_CNTL␉␉␉0x2080␊
2818# define R200_VAP_TCL_ENABLE␉␉0x00000001␊
2819# define R200_VAP_SINGLE_BUF_STATE_ENABLE␉0x00000010␊
2820# define R200_VAP_FORCE_W_TO_ONE␉␉0x00010000␊
2821# define R200_VAP_D3D_TEX_DEFAULT␉␉0x00020000␊
2822# define R200_VAP_VF_MAX_VTX_NUM__SHIFT␉18␊
2823# define R200_VAP_VF_MAX_VTX_NUM␉␉(9 << 18)␊
2824# define R200_VAP_DX_CLIP_SPACE_DEF␉0x00400000␊
2825#define R200_VF_MAX_VTX_INDX␉␉␉0x210c␊
2826#define R200_VF_MIN_VTX_INDX␉␉␉0x2110␊
2827#define R200_SE_VTE_CNTL␉␉␉0x20b0␊
2828# define R200_VPORT_X_SCALE_ENA␉␉␉0x00000001␊
2829# define R200_VPORT_X_OFFSET_ENA␉␉␉0x00000002␊
2830# define R200_VPORT_Y_SCALE_ENA␉␉␉0x00000004␊
2831# define R200_VPORT_Y_OFFSET_ENA␉␉␉0x00000008␊
2832# define R200_VPORT_Z_SCALE_ENA␉␉␉0x00000010␊
2833# define R200_VPORT_Z_OFFSET_ENA␉␉␉0x00000020␊
2834# define R200_VTX_XY_FMT␉␉␉␉0x00000100␊
2835# define R200_VTX_Z_FMT␉␉␉␉0x00000200␊
2836# define R200_VTX_W0_FMT␉␉␉␉0x00000400␊
2837# define R200_VTX_W0_NORMALIZE␉␉␉0x00000800␊
2838# define R200_VTX_ST_DENORMALIZED␉␉0x00001000␊
2839#define R200_SE_VAP_CNTL_STATUS␉␉␉0x2140␊
2840# define R200_VC_NO_SWAP␉␉␉(0 << 0)␊
2841# define R200_VC_16BIT_SWAP␉␉(1 << 0)␊
2842# define R200_VC_32BIT_SWAP␉␉(2 << 0)␊
2843#define R200_RE_AUX_SCISSOR_CNTL␉␉0x26f0␊
2844# define R200_EXCLUSIVE_SCISSOR_0␉␉0x01000000␊
2845# define R200_EXCLUSIVE_SCISSOR_1␉␉0x02000000␊
2846# define R200_EXCLUSIVE_SCISSOR_2␉␉0x04000000␊
2847# define R200_SCISSOR_ENABLE_0␉␉0x10000000␊
2848# define R200_SCISSOR_ENABLE_1␉␉0x20000000␊
2849# define R200_SCISSOR_ENABLE_2␉␉0x40000000␊
2850#define R200_PP_TXFILTER_0␉␉␉0x2c00 ␊
2851#define R200_PP_TXFILTER_1␉␉␉0x2c20␊
2852#define R200_PP_TXFILTER_2␉␉␉0x2c40␊
2853#define R200_PP_TXFILTER_3␉␉␉0x2c60␊
2854#define R200_PP_TXFILTER_4␉␉␉0x2c80␊
2855#define R200_PP_TXFILTER_5␉␉␉0x2ca0␊
2856# define R200_MAG_FILTER_NEAREST␉␉(0 << 0)␊
2857# define R200_MAG_FILTER_LINEAR␉␉(1 << 0)␊
2858# define R200_MAG_FILTER_MASK␉␉(1 << 0)␊
2859# define R200_MIN_FILTER_NEAREST␉␉(0 << 1)␊
2860# define R200_MIN_FILTER_LINEAR␉␉(1 << 1)␊
2861# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)␊
2862# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)␊
2863# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)␊
2864# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)␊
2865# define R200_MIN_FILTER_ANISO_NEAREST␉(8 << 1)␊
2866# define R200_MIN_FILTER_ANISO_LINEAR␉(9 << 1)␊
2867# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)␊
2868# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)␊
2869# define R200_MIN_FILTER_MASK␉␉(15 << 1)␊
2870# define R200_MAX_ANISO_1_TO_1␉␉(0 << 5)␊
2871# define R200_MAX_ANISO_2_TO_1␉␉(1 << 5)␊
2872# define R200_MAX_ANISO_4_TO_1␉␉(2 << 5)␊
2873# define R200_MAX_ANISO_8_TO_1␉␉(3 << 5)␊
2874# define R200_MAX_ANISO_16_TO_1␉␉(4 << 5)␊
2875# define R200_MAX_ANISO_MASK␉␉(7 << 5)␊
2876# define R200_MAX_MIP_LEVEL_MASK␉␉(0x0f << 16)␊
2877# define R200_MAX_MIP_LEVEL_SHIFT␉␉16␊
2878# define R200_YUV_TO_RGB␉␉␉(1 << 20)␊
2879# define R200_YUV_TEMPERATURE_COOL␉(0 << 21)␊
2880# define R200_YUV_TEMPERATURE_HOT␉␉(1 << 21)␊
2881# define R200_YUV_TEMPERATURE_MASK␉(1 << 21)␊
2882# define R200_WRAPEN_S␉␉␉(1 << 22)␊
2883# define R200_CLAMP_S_WRAP␉␉(0 << 23)␊
2884# define R200_CLAMP_S_MIRROR␉␉(1 << 23)␊
2885# define R200_CLAMP_S_CLAMP_LAST␉␉(2 << 23)␊
2886# define R200_CLAMP_S_MIRROR_CLAMP_LAST␉(3 << 23)␊
2887# define R200_CLAMP_S_CLAMP_BORDER␉(4 << 23)␊
2888# define R200_CLAMP_S_MIRROR_CLAMP_BORDER␉(5 << 23)␊
2889# define R200_CLAMP_S_CLAMP_GL␉␉(6 << 23)␊
2890# define R200_CLAMP_S_MIRROR_CLAMP_GL␉(7 << 23)␊
2891# define R200_CLAMP_S_MASK␉␉(7 << 23)␊
2892# define R200_WRAPEN_T␉␉␉(1 << 26)␊
2893# define R200_CLAMP_T_WRAP␉␉(0 << 27)␊
2894# define R200_CLAMP_T_MIRROR␉␉(1 << 27)␊
2895# define R200_CLAMP_T_CLAMP_LAST␉␉(2 << 27)␊
2896# define R200_CLAMP_T_MIRROR_CLAMP_LAST␉(3 << 27)␊
2897# define R200_CLAMP_T_CLAMP_BORDER␉(4 << 27)␊
2898# define R200_CLAMP_T_MIRROR_CLAMP_BORDER␉(5 << 27)␊
2899# define R200_CLAMP_T_CLAMP_GL␉␉(6 << 27)␊
2900# define R200_CLAMP_T_MIRROR_CLAMP_GL␉(7 << 27)␊
2901# define R200_CLAMP_T_MASK␉␉(7 << 27)␊
2902# define R200_KILL_LT_ZERO␉␉(1 << 30)␊
2903# define R200_BORDER_MODE_OGL␉␉(0 << 31)␊
2904# define R200_BORDER_MODE_D3D␉␉(1 << 31)␊
2905#define R200_PP_TXFORMAT_0␉␉␉0x2c04␊
2906#define R200_PP_TXFORMAT_1␉␉␉0x2c24␊
2907#define R200_PP_TXFORMAT_2␉␉␉0x2c44␊
2908#define R200_PP_TXFORMAT_3␉␉␉0x2c64␊
2909#define R200_PP_TXFORMAT_4␉␉␉0x2c84␊
2910#define R200_PP_TXFORMAT_5␉␉␉0x2ca4␊
2911# define R200_TXFORMAT_I8␉␉␉(0 << 0)␊
2912# define R200_TXFORMAT_AI88␉␉(1 << 0)␊
2913# define R200_TXFORMAT_RGB332␉␉(2 << 0)␊
2914# define R200_TXFORMAT_ARGB1555␉␉(3 << 0)␊
2915# define R200_TXFORMAT_RGB565␉␉(4 << 0)␊
2916# define R200_TXFORMAT_ARGB4444␉␉(5 << 0)␊
2917# define R200_TXFORMAT_ARGB8888␉␉(6 << 0)␊
2918# define R200_TXFORMAT_RGBA8888␉␉(7 << 0)␊
2919# define R200_TXFORMAT_Y8␉␉␉(8 << 0)␊
2920# define R200_TXFORMAT_AVYU4444␉␉(9 << 0)␊
2921# define R200_TXFORMAT_VYUY422␉␉(10 << 0)␊
2922# define R200_TXFORMAT_YVYU422␉␉(11 << 0)␊
2923# define R200_TXFORMAT_DXT1␉␉(12 << 0)␊
2924# define R200_TXFORMAT_DXT23␉␉(14 << 0)␊
2925# define R200_TXFORMAT_DXT45␉␉(15 << 0)␊
2926# define R200_TXFORMAT_ABGR8888␉␉(22 << 0)␊
2927# define R200_TXFORMAT_FORMAT_MASK␉(31 <<␉0)␊
2928# define R200_TXFORMAT_FORMAT_SHIFT␉0␊
2929# define R200_TXFORMAT_ALPHA_IN_MAP␉(1 << 6)␊
2930# define R200_TXFORMAT_NON_POWER2␉␉(1 << 7)␊
2931# define R200_TXFORMAT_WIDTH_MASK␉␉(15 <<␉8)␊
2932# define R200_TXFORMAT_WIDTH_SHIFT␉8␊
2933# define R200_TXFORMAT_HEIGHT_MASK␉(15 << 12)␊
2934# define R200_TXFORMAT_HEIGHT_SHIFT␉12␊
2935# define R200_TXFORMAT_F5_WIDTH_MASK␉(15 << 16)␉/* cube face 5 */␊
2936# define R200_TXFORMAT_F5_WIDTH_SHIFT␉16␊
2937# define R200_TXFORMAT_F5_HEIGHT_MASK␉(15 << 20)␊
2938# define R200_TXFORMAT_F5_HEIGHT_SHIFT␉20␊
2939# define R200_TXFORMAT_ST_ROUTE_STQ0␉(0 << 24)␊
2940# define R200_TXFORMAT_ST_ROUTE_STQ1␉(1 << 24)␊
2941# define R200_TXFORMAT_ST_ROUTE_STQ2␉(2 << 24)␊
2942# define R200_TXFORMAT_ST_ROUTE_STQ3␉(3 << 24)␊
2943# define R200_TXFORMAT_ST_ROUTE_STQ4␉(4 << 24)␊
2944# define R200_TXFORMAT_ST_ROUTE_STQ5␉(5 << 24)␊
2945# define R200_TXFORMAT_ST_ROUTE_MASK␉(7 << 24)␊
2946# define R200_TXFORMAT_ST_ROUTE_SHIFT␉24␊
2947# define R200_TXFORMAT_ALPHA_MASK_ENABLE␉(1 << 28)␊
2948# define R200_TXFORMAT_CHROMA_KEY_ENABLE␉(1 << 29)␊
2949# define R200_TXFORMAT_CUBIC_MAP_ENABLE␉␉(1 << 30)␊
2950#define R200_PP_TXFORMAT_X_0 0x2c08␊
2951#define R200_PP_TXFORMAT_X_1 0x2c28␊
2952#define R200_PP_TXFORMAT_X_2 0x2c48␊
2953#define R200_PP_TXFORMAT_X_3 0x2c68␊
2954#define R200_PP_TXFORMAT_X_4 0x2c88␊
2955#define R200_PP_TXFORMAT_X_5 0x2ca8␊
2956␊
2957#define R200_PP_TXSIZE_0␉␉␉0x2c0c /* NPOT only */␊
2958#define R200_PP_TXSIZE_1␉␉␉0x2c2c /* NPOT only */␊
2959#define R200_PP_TXSIZE_2␉␉␉0x2c4c /* NPOT only */␊
2960#define R200_PP_TXSIZE_3␉␉␉0x2c6c /* NPOT only */␊
2961#define R200_PP_TXSIZE_4␉␉␉0x2c8c /* NPOT only */␊
2962#define R200_PP_TXSIZE_5␉␉␉0x2cac /* NPOT only */␊
2963␊
2964#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */␊
2965#define R200_PP_TXPITCH_1␉␉␉0x2c30 /* NPOT only */␊
2966#define R200_PP_TXPITCH_2␉␉␉0x2c50 /* NPOT only */␊
2967#define R200_PP_TXPITCH_3␉␉␉0x2c70 /* NPOT only */␊
2968#define R200_PP_TXPITCH_4␉␉␉0x2c90 /* NPOT only */␊
2969#define R200_PP_TXPITCH_5␉␉␉0x2cb0 /* NPOT only */␊
2970␊
2971#define R200_PP_TXOFFSET_0␉␉␉0x2d00␊
2972# define R200_TXO_ENDIAN_NO_SWAP␉␉(0 << 0)␊
2973# define R200_TXO_ENDIAN_BYTE_SWAP␉(1 << 0)␊
2974# define R200_TXO_ENDIAN_WORD_SWAP␉(2 << 0)␊
2975# define R200_TXO_ENDIAN_HALFDW_SWAP␉(3 << 0)␊
2976# define R200_TXO_MACRO_LINEAR␉␉(0 << 2)␊
2977# define R200_TXO_MACRO_TILE␉␉(1 << 2)␊
2978# define R200_TXO_MICRO_LINEAR␉␉(0 << 3)␊
2979# define R200_TXO_MICRO_TILE␉␉(1 << 3)␊
2980# define R200_TXO_OFFSET_MASK␉␉0xffffffe0␊
2981# define R200_TXO_OFFSET_SHIFT␉␉5␊
2982#define R200_PP_TXOFFSET_1␉␉␉0x2d18␊
2983#define R200_PP_TXOFFSET_2␉␉␉0x2d30␊
2984#define R200_PP_TXOFFSET_3␉␉␉0x2d48␊
2985#define R200_PP_TXOFFSET_4␉␉␉0x2d60␊
2986#define R200_PP_TXOFFSET_5␉␉␉0x2d78␊
2987␊
2988#define R200_PP_TFACTOR_0␉␉␉0x2ee0␊
2989#define R200_PP_TFACTOR_1␉␉␉0x2ee4␊
2990#define R200_PP_TFACTOR_2␉␉␉0x2ee8␊
2991#define R200_PP_TFACTOR_3␉␉␉0x2eec␊
2992#define R200_PP_TFACTOR_4␉␉␉0x2ef0␊
2993#define R200_PP_TFACTOR_5␉␉␉0x2ef4␊
2994␊
2995#define R200_PP_TXCBLEND_0␉␉␉0x2f00␊
2996# define R200_TXC_ARG_A_ZERO␉␉(0)␊
2997# define R200_TXC_ARG_A_CURRENT_COLOR␉(2)␊
2998# define R200_TXC_ARG_A_CURRENT_ALPHA␉(3)␊
2999# define R200_TXC_ARG_A_DIFFUSE_COLOR␉(4)␊
3000# define R200_TXC_ARG_A_DIFFUSE_ALPHA␉(5)␊
3001# define R200_TXC_ARG_A_SPECULAR_COLOR␉(6)␊
3002# define R200_TXC_ARG_A_SPECULAR_ALPHA␉(7)␊
3003# define R200_TXC_ARG_A_TFACTOR_COLOR␉(8)␊
3004# define R200_TXC_ARG_A_TFACTOR_ALPHA␉(9)␊
3005# define R200_TXC_ARG_A_R0_COLOR␉␉(10)␊
3006# define R200_TXC_ARG_A_R0_ALPHA␉␉(11)␊
3007# define R200_TXC_ARG_A_R1_COLOR␉␉(12)␊
3008# define R200_TXC_ARG_A_R1_ALPHA␉␉(13)␊
3009# define R200_TXC_ARG_A_R2_COLOR␉␉(14)␊
3010# define R200_TXC_ARG_A_R2_ALPHA␉␉(15)␊
3011# define R200_TXC_ARG_A_R3_COLOR␉␉(16)␊
3012# define R200_TXC_ARG_A_R3_ALPHA␉␉(17)␊
3013# define R200_TXC_ARG_A_R4_COLOR␉␉(18)␊
3014# define R200_TXC_ARG_A_R4_ALPHA␉␉(19)␊
3015# define R200_TXC_ARG_A_R5_COLOR␉␉(20)␊
3016# define R200_TXC_ARG_A_R5_ALPHA␉␉(21)␊
3017# define R200_TXC_ARG_A_TFACTOR1_COLOR␉(26)␊
3018# define R200_TXC_ARG_A_TFACTOR1_ALPHA␉(27)␊
3019# define R200_TXC_ARG_A_MASK␉␉(31 << 0)␊
3020# define R200_TXC_ARG_A_SHIFT␉␉0␊
3021# define R200_TXC_ARG_B_ZERO␉␉(0 << 5)␊
3022# define R200_TXC_ARG_B_CURRENT_COLOR␉(2 << 5)␊
3023# define R200_TXC_ARG_B_CURRENT_ALPHA␉(3 << 5)␊
3024# define R200_TXC_ARG_B_DIFFUSE_COLOR␉(4 << 5)␊
3025# define R200_TXC_ARG_B_DIFFUSE_ALPHA␉(5 << 5)␊
3026# define R200_TXC_ARG_B_SPECULAR_COLOR␉(6 << 5)␊
3027# define R200_TXC_ARG_B_SPECULAR_ALPHA␉(7 << 5)␊
3028# define R200_TXC_ARG_B_TFACTOR_COLOR␉(8 << 5)␊
3029# define R200_TXC_ARG_B_TFACTOR_ALPHA␉(9 << 5)␊
3030# define R200_TXC_ARG_B_R0_COLOR␉␉(10 << 5)␊
3031# define R200_TXC_ARG_B_R0_ALPHA␉␉(11 << 5)␊
3032# define R200_TXC_ARG_B_R1_COLOR␉␉(12 << 5)␊
3033# define R200_TXC_ARG_B_R1_ALPHA␉␉(13 << 5)␊
3034# define R200_TXC_ARG_B_R2_COLOR␉␉(14 << 5)␊
3035# define R200_TXC_ARG_B_R2_ALPHA␉␉(15 << 5)␊
3036# define R200_TXC_ARG_B_R3_COLOR␉␉(16 << 5)␊
3037# define R200_TXC_ARG_B_R3_ALPHA␉␉(17 << 5)␊
3038# define R200_TXC_ARG_B_R4_COLOR␉␉(18 << 5)␊
3039# define R200_TXC_ARG_B_R4_ALPHA␉␉(19 << 5)␊
3040# define R200_TXC_ARG_B_R5_COLOR␉␉(20 << 5)␊
3041# define R200_TXC_ARG_B_R5_ALPHA␉␉(21 << 5)␊
3042# define R200_TXC_ARG_B_TFACTOR1_COLOR␉(26 << 5)␊
3043# define R200_TXC_ARG_B_TFACTOR1_ALPHA␉(27 << 5)␊
3044# define R200_TXC_ARG_B_MASK␉␉(31 << 5)␊
3045# define R200_TXC_ARG_B_SHIFT␉␉5␊
3046# define R200_TXC_ARG_C_ZERO␉␉(0 << 10)␊
3047# define R200_TXC_ARG_C_CURRENT_COLOR␉(2 << 10)␊
3048# define R200_TXC_ARG_C_CURRENT_ALPHA␉(3 << 10)␊
3049# define R200_TXC_ARG_C_DIFFUSE_COLOR␉(4 << 10)␊
3050# define R200_TXC_ARG_C_DIFFUSE_ALPHA␉(5 << 10)␊
3051# define R200_TXC_ARG_C_SPECULAR_COLOR␉(6 << 10)␊
3052# define R200_TXC_ARG_C_SPECULAR_ALPHA␉(7 << 10)␊
3053# define R200_TXC_ARG_C_TFACTOR_COLOR␉(8 << 10)␊
3054# define R200_TXC_ARG_C_TFACTOR_ALPHA␉(9 << 10)␊
3055# define R200_TXC_ARG_C_R0_COLOR␉␉(10 << 10)␊
3056# define R200_TXC_ARG_C_R0_ALPHA␉␉(11 << 10)␊
3057# define R200_TXC_ARG_C_R1_COLOR␉␉(12 << 10)␊
3058# define R200_TXC_ARG_C_R1_ALPHA␉␉(13 << 10)␊
3059# define R200_TXC_ARG_C_R2_COLOR␉␉(14 << 10)␊
3060# define R200_TXC_ARG_C_R2_ALPHA␉␉(15 << 10)␊
3061# define R200_TXC_ARG_C_R3_COLOR␉␉(16 << 10)␊
3062# define R200_TXC_ARG_C_R3_ALPHA␉␉(17 << 10)␊
3063# define R200_TXC_ARG_C_R4_COLOR␉␉(18 << 10)␊
3064# define R200_TXC_ARG_C_R4_ALPHA␉␉(19 << 10)␊
3065# define R200_TXC_ARG_C_R5_COLOR␉␉(20 << 10)␊
3066# define R200_TXC_ARG_C_R5_ALPHA␉␉(21 << 10)␊
3067# define R200_TXC_ARG_C_TFACTOR1_COLOR␉(26 << 10)␊
3068# define R200_TXC_ARG_C_TFACTOR1_ALPHA␉(27 << 10)␊
3069# define R200_TXC_ARG_C_MASK␉␉(31 << 10)␊
3070# define R200_TXC_ARG_C_SHIFT␉␉10␊
3071# define R200_TXC_COMP_ARG_A␉␉(1 << 16)␊
3072# define R200_TXC_COMP_ARG_A_SHIFT␉(16)␊
3073# define R200_TXC_BIAS_ARG_A␉␉(1 << 17)␊
3074# define R200_TXC_SCALE_ARG_A␉␉(1 << 18)␊
3075# define R200_TXC_NEG_ARG_A␉␉(1 << 19)␊
3076# define R200_TXC_COMP_ARG_B␉␉(1 << 20)␊
3077# define R200_TXC_COMP_ARG_B_SHIFT␉(20)␊
3078# define R200_TXC_BIAS_ARG_B␉␉(1 << 21)␊
3079# define R200_TXC_SCALE_ARG_B␉␉(1 << 22)␊
3080# define R200_TXC_NEG_ARG_B␉␉(1 << 23)␊
3081# define R200_TXC_COMP_ARG_C␉␉(1 << 24)␊
3082# define R200_TXC_COMP_ARG_C_SHIFT␉(24)␊
3083# define R200_TXC_BIAS_ARG_C␉␉(1 << 25)␊
3084# define R200_TXC_SCALE_ARG_C␉␉(1 << 26)␊
3085# define R200_TXC_NEG_ARG_C␉␉(1 << 27)␊
3086# define R200_TXC_OP_MADD␉␉␉(0 << 28)␊
3087# define R200_TXC_OP_CND0␉␉␉(2 << 28)␊
3088# define R200_TXC_OP_LERP␉␉␉(3 << 28)␊
3089# define R200_TXC_OP_DOT3␉␉␉(4 << 28)␊
3090# define R200_TXC_OP_DOT4␉␉␉(5 << 28)␊
3091# define R200_TXC_OP_CONDITIONAL␉␉(6 << 28)␊
3092# define R200_TXC_OP_DOT2_ADD␉␉(7 << 28)␊
3093# define R200_TXC_OP_MASK␉␉␉(7 << 28)␊
3094#define R200_PP_TXCBLEND2_0␉␉0x2f04␊
3095# define R200_TXC_TFACTOR_SEL_SHIFT␉0␊
3096# define R200_TXC_TFACTOR_SEL_MASK␉0x7␊
3097# define R200_TXC_TFACTOR1_SEL_SHIFT␉4␊
3098# define R200_TXC_TFACTOR1_SEL_MASK␉(0x7 << 4)␊
3099# define R200_TXC_SCALE_SHIFT␉␉8␊
3100# define R200_TXC_SCALE_MASK␉␉(7 << 8)␊
3101# define R200_TXC_SCALE_1X␉␉(0 << 8)␊
3102# define R200_TXC_SCALE_2X␉␉(1 << 8)␊
3103# define R200_TXC_SCALE_4X␉␉(2 << 8)␊
3104# define R200_TXC_SCALE_8X␉␉(3 << 8)␊
3105# define R200_TXC_SCALE_INV2␉␉(5 << 8)␊
3106# define R200_TXC_SCALE_INV4␉␉(6 << 8)␊
3107# define R200_TXC_SCALE_INV8␉␉(7 << 8)␊
3108# define R200_TXC_CLAMP_SHIFT␉␉12␊
3109# define R200_TXC_CLAMP_MASK␉␉(3 << 12)␊
3110# define R200_TXC_CLAMP_WRAP␉␉(0 << 12)␊
3111# define R200_TXC_CLAMP_0_1␉␉(1 << 12)␊
3112# define R200_TXC_CLAMP_8_8␉␉(2 << 12)␊
3113# define R200_TXC_OUTPUT_REG_MASK␉␉(7 << 16)␊
3114# define R200_TXC_OUTPUT_REG_NONE␉␉(0 << 16)␊
3115# define R200_TXC_OUTPUT_REG_R0␉␉(1 << 16)␊
3116# define R200_TXC_OUTPUT_REG_R1␉␉(2 << 16)␊
3117# define R200_TXC_OUTPUT_REG_R2␉␉(3 << 16)␊
3118# define R200_TXC_OUTPUT_REG_R3␉␉(4 << 16)␊
3119# define R200_TXC_OUTPUT_REG_R4␉␉(5 << 16)␊
3120# define R200_TXC_OUTPUT_REG_R5␉␉(6 << 16)␊
3121# define R200_TXC_OUTPUT_MASK_MASK␉(7 << 20)␊
3122# define R200_TXC_OUTPUT_MASK_RGB␉␉(0 << 20)␊
3123# define R200_TXC_OUTPUT_MASK_RG␉␉(1 << 20)␊
3124# define R200_TXC_OUTPUT_MASK_RB␉␉(2 << 20)␊
3125# define R200_TXC_OUTPUT_MASK_R␉␉(3 << 20)␊
3126# define R200_TXC_OUTPUT_MASK_GB␉␉(4 << 20)␊
3127# define R200_TXC_OUTPUT_MASK_G␉␉(5 << 20)␊
3128# define R200_TXC_OUTPUT_MASK_B␉␉(6 << 20)␊
3129# define R200_TXC_OUTPUT_MASK_NONE␉(7 << 20)␊
3130# define R200_TXC_REPL_NORMAL␉␉0␊
3131# define R200_TXC_REPL_RED␉␉1␊
3132# define R200_TXC_REPL_GREEN␉␉2␊
3133# define R200_TXC_REPL_BLUE␉␉3␊
3134# define R200_TXC_REPL_ARG_A_SHIFT␉26␊
3135# define R200_TXC_REPL_ARG_A_MASK␉␉(3 << 26)␊
3136# define R200_TXC_REPL_ARG_B_SHIFT␉28␊
3137# define R200_TXC_REPL_ARG_B_MASK␉␉(3 << 28)␊
3138# define R200_TXC_REPL_ARG_C_SHIFT␉30␊
3139# define R200_TXC_REPL_ARG_C_MASK␉␉(3 << 30)␊
3140#define R200_PP_TXABLEND_0␉␉␉0x2f08␊
3141# define R200_TXA_ARG_A_ZERO␉␉(0)␊
3142# define R200_TXA_ARG_A_CURRENT_ALPHA␉(2) /* guess */␊
3143# define R200_TXA_ARG_A_CURRENT_BLUE␉(3) /* guess */␊
3144# define R200_TXA_ARG_A_DIFFUSE_ALPHA␉(4)␊
3145# define R200_TXA_ARG_A_DIFFUSE_BLUE␉(5)␊
3146# define R200_TXA_ARG_A_SPECULAR_ALPHA␉(6)␊
3147# define R200_TXA_ARG_A_SPECULAR_BLUE␉(7)␊
3148# define R200_TXA_ARG_A_TFACTOR_ALPHA␉(8)␊
3149# define R200_TXA_ARG_A_TFACTOR_BLUE␉(9)␊
3150# define R200_TXA_ARG_A_R0_ALPHA␉␉(10)␊
3151# define R200_TXA_ARG_A_R0_BLUE␉␉(11)␊
3152# define R200_TXA_ARG_A_R1_ALPHA␉␉(12)␊
3153# define R200_TXA_ARG_A_R1_BLUE␉␉(13)␊
3154# define R200_TXA_ARG_A_R2_ALPHA␉␉(14)␊
3155# define R200_TXA_ARG_A_R2_BLUE␉␉(15)␊
3156# define R200_TXA_ARG_A_R3_ALPHA␉␉(16)␊
3157# define R200_TXA_ARG_A_R3_BLUE␉␉(17)␊
3158# define R200_TXA_ARG_A_R4_ALPHA␉␉(18)␊
3159# define R200_TXA_ARG_A_R4_BLUE␉␉(19)␊
3160# define R200_TXA_ARG_A_R5_ALPHA␉␉(20)␊
3161# define R200_TXA_ARG_A_R5_BLUE␉␉(21)␊
3162# define R200_TXA_ARG_A_TFACTOR1_ALPHA␉(26)␊
3163# define R200_TXA_ARG_A_TFACTOR1_BLUE␉(27)␊
3164# define R200_TXA_ARG_A_MASK␉␉(31 << 0)␊
3165# define R200_TXA_ARG_A_SHIFT␉␉0␊
3166# define R200_TXA_ARG_B_ZERO␉␉(0 << 5)␊
3167# define R200_TXA_ARG_B_CURRENT_ALPHA␉(2 << 5) /* guess */␊
3168# define R200_TXA_ARG_B_CURRENT_BLUE␉(3 << 5) /* guess */␊
3169# define R200_TXA_ARG_B_DIFFUSE_ALPHA␉(4 << 5)␊
3170# define R200_TXA_ARG_B_DIFFUSE_BLUE␉(5 << 5)␊
3171# define R200_TXA_ARG_B_SPECULAR_ALPHA␉(6 << 5)␊
3172# define R200_TXA_ARG_B_SPECULAR_BLUE␉(7 << 5)␊
3173# define R200_TXA_ARG_B_TFACTOR_ALPHA␉(8 << 5)␊
3174# define R200_TXA_ARG_B_TFACTOR_BLUE␉(9 << 5)␊
3175# define R200_TXA_ARG_B_R0_ALPHA␉␉(10 << 5)␊
3176# define R200_TXA_ARG_B_R0_BLUE␉␉(11 << 5)␊
3177# define R200_TXA_ARG_B_R1_ALPHA␉␉(12 << 5)␊
3178# define R200_TXA_ARG_B_R1_BLUE␉␉(13 << 5)␊
3179# define R200_TXA_ARG_B_R2_ALPHA␉␉(14 << 5)␊
3180# define R200_TXA_ARG_B_R2_BLUE␉␉(15 << 5)␊
3181# define R200_TXA_ARG_B_R3_ALPHA␉␉(16 << 5)␊
3182# define R200_TXA_ARG_B_R3_BLUE␉␉(17 << 5)␊
3183# define R200_TXA_ARG_B_R4_ALPHA␉␉(18 << 5)␊
3184# define R200_TXA_ARG_B_R4_BLUE␉␉(19 << 5)␊
3185# define R200_TXA_ARG_B_R5_ALPHA␉␉(20 << 5)␊
3186# define R200_TXA_ARG_B_R5_BLUE␉␉(21 << 5)␊
3187# define R200_TXA_ARG_B_TFACTOR1_ALPHA␉(26 << 5)␊
3188# define R200_TXA_ARG_B_TFACTOR1_BLUE␉(27 << 5)␊
3189# define R200_TXA_ARG_B_MASK␉␉(31 << 5)␊
3190# define R200_TXA_ARG_B_SHIFT␉␉␉5␊
3191# define R200_TXA_ARG_C_ZERO␉␉(0 << 10)␊
3192# define R200_TXA_ARG_C_CURRENT_ALPHA␉(2 << 10) /* guess */␊
3193# define R200_TXA_ARG_C_CURRENT_BLUE␉(3 << 10) /* guess */␊
3194# define R200_TXA_ARG_C_DIFFUSE_ALPHA␉(4 << 10)␊
3195# define R200_TXA_ARG_C_DIFFUSE_BLUE␉(5 << 10)␊
3196# define R200_TXA_ARG_C_SPECULAR_ALPHA␉(6 << 10)␊
3197# define R200_TXA_ARG_C_SPECULAR_BLUE␉(7 << 10)␊
3198# define R200_TXA_ARG_C_TFACTOR_ALPHA␉(8 << 10)␊
3199# define R200_TXA_ARG_C_TFACTOR_BLUE␉(9 << 10)␊
3200# define R200_TXA_ARG_C_R0_ALPHA␉␉(10 << 10)␊
3201# define R200_TXA_ARG_C_R0_BLUE␉␉(11 << 10)␊
3202# define R200_TXA_ARG_C_R1_ALPHA␉␉(12 << 10)␊
3203# define R200_TXA_ARG_C_R1_BLUE␉␉(13 << 10)␊
3204# define R200_TXA_ARG_C_R2_ALPHA␉␉(14 << 10)␊
3205# define R200_TXA_ARG_C_R2_BLUE␉␉(15 << 10)␊
3206# define R200_TXA_ARG_C_R3_ALPHA␉␉(16 << 10)␊
3207# define R200_TXA_ARG_C_R3_BLUE␉␉(17 << 10)␊
3208# define R200_TXA_ARG_C_R4_ALPHA␉␉(18 << 10)␊
3209# define R200_TXA_ARG_C_R4_BLUE␉␉(19 << 10)␊
3210# define R200_TXA_ARG_C_R5_ALPHA␉␉(20 << 10)␊
3211# define R200_TXA_ARG_C_R5_BLUE␉␉(21 << 10)␊
3212# define R200_TXA_ARG_C_TFACTOR1_ALPHA␉(26 << 10)␊
3213# define R200_TXA_ARG_C_TFACTOR1_BLUE␉(27 << 10)␊
3214# define R200_TXA_ARG_C_MASK␉␉(31 << 10)␊
3215# define R200_TXA_ARG_C_SHIFT␉␉10␊
3216# define R200_TXA_COMP_ARG_A␉␉(1 << 16)␊
3217# define R200_TXA_COMP_ARG_A_SHIFT␉(16)␊
3218# define R200_TXA_BIAS_ARG_A␉␉(1 << 17)␊
3219# define R200_TXA_SCALE_ARG_A␉␉(1 << 18)␊
3220# define R200_TXA_NEG_ARG_A␉␉(1 << 19)␊
3221# define R200_TXA_COMP_ARG_B␉␉(1 << 20)␊
3222# define R200_TXA_COMP_ARG_B_SHIFT␉(20)␊
3223# define R200_TXA_BIAS_ARG_B␉␉(1 << 21)␊
3224# define R200_TXA_SCALE_ARG_B␉␉(1 << 22)␊
3225# define R200_TXA_NEG_ARG_B␉␉(1 << 23)␊
3226# define R200_TXA_COMP_ARG_C␉␉(1 << 24)␊
3227# define R200_TXA_COMP_ARG_C_SHIFT␉(24)␊
3228# define R200_TXA_BIAS_ARG_C␉␉(1 << 25)␊
3229# define R200_TXA_SCALE_ARG_C␉␉(1 << 26)␊
3230# define R200_TXA_NEG_ARG_C␉␉(1 << 27)␊
3231# define R200_TXA_OP_MADD␉␉␉(0 << 28)␊
3232# define R200_TXA_OP_CND0␉␉␉(2 << 28)␊
3233# define R200_TXA_OP_LERP␉␉␉(3 << 28)␊
3234# define R200_TXA_OP_CONDITIONAL␉␉(6 << 28)␊
3235# define R200_TXA_OP_MASK␉␉␉(7 << 28)␊
3236#define R200_PP_TXABLEND2_0␉␉␉0x2f0c␊
3237# define R200_TXA_TFACTOR_SEL_SHIFT␉0␊
3238# define R200_TXA_TFACTOR_SEL_MASK␉0x7␊
3239# define R200_TXA_TFACTOR1_SEL_SHIFT␉4␊
3240# define R200_TXA_TFACTOR1_SEL_MASK␉(0x7 << 4)␊
3241# define R200_TXA_SCALE_SHIFT␉␉8␊
3242# define R200_TXA_SCALE_MASK␉␉(7 << 8)␊
3243# define R200_TXA_SCALE_1X␉␉(0 << 8)␊
3244# define R200_TXA_SCALE_2X␉␉(1 << 8)␊
3245# define R200_TXA_SCALE_4X␉␉(2 << 8)␊
3246# define R200_TXA_SCALE_8X␉␉(3 << 8)␊
3247# define R200_TXA_SCALE_INV2␉␉(5 << 8)␊
3248# define R200_TXA_SCALE_INV4␉␉(6 << 8)␊
3249# define R200_TXA_SCALE_INV8␉␉(7 << 8)␊
3250# define R200_TXA_CLAMP_SHIFT␉␉12␊
3251# define R200_TXA_CLAMP_MASK␉␉(3 << 12)␊
3252# define R200_TXA_CLAMP_WRAP␉␉(0 << 12)␊
3253# define R200_TXA_CLAMP_0_1␉␉(1 << 12)␊
3254# define R200_TXA_CLAMP_8_8␉␉(2 << 12)␊
3255# define R200_TXA_OUTPUT_REG_MASK␉␉(7 << 16)␊
3256# define R200_TXA_OUTPUT_REG_NONE␉␉(0 << 16)␊
3257# define R200_TXA_OUTPUT_REG_R0␉␉(1 << 16)␊
3258# define R200_TXA_OUTPUT_REG_R1␉␉(2 << 16)␊
3259# define R200_TXA_OUTPUT_REG_R2␉␉(3 << 16)␊
3260# define R200_TXA_OUTPUT_REG_R3␉␉(4 << 16)␊
3261# define R200_TXA_OUTPUT_REG_R4␉␉(5 << 16)␊
3262# define R200_TXA_OUTPUT_REG_R5␉␉(6 << 16)␊
3263# define R200_TXA_DOT_ALPHA␉␉(1 << 20)␊
3264# define R200_TXA_REPL_NORMAL␉␉0␊
3265# define R200_TXA_REPL_RED␉␉1␊
3266# define R200_TXA_REPL_GREEN␉␉2␊
3267# define R200_TXA_REPL_ARG_A_SHIFT␉26␊
3268# define R200_TXA_REPL_ARG_A_MASK␉␉(3 << 26)␊
3269# define R200_TXA_REPL_ARG_B_SHIFT␉28␊
3270# define R200_TXA_REPL_ARG_B_MASK␉␉(3 << 28)␊
3271# define R200_TXA_REPL_ARG_C_SHIFT␉30␊
3272# define R200_TXA_REPL_ARG_C_MASK␉␉(3 << 30)␊
3273#define R200_PP_TXCBLEND_1␉␉␉0x2f10␊
3274#define R200_PP_TXCBLEND2_1␉␉␉0x2f14␊
3275#define R200_PP_TXABLEND_1␉␉␉0x2f18␊
3276#define R200_PP_TXABLEND2_1␉␉␉0x2f1c␊
3277#define R200_PP_TXCBLEND_2␉␉␉0x2f20␊
3278#define R200_PP_TXCBLEND2_2␉␉␉0x2f24␊
3279#define R200_PP_TXABLEND_2␉␉␉0x2f28␊
3280#define R200_PP_TXABLEND2_2␉␉␉0x2f2c␊
3281#define R200_PP_TXCBLEND_3␉␉␉0x2f30␊
3282#define R200_PP_TXCBLEND2_3␉␉␉0x2f34␊
3283#define R200_PP_TXABLEND_3␉␉␉0x2f38␊
3284#define R200_PP_TXABLEND2_3␉␉␉0x2f3c␊
3285␊
3286#define R200_SE_VTX_FMT_0␉␉␉0x2088␊
3287# define R200_VTX_XY␉␉␉0 /* always have xy */␊
3288# define R200_VTX_Z0␉␉␉(1<<0)␊
3289# define R200_VTX_W0␉␉␉(1<<1)␊
3290# define R200_VTX_WEIGHT_COUNT_SHIFT␉(2)␊
3291# define R200_VTX_PV_MATRIX_SEL␉␉(1<<5)␊
3292# define R200_VTX_N0␉␉␉(1<<6)␊
3293# define R200_VTX_POINT_SIZE␉␉(1<<7)␊
3294# define R200_VTX_DISCRETE_FOG␉␉(1<<8)␊
3295# define R200_VTX_SHININESS_0␉␉(1<<9)␊
3296# define R200_VTX_SHININESS_1␉␉(1<<10)␊
3297# define R200_VTX_COLOR_NOT_PRESENT␉0␊
3298# define R200_VTX_PK_RGBA␉␉1␊
3299# define R200_VTX_FP_RGB␉␉2␊
3300# define R200_VTX_FP_RGBA␉␉3␊
3301# define R200_VTX_COLOR_MASK␉␉3␊
3302# define R200_VTX_COLOR_0_SHIFT␉␉11␊
3303# define R200_VTX_COLOR_1_SHIFT␉␉13␊
3304# define R200_VTX_COLOR_2_SHIFT␉␉15␊
3305# define R200_VTX_COLOR_3_SHIFT␉␉17␊
3306# define R200_VTX_COLOR_4_SHIFT␉␉19␊
3307# define R200_VTX_COLOR_5_SHIFT␉␉21␊
3308# define R200_VTX_COLOR_6_SHIFT␉␉23␊
3309# define R200_VTX_COLOR_7_SHIFT␉␉25␊
3310# define R200_VTX_XY1␉␉␉(1<<28)␊
3311# define R200_VTX_Z1␉␉␉(1<<29)␊
3312# define R200_VTX_W1␉␉␉(1<<30)␊
3313# define R200_VTX_N1␉␉␉(1<<31)␊
3314#define R200_SE_VTX_FMT_1␉␉␉0x208c␊
3315# define R200_VTX_TEX0_COMP_CNT_SHIFT␉0␊
3316# define R200_VTX_TEX1_COMP_CNT_SHIFT␉3␊
3317# define R200_VTX_TEX2_COMP_CNT_SHIFT␉6␊
3318# define R200_VTX_TEX3_COMP_CNT_SHIFT␉9␊
3319# define R200_VTX_TEX4_COMP_CNT_SHIFT␉12␊
3320# define R200_VTX_TEX5_COMP_CNT_SHIFT␉15␊
3321␊
3322#define R200_SE_TCL_OUTPUT_VTX_FMT_0␉␉0x2090␊
3323#define R200_SE_TCL_OUTPUT_VTX_FMT_1␉␉0x2094␊
3324#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL␉␉0x2250␊
3325# define R200_OUTPUT_XYZW␉␉␉(1<<0)␊
3326# define R200_OUTPUT_COLOR_0␉␉(1<<8)␊
3327# define R200_OUTPUT_COLOR_1␉␉(1<<9)␊
3328# define R200_OUTPUT_TEX_0␉␉(1<<16)␊
3329# define R200_OUTPUT_TEX_1␉␉(1<<17)␊
3330# define R200_OUTPUT_TEX_2␉␉(1<<18)␊
3331# define R200_OUTPUT_TEX_3␉␉(1<<19)␊
3332# define R200_OUTPUT_TEX_4␉␉(1<<20)␊
3333# define R200_OUTPUT_TEX_5␉␉(1<<21)␊
3334# define R200_OUTPUT_TEX_MASK␉␉(0x3f<<16)␊
3335# define R200_OUTPUT_DISCRETE_FOG␉␉(1<<24)␊
3336# define R200_OUTPUT_PT_SIZE␉␉(1<<25)␊
3337# define R200_FORCE_INORDER_PROC␉␉(1<<31)␊
3338#define R200_PP_CNTL_X␉␉␉␉0x2cc4␊
3339#define R200_PP_TXMULTI_CTL_0␉␉␉0x2c1c␊
3340#define R200_SE_VTX_STATE_CNTL␉␉␉0x2180␊
3341# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)␊
3342␊
3343␉␉␉␉/* Registers for CP and Microcode Engine */␊
3344#define RADEON_CP_ME_RAM_ADDR 0x07d4␊
3345#define RADEON_CP_ME_RAM_RADDR 0x07d8␊
3346#define RADEON_CP_ME_RAM_DATAH 0x07dc␊
3347#define RADEON_CP_ME_RAM_DATAL 0x07e0␊
3348␊
3349#define RADEON_CP_RB_BASE 0x0700␊
3350#define RADEON_CP_RB_CNTL 0x0704␊
3351#define RADEON_CP_RB_RPTR_ADDR 0x070c␊
3352#define RADEON_CP_RB_RPTR 0x0710␊
3353#define RADEON_CP_RB_WPTR 0x0714␊
3354␊
3355#define RADEON_CP_IB_BASE 0x0738␊
3356#define RADEON_CP_IB_BUFSZ 0x073c␊
3357␊
3358#define RADEON_CP_CSQ_CNTL 0x0740␊
3359# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)␊
3360# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)␊
3361# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)␊
3362# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)␊
3363# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)␊
3364# define RADEON_CSQ_PRIBM_INDBM (4 << 28)␊
3365# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)␊
3366#define RADEON_CP_CSQ_STAT 0x07f8␊
3367# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)␊
3368# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)␊
3369# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)␊
3370# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)␊
3371#define RADEON_CP_CSQ_ADDR 0x07f0␊
3372#define RADEON_CP_CSQ_DATA 0x07f4␊
3373#define RADEON_CP_CSQ_APER_PRIMARY 0x1000␊
3374#define RADEON_CP_CSQ_APER_INDIRECT 0x1300␊
3375␊
3376#define RADEON_CP_RB_WPTR_DELAY 0x0718␊
3377# define RADEON_PRE_WRITE_TIMER_SHIFT 0␊
3378# define RADEON_PRE_WRITE_LIMIT_SHIFT 23␊
3379␊
3380#define RADEON_AIC_CNTL 0x01d0␊
3381# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)␊
3382#define RADEON_AIC_LO_ADDR 0x01dc␊
3383␊
3384␊
3385␊
3386␉␉␉␉/* Constants */␊
3387#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0␊
3388#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2␊
3389␊
3390␊
3391␊
3392␉␉␉␉/* CP packet types */␊
3393#define RADEON_CP_PACKET0 0x00000000␊
3394#define RADEON_CP_PACKET1 0x40000000␊
3395#define RADEON_CP_PACKET2 0x80000000␊
3396#define RADEON_CP_PACKET3 0xC0000000␊
3397# define RADEON_CP_PACKET_MASK 0xC0000000␊
3398# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000␊
3399# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)␊
3400# define RADEON_CP_PACKET0_REG_MASK 0x000007ff␊
3401# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff␊
3402# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800␊
3403␊
3404#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000␊
3405␊
3406#define RADEON_CP_PACKET3_NOP 0xC0001000␊
3407#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900␊
3408#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00␊
3409#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00␊
3410#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300␊
3411#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400␊
3412#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600␊
3413#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800␊
3414#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900␊
3415#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00␊
3416#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00␊
3417#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500␊
3418#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00␊
3419#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100␊
3420#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200␊
3421#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300␊
3422#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400␊
3423#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500␊
3424#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800␊
3425#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00␊
3426#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00␊
3427#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00␊
3428␊
3429␊
3430#define RADEON_CP_VC_FRMT_XY 0x00000000␊
3431#define RADEON_CP_VC_FRMT_W0 0x00000001␊
3432#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002␊
3433#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004␊
3434#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008␊
3435#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010␊
3436#define RADEON_CP_VC_FRMT_FPFOG 0x00000020␊
3437#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040␊
3438#define RADEON_CP_VC_FRMT_ST0 0x00000080␊
3439#define RADEON_CP_VC_FRMT_ST1 0x00000100␊
3440#define RADEON_CP_VC_FRMT_Q1 0x00000200␊
3441#define RADEON_CP_VC_FRMT_ST2 0x00000400␊
3442#define RADEON_CP_VC_FRMT_Q2 0x00000800␊
3443#define RADEON_CP_VC_FRMT_ST3 0x00001000␊
3444#define RADEON_CP_VC_FRMT_Q3 0x00002000␊
3445#define RADEON_CP_VC_FRMT_Q0 0x00004000␊
3446#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000␊
3447#define RADEON_CP_VC_FRMT_N0 0x00040000␊
3448#define RADEON_CP_VC_FRMT_XY1 0x08000000␊
3449#define RADEON_CP_VC_FRMT_Z1 0x10000000␊
3450#define RADEON_CP_VC_FRMT_W1 0x20000000␊
3451#define RADEON_CP_VC_FRMT_N1 0x40000000␊
3452#define RADEON_CP_VC_FRMT_Z 0x80000000␊
3453␊
3454#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000␊
3455#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001␊
3456#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002␊
3457#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003␊
3458#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004␊
3459#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005␊
3460#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006␊
3461#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007␊
3462#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008␊
3463#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009␊
3464#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a␊
3465#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d␊
3466#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010␊
3467#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020␊
3468#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030␊
3469#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000␊
3470#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040␊
3471#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080␊
3472#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000␊
3473#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100␊
3474#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000␊
3475#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200␊
3476#define RADEON_CP_VC_CNTL_NUM_SHIFT 16␊
3477␊
3478#define RADEON_VS_MATRIX_0_ADDR 0␊
3479#define RADEON_VS_MATRIX_1_ADDR 4␊
3480#define RADEON_VS_MATRIX_2_ADDR 8␊
3481#define RADEON_VS_MATRIX_3_ADDR 12␊
3482#define RADEON_VS_MATRIX_4_ADDR 16␊
3483#define RADEON_VS_MATRIX_5_ADDR 20␊
3484#define RADEON_VS_MATRIX_6_ADDR 24␊
3485#define RADEON_VS_MATRIX_7_ADDR 28␊
3486#define RADEON_VS_MATRIX_8_ADDR 32␊
3487#define RADEON_VS_MATRIX_9_ADDR 36␊
3488#define RADEON_VS_MATRIX_10_ADDR 40␊
3489#define RADEON_VS_MATRIX_11_ADDR 44␊
3490#define RADEON_VS_MATRIX_12_ADDR 48␊
3491#define RADEON_VS_MATRIX_13_ADDR 52␊
3492#define RADEON_VS_MATRIX_14_ADDR 56␊
3493#define RADEON_VS_MATRIX_15_ADDR 60␊
3494#define RADEON_VS_LIGHT_AMBIENT_ADDR 64␊
3495#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72␊
3496#define RADEON_VS_LIGHT_SPECULAR_ADDR 80␊
3497#define RADEON_VS_LIGHT_DIRPOS_ADDR 88␊
3498#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96␊
3499#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104␊
3500#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112␊
3501#define RADEON_VS_UCP_ADDR 116␊
3502#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122␊
3503#define RADEON_VS_FOG_PARAM_ADDR 123␊
3504#define RADEON_VS_EYE_VECTOR_ADDR 124␊
3505␊
3506#define RADEON_SS_LIGHT_DCD_ADDR 0␊
3507#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8␊
3508#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16␊
3509#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24␊
3510#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32␊
3511#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48␊
3512#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49␊
3513#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50␊
3514#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51␊
3515#define RADEON_SS_SHININESS 60␊
3516␊
3517#define RADEON_TV_MASTER_CNTL 0x0800␊
3518# define RADEON_TV_ASYNC_RST (1 << 0)␊
3519# define RADEON_CRT_ASYNC_RST (1 << 1)␊
3520# define RADEON_RESTART_PHASE_FIX (1 << 3)␊
3521#␉define RADEON_TV_FIFO_ASYNC_RST␉␉ (1 << 4)␊
3522#␉define RADEON_VIN_ASYNC_RST␉␉ (1 << 5)␊
3523#␉define RADEON_AUD_ASYNC_RST␉␉ (1 << 6)␊
3524#␉define RADEON_DVS_ASYNC_RST␉␉ (1 << 7)␊
3525# define RADEON_CRT_FIFO_CE_EN (1 << 9)␊
3526# define RADEON_TV_FIFO_CE_EN (1 << 10)␊
3527# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)␊
3528# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)␊
3529#␉define RADEON_TV_ON␉␉␉ (1 << 31)␊
3530#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888␊
3531# define RADEON_Y_RED_EN (1 << 0)␊
3532# define RADEON_C_GRN_EN (1 << 1)␊
3533# define RADEON_CMP_BLU_EN (1 << 2)␊
3534# define RADEON_DAC_DITHER_EN (1 << 3)␊
3535# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)␊
3536# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)␊
3537# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)␊
3538# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16␊
3539#define RADEON_TV_RGB_CNTL 0x0804␊
3540# define RADEON_SWITCH_TO_BLUE␉␉ (1 << 4)␊
3541# define RADEON_RGB_DITHER_EN␉␉ (1 << 5)␊
3542# define RADEON_RGB_SRC_SEL_MASK␉␉ (3 << 8)␊
3543# define RADEON_RGB_SRC_SEL_CRTC1␉␉ (0 << 8)␊
3544# define RADEON_RGB_SRC_SEL_RMX␉␉ (1 << 8)␊
3545# define RADEON_RGB_SRC_SEL_CRTC2␉␉ (2 << 8)␊
3546# define RADEON_RGB_CONVERT_BY_PASS␉ (1 << 10)␊
3547# define RADEON_UVRAM_READ_MARGIN_SHIFT␉ 16␊
3548# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT␉ 20␊
3549#␉define RADEON_RGB_ATTEN_SEL(x) ␉␉ ((x) << 24)␊
3550#␉define RADEON_TVOUT_SCALE_EN ␉␉ (1 << 26)␊
3551#␉define RADEON_RGB_ATTEN_VAL(x) ␉␉ ((x) << 28)␊
3552#define RADEON_TV_SYNC_CNTL 0x0808␊
3553# define RADEON_SYNC_OE (1 << 0)␊
3554# define RADEON_SYNC_OUT (1 << 1)␊
3555# define RADEON_SYNC_IN (1 << 2)␊
3556# define RADEON_SYNC_PUB (1 << 3)␊
3557# define RADEON_SYNC_PD (1 << 4)␊
3558# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)␊
3559#define RADEON_TV_HTOTAL 0x080c␊
3560#define RADEON_TV_HDISP 0x0810␊
3561#define RADEON_TV_HSTART 0x0818␊
3562#define RADEON_TV_HCOUNT 0x081C␊
3563#define RADEON_TV_VTOTAL 0x0820␊
3564#define RADEON_TV_VDISP 0x0824␊
3565#define RADEON_TV_VCOUNT 0x0828␊
3566#define RADEON_TV_FTOTAL 0x082c␊
3567#define RADEON_TV_FCOUNT 0x0830␊
3568#define RADEON_TV_FRESTART 0x0834␊
3569#define RADEON_TV_HRESTART 0x0838␊
3570#define RADEON_TV_VRESTART 0x083c␊
3571#define RADEON_TV_HOST_READ_DATA 0x0840␊
3572#define RADEON_TV_HOST_WRITE_DATA 0x0844␊
3573#define RADEON_TV_HOST_RD_WT_CNTL 0x0848␊
3574#␉define RADEON_HOST_FIFO_RD␉␉ (1 << 12)␊
3575#␉define RADEON_HOST_FIFO_RD_ACK␉␉ (1 << 13)␊
3576#␉define RADEON_HOST_FIFO_WT␉␉ (1 << 14)␊
3577#␉define RADEON_HOST_FIFO_WT_ACK␉␉ (1 << 15)␊
3578#define RADEON_TV_VSCALER_CNTL1 0x084c␊
3579# define RADEON_UV_INC_MASK 0xffff␊
3580# define RADEON_UV_INC_SHIFT 0␊
3581# define RADEON_Y_W_EN␉␉␉ (1 << 24)␊
3582# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */␊
3583# define RADEON_Y_DEL_W_SIG_SHIFT 26␊
3584#define RADEON_TV_TIMING_CNTL 0x0850␊
3585# define RADEON_H_INC_MASK 0xfff␊
3586# define RADEON_H_INC_SHIFT 0␊
3587# define RADEON_REQ_Y_FIRST (1 << 19)␊
3588# define RADEON_FORCE_BURST_ALWAYS (1 << 21)␊
3589# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)␊
3590# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24␊
3591#define RADEON_TV_VSCALER_CNTL2 0x0854␊
3592# define RADEON_DITHER_MODE (1 << 0)␊
3593# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)␊
3594# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)␊
3595# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)␊
3596#define RADEON_TV_Y_FALL_CNTL 0x0858␊
3597# define RADEON_Y_FALL_PING_PONG (1 << 16)␊
3598# define RADEON_Y_COEF_EN (1 << 17)␊
3599#define RADEON_TV_Y_RISE_CNTL 0x085c␊
3600# define RADEON_Y_RISE_PING_PONG (1 << 16)␊
3601#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860␊
3602#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864␊
3603#␉define RADEON_YUPSAMP_EN␉␉ (1 << 0)␊
3604#␉define RADEON_UVUPSAMP_EN␉␉ (1 << 2)␊
3605#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868␊
3606# define RADEON_Y_GAIN_LIMIT_SHIFT 0␊
3607# define RADEON_UV_GAIN_LIMIT_SHIFT 16␊
3608#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c␊
3609# define RADEON_Y_GAIN_SHIFT 0␊
3610# define RADEON_UV_GAIN_SHIFT 16␊
3611#define RADEON_TV_MODULATOR_CNTL1 0x0870␊
3612#␉define RADEON_YFLT_EN␉␉␉ (1 << 2)␊
3613#␉define RADEON_UVFLT_EN␉␉␉ (1 << 3)␊
3614# define RADEON_ALT_PHASE_EN (1 << 6)␊
3615# define RADEON_SYNC_TIP_LEVEL (1 << 7)␊
3616# define RADEON_BLANK_LEVEL_SHIFT 8␊
3617# define RADEON_SET_UP_LEVEL_SHIFT 16␊
3618#␉define RADEON_SLEW_RATE_LIMIT␉␉ (1 << 23)␊
3619# define RADEON_CY_FILT_BLEND_SHIFT 28␊
3620#define RADEON_TV_MODULATOR_CNTL2 0x0874␊
3621# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff␊
3622# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff␊
3623# define RADEON_TV_V_BURST_LEVEL_SHIFT 16␊
3624#define RADEON_TV_CRC_CNTL 0x0890␊
3625#define RADEON_TV_UV_ADR 0x08ac␊
3626#␉define RADEON_MAX_UV_ADR_MASK␉␉ 0x000000ff␊
3627#␉define RADEON_MAX_UV_ADR_SHIFT␉␉ 0␊
3628#␉define RADEON_TABLE1_BOT_ADR_MASK␉ 0x0000ff00␊
3629#␉define RADEON_TABLE1_BOT_ADR_SHIFT␉ 8␊
3630#␉define RADEON_TABLE3_TOP_ADR_MASK␉ 0x00ff0000␊
3631#␉define RADEON_TABLE3_TOP_ADR_SHIFT␉ 16␊
3632#␉define RADEON_HCODE_TABLE_SEL_MASK␉ 0x06000000␊
3633#␉define RADEON_HCODE_TABLE_SEL_SHIFT␉ 25␊
3634#␉define RADEON_VCODE_TABLE_SEL_MASK␉ 0x18000000␊
3635#␉define RADEON_VCODE_TABLE_SEL_SHIFT␉ 27␊
3636#␉define RADEON_TV_MAX_FIFO_ADDR␉␉ 0x1a7␊
3637#␉define RADEON_TV_MAX_FIFO_ADDR_INTERNAL␉ 0x1ff␊
3638#define RADEON_TV_PLL_FINE_CNTL␉␉␉ 0x0020␉/* PLL */␊
3639#define RADEON_TV_PLL_CNTL 0x0021␉/* PLL */␊
3640# define RADEON_TV_M0LO_MASK 0xff␊
3641# define RADEON_TV_M0HI_MASK 0x7␊
3642# define RADEON_TV_M0HI_SHIFT 18␊
3643# define RADEON_TV_N0LO_MASK 0x1ff␊
3644# define RADEON_TV_N0LO_SHIFT 8␊
3645# define RADEON_TV_N0HI_MASK 0x3␊
3646# define RADEON_TV_N0HI_SHIFT 21␊
3647# define RADEON_TV_P_MASK 0xf␊
3648# define RADEON_TV_P_SHIFT 24␊
3649# define RADEON_TV_SLIP_EN (1 << 23)␊
3650# define RADEON_TV_DTO_EN (1 << 28)␊
3651#define RADEON_TV_PLL_CNTL1 0x0022␉/* PLL */␊
3652# define RADEON_TVPLL_RESET (1 << 1)␊
3653# define RADEON_TVPLL_SLEEP (1 << 3)␊
3654# define RADEON_TVPLL_REFCLK_SEL (1 << 4)␊
3655# define RADEON_TVPCP_SHIFT 8␊
3656# define RADEON_TVPCP_MASK (7 << 8)␊
3657# define RADEON_TVPVG_SHIFT 11␊
3658# define RADEON_TVPVG_MASK (7 << 11)␊
3659# define RADEON_TVPDC_SHIFT 14␊
3660# define RADEON_TVPDC_MASK (3 << 14)␊
3661# define RADEON_TVPLL_TEST_DIS (1 << 31)␊
3662# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)␊
3663␊
3664#define RS400_DISP2_REQ_CNTL1␉␉␉0xe30␊
3665# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0␊
3666# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff␊
3667# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12␊
3668# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff␊
3669# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22␊
3670# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff␊
3671#define RS400_DISP2_REQ_CNTL2␉␉␉0xe34␊
3672# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12␊
3673# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff␊
3674# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22␊
3675# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff␊
3676#define RS400_DMIF_MEM_CNTL1␉␉␉0xe38␊
3677# define RS400_DISP2_START_ADR_SHIFT 0␊
3678# define RS400_DISP2_START_ADR_MASK 0x3ff␊
3679# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12␊
3680# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff␊
3681# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22␊
3682# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff␊
3683#define RS400_DISP1_REQ_CNTL1␉␉␉0xe3c␊
3684# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0␊
3685# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff␊
3686# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12␊
3687# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff␊
3688# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22␊
3689# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff␊
3690␊
3691#define RS690_MC_INDEX␉␉␉␉0x78␊
3692#␉define RS690_MC_INDEX_MASK␉␉0x1ff␊
3693#␉define RS690_MC_INDEX_WR_EN␉␉(1 << 9)␊
3694#␉define RS690_MC_INDEX_WR_ACK␉␉0x7f␊
3695#define RS690_MC_DATA␉␉␉␉0x7c␊
3696␊
3697#define RS690_MC_FB_LOCATION␉␉␉0x100␊
3698#define RS690_MC_AGP_LOCATION␉␉␉0x101␊
3699#define RS690_MC_AGP_BASE␉␉␉0x102␊
3700#define RS690_MC_AGP_BASE_2 0x103␊
3701#define RS690_MC_INIT_MISC_LAT_TIMER 0x104␊
3702#define RS690_MC_STATUS 0x90␊
3703#define RS690_MC_STATUS_IDLE (1 << 0)␊
3704␊
3705#define RS600_MC_INDEX 0x70␊
3706#␉define RS600_MC_ADDR_MASK␉␉0xffff␊
3707# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)␊
3708# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)␊
3709# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)␊
3710# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)␊
3711# define RS600_MC_IND_AIC_RBS (1 << 20)␊
3712# define RS600_MC_IND_CITF_ARB0 (1 << 21)␊
3713# define RS600_MC_IND_CITF_ARB1 (1 << 22)␊
3714# define RS600_MC_IND_WR_EN (1 << 23)␊
3715#define RS600_MC_DATA 0x74␊
3716␊
3717#define RS600_MC_STATUS␉␉␉ 0x0␊
3718#␉define RS600_MC_IDLE␉␉ (1 << 1)␊
3719#define RS600_MC_FB_LOCATION 0x4␊
3720#define RS600_MC_AGP_LOCATION 0x5␊
3721#define RS600_AGP_BASE 0x6␊
3722#define RS600_AGP_BASE2 0x7␊
3723␊
3724#define AVIVO_MC_INDEX␉␉␉␉0x0070␊
3725#define R520_MC_STATUS 0x00␊
3726# define R520_MC_STATUS_IDLE (1 << 1)␊
3727#define RV515_MC_STATUS 0x08␊
3728# define RV515_MC_STATUS_IDLE (1 << 4)␊
3729#define RV515_MC_INIT_MISC_LAT_TIMER 0x09␊
3730#define AVIVO_MC_DATA␉␉␉␉0x0074␊
3731␊
3732#define RV515_MC_FB_LOCATION 0x1␊
3733#define RV515_MC_AGP_LOCATION 0x2␊
3734#define RV515_MC_AGP_BASE 0x3␊
3735#define RV515_MC_AGP_BASE_2 0x4␊
3736#define RV515_MC_CNTL 0x5␊
3737#␉define RV515_MEM_NUM_CHANNELS_MASK 0x3␊
3738#define R520_MC_FB_LOCATION 0x4␊
3739#define R520_MC_AGP_LOCATION 0x5␊
3740#define R520_MC_AGP_BASE 0x6␊
3741#define R520_MC_AGP_BASE_2 0x7␊
3742#define R520_MC_CNTL0 0x8␊
3743#␉define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)␊
3744#␉define R520_MEM_NUM_CHANNELS_SHIFT 24␊
3745#␉define R520_MC_CHANNEL_SIZE (1 << 23)␊
3746␊
3747#define RS780_MC_INDEX␉␉␉␉0x28f8␊
3748#␉define RS780_MC_INDEX_MASK␉␉0x1ff␊
3749#␉define RS780_MC_INDEX_WR_EN␉␉(1 << 9)␊
3750#define RS780_MC_DATA␉␉␉␉0x28fc␊
3751␊
3752#define R600_RAMCFG␉␉␉␉ 0x2408␊
3753# define R600_CHANSIZE (1 << 7)␊
3754# define R600_CHANSIZE_OVERRIDE (1 << 10)␊
3755␊
3756#define R600_SRBM_STATUS␉␉␉ 0x0e50␊
3757␊
3758#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */␊
3759# define AVIVO_CP_FORCEON (1 << 0)␊
3760#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */␊
3761# define AVIVO_E2_FORCEON (1 << 0)␊
3762#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */␊
3763# define AVIVO_IDCT_FORCEON (1 << 0)␊
3764␊
3765#define AVIVO_HDP_FB_LOCATION 0x134␊
3766␊
3767#define AVIVO_VGA_RENDER_CONTROL␉␉␉␉0x0300␊
3768# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)␊
3769#define AVIVO_D1VGA_CONTROL␉␉␉␉␉0x0330␊
3770# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)␊
3771# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)␊
3772# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)␊
3773# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)␊
3774# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)␊
3775# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)␊
3776#define AVIVO_D2VGA_CONTROL␉␉␉␉␉0x0338␊
3777␊
3778#define AVIVO_VGA25_PPLL_REF_DIV_SRC␉␉␉␉0x0360␊
3779#define AVIVO_VGA25_PPLL_REF_DIV␉␉␉␉0x0364␊
3780#define AVIVO_VGA28_PPLL_REF_DIV_SRC␉␉␉␉0x0368␊
3781#define AVIVO_VGA28_PPLL_REF_DIV␉␉␉␉0x036c␊
3782#define AVIVO_VGA41_PPLL_REF_DIV_SRC␉␉␉␉0x0370␊
3783#define AVIVO_VGA41_PPLL_REF_DIV␉␉␉␉0x0374␊
3784#define AVIVO_VGA25_PPLL_FB_DIV␉␉␉␉0x0378␊
3785#define AVIVO_VGA28_PPLL_FB_DIV␉␉␉␉0x037c␊
3786#define AVIVO_VGA41_PPLL_FB_DIV␉␉␉␉0x0380␊
3787#define AVIVO_VGA25_PPLL_POST_DIV_SRC␉␉␉␉0x0384␊
3788#define AVIVO_VGA25_PPLL_POST_DIV␉␉␉␉0x0388␊
3789#define AVIVO_VGA28_PPLL_POST_DIV_SRC␉␉␉␉0x038c␊
3790#define AVIVO_VGA28_PPLL_POST_DIV␉␉␉␉0x0390␊
3791#define AVIVO_VGA41_PPLL_POST_DIV_SRC␉␉␉␉0x0394␊
3792#define AVIVO_VGA41_PPLL_POST_DIV␉␉␉␉0x0398␊
3793#define AVIVO_VGA25_PPLL_CNTL␉␉␉␉␉0x039c␊
3794#define AVIVO_VGA28_PPLL_CNTL␉␉␉␉␉0x03a0␊
3795#define AVIVO_VGA41_PPLL_CNTL␉␉␉␉␉0x03a4␊
3796␊
3797#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400␊
3798#define AVIVO_EXT1_PPLL_REF_DIV 0x404␊
3799#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408␊
3800#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c␊
3801␊
3802#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410␊
3803#define AVIVO_EXT2_PPLL_REF_DIV 0x414␊
3804#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418␊
3805#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c␊
3806␊
3807#define AVIVO_EXT1_PPLL_FB_DIV 0x430␊
3808#define AVIVO_EXT2_PPLL_FB_DIV 0x434␊
3809␊
3810#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438␊
3811#define AVIVO_EXT1_PPLL_POST_DIV 0x43c␊
3812␊
3813#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440␊
3814#define AVIVO_EXT2_PPLL_POST_DIV 0x444␊
3815␊
3816#define AVIVO_EXT1_PPLL_CNTL 0x448␊
3817#define AVIVO_EXT2_PPLL_CNTL 0x44c␊
3818␊
3819#define AVIVO_P1PLL_CNTL 0x450␊
3820#define AVIVO_P2PLL_CNTL 0x454␊
3821#define AVIVO_P1PLL_INT_SS_CNTL 0x458␊
3822#define AVIVO_P2PLL_INT_SS_CNTL 0x45c␊
3823#define AVIVO_P1PLL_TMDSA_CNTL 0x460␊
3824#define AVIVO_P2PLL_LVTMA_CNTL 0x464␊
3825␊
3826#define AVIVO_PCLK_CRTC1_CNTL 0x480␊
3827#define AVIVO_PCLK_CRTC2_CNTL 0x484␊
3828␊
3829#define AVIVO_D1CRTC_H_TOTAL␉␉␉␉␉0x6000␊
3830#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004␊
3831#define AVIVO_D1CRTC_H_SYNC_A 0x6008␊
3832#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c␊
3833#define AVIVO_D1CRTC_H_SYNC_B 0x6010␊
3834#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014␊
3835␊
3836#define AVIVO_D1CRTC_V_TOTAL␉␉␉␉␉0x6020␊
3837#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024␊
3838#define AVIVO_D1CRTC_V_SYNC_A 0x6028␊
3839#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c␊
3840#define AVIVO_D1CRTC_V_SYNC_B 0x6030␊
3841#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034␊
3842␊
3843#define AVIVO_D1CRTC_CONTROL 0x6080␊
3844# define AVIVO_CRTC_EN (1<<0)␊
3845#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084␊
3846#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088␊
3847#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c␊
3848#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4␊
3849␊
3850/* master controls */␊
3851#define AVIVO_DC_CRTC_MASTER_EN 0x60f8␊
3852#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc␊
3853␊
3854#define AVIVO_D1GRPH_ENABLE 0x6100␊
3855#define AVIVO_D1GRPH_CONTROL 0x6104␊
3856# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)␊
3857# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)␊
3858# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)␊
3859# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)␊
3860␊
3861# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)␊
3862␊
3863# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)␊
3864# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)␊
3865# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)␊
3866# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)␊
3867# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)␊
3868␊
3869# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)␊
3870# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)␊
3871# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)␊
3872# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)␊
3873␊
3874␊
3875# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)␊
3876␊
3877# define AVIVO_D1GRPH_SWAP_RB (1<<16)␊
3878# define AVIVO_D1GRPH_TILED (1<<20)␊
3879# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)␊
3880␊
3881#define AVIVO_D1GRPH_LUT_SEL 0x6108␊
3882␊
3883#define R600_D1GRPH_SWAP_CONTROL 0x610C␊
3884# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)␊
3885# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)␊
3886# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)␊
3887# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)␊
3888␊
3889/* the *_HIGH surface regs are backwards; the D1 regs are in the D2␊
3890 * block and vice versa. This applies to GRPH, CUR, etc.␊
3891 */␊
3892␊
3893#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110␊
3894#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914␊
3895#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114␊
3896#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118␊
3897#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c␊
3898#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c␊
3899#define AVIVO_D1GRPH_PITCH 0x6120␊
3900#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124␊
3901#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128␊
3902#define AVIVO_D1GRPH_X_START 0x612c␊
3903#define AVIVO_D1GRPH_Y_START 0x6130␊
3904#define AVIVO_D1GRPH_X_END 0x6134␊
3905#define AVIVO_D1GRPH_Y_END 0x6138␊
3906#define AVIVO_D1GRPH_UPDATE 0x6144␊
3907# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)␊
3908#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148␊
3909␊
3910#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380␊
3911␊
3912#define AVIVO_D1CUR_CONTROL 0x6400␊
3913# define AVIVO_D1CURSOR_EN (1<<0)␊
3914# define AVIVO_D1CURSOR_MODE_SHIFT 8␊
3915# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)␊
3916# define AVIVO_D1CURSOR_MODE_24BPP (0x2)␊
3917#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408␊
3918#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c␊
3919#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c␊
3920#define AVIVO_D1CUR_SIZE 0x6410␊
3921#define AVIVO_D1CUR_POSITION 0x6414␊
3922#define AVIVO_D1CUR_HOT_SPOT 0x6418␊
3923#define AVIVO_D1CUR_UPDATE 0x6424␊
3924# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)␊
3925␊
3926#define AVIVO_DC_LUT_RW_SELECT 0x6480␊
3927#define AVIVO_DC_LUT_RW_MODE 0x6484␊
3928#define AVIVO_DC_LUT_RW_INDEX 0x6488␊
3929#define AVIVO_DC_LUT_SEQ_COLOR 0x648c␊
3930#define AVIVO_DC_LUT_PWL_DATA 0x6490␊
3931#define AVIVO_DC_LUT_30_COLOR 0x6494␊
3932#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498␊
3933#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c␊
3934#define AVIVO_DC_LUT_AUTOFILL 0x64a0␊
3935␊
3936#define AVIVO_DC_LUTA_CONTROL 0x64c0␊
3937#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4␊
3938#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8␊
3939#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc␊
3940#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0␊
3941#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4␊
3942#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8␊
3943␊
3944#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520␊
3945# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3␊
3946# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0␊
3947# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0␊
3948# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1␊
3949# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2␊
3950# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3␊
3951# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)␊
3952# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4␊
3953# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff␊
3954#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548␊
3955# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff␊
3956# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16)␊
3957# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20)␊
3958# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24)␊
3959#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c␊
3960#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48␊
3961#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c␊
3962#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58␊
3963# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf␊
3964# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0␊
3965# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf␊
3966# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16␊
3967␊
3968#define AVIVO_D1MODE_DATA_FORMAT 0x6528␊
3969# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)␊
3970#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c␊
3971#define AVIVO_D1MODE_VLINE_START_END 0x6538␊
3972# define AVIVO_D1MODE_VLINE_START_SHIFT 0␊
3973# define AVIVO_D1MODE_VLINE_END_SHIFT 16␊
3974# define AVIVO_D1MODE_VLINE_INV (1 << 31)␊
3975#define AVIVO_D1MODE_VLINE_STATUS 0x653c␊
3976# define AVIVO_D1MODE_VLINE_STAT (1 << 12)␊
3977#define AVIVO_D1MODE_VIEWPORT_START 0x6580␊
3978#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584␊
3979#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588␊
3980#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c␊
3981␊
3982#define AVIVO_D1SCL_SCALER_ENABLE 0x6590␊
3983#define AVIVO_D1SCL_SCALER_TAP_CONTROL␉ ␉0x6594␊
3984#define AVIVO_D1SCL_UPDATE 0x65cc␊
3985# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)␊
3986␊
3987/* second crtc */␊
3988#define AVIVO_D2CRTC_H_TOTAL␉␉␉␉␉0x6800␊
3989#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804␊
3990#define AVIVO_D2CRTC_H_SYNC_A 0x6808␊
3991#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c␊
3992#define AVIVO_D2CRTC_H_SYNC_B 0x6810␊
3993#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814␊
3994␊
3995#define AVIVO_D2CRTC_V_TOTAL␉␉␉␉␉0x6820␊
3996#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824␊
3997#define AVIVO_D2CRTC_V_SYNC_A 0x6828␊
3998#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c␊
3999#define AVIVO_D2CRTC_V_SYNC_B 0x6830␊
4000#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834␊
4001␊
4002#define AVIVO_D2CRTC_CONTROL 0x6880␊
4003#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884␊
4004#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888␊
4005#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c␊
4006#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4␊
4007␊
4008#define AVIVO_D2GRPH_ENABLE 0x6900␊
4009#define AVIVO_D2GRPH_CONTROL 0x6904␊
4010#define AVIVO_D2GRPH_LUT_SEL 0x6908␊
4011#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910␊
4012#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918␊
4013#define AVIVO_D2GRPH_PITCH 0x6920␊
4014#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924␊
4015#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928␊
4016#define AVIVO_D2GRPH_X_START 0x692c␊
4017#define AVIVO_D2GRPH_Y_START 0x6930␊
4018#define AVIVO_D2GRPH_X_END 0x6934␊
4019#define AVIVO_D2GRPH_Y_END 0x6938␊
4020#define AVIVO_D2GRPH_UPDATE 0x6944␊
4021#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948␊
4022␊
4023#define AVIVO_D2CUR_CONTROL 0x6c00␊
4024#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08␊
4025#define AVIVO_D2CUR_SIZE 0x6c10␊
4026#define AVIVO_D2CUR_POSITION 0x6c14␊
4027␊
4028#define RS690_DCP_CONTROL 0x6c9c␊
4029␊
4030#define AVIVO_D2MODE_DATA_FORMAT 0x6d28␊
4031#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c␊
4032#define AVIVO_D2MODE_VIEWPORT_START 0x6d80␊
4033#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84␊
4034#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88␊
4035#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c␊
4036␊
4037#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90␊
4038#define AVIVO_D2SCL_SCALER_TAP_CONTROL␉ ␉0x6d94␊
4039#define AVIVO_D2SCL_UPDATE 0x6dcc␊
4040␊
4041#define AVIVO_DDIA_BIT_DEPTH_CONTROL␉␉␉␉0x7214␊
4042␊
4043#define AVIVO_DACA_ENABLE␉␉␉␉␉0x7800␊
4044#␉define AVIVO_DAC_ENABLE␉␉␉␉(1 << 0)␊
4045#define AVIVO_DACA_SOURCE_SELECT␉␉␉␉0x7804␊
4046# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)␊
4047# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)␊
4048# define AVIVO_DAC_SOURCE_TV (2 << 0)␊
4049␊
4050#define AVIVO_DACA_FORCE_OUTPUT_CNTL␉␉␉␉0x783c␊
4051# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)␊
4052# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)␊
4053# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)␊
4054# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)␊
4055# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)␊
4056# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)␊
4057#define AVIVO_DACA_POWERDOWN␉␉␉␉␉0x7850␊
4058# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)␊
4059# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)␊
4060# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)␊
4061# define AVIVO_DACA_POWERDOWN_RED (1 << 24)␊
4062␊
4063#define AVIVO_DACB_ENABLE␉␉␉␉␉0x7a00␊
4064#define AVIVO_DACB_SOURCE_SELECT␉␉␉␉0x7a04␊
4065#define AVIVO_DACB_FORCE_OUTPUT_CNTL␉␉␉␉0x7a3c␊
4066# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)␊
4067# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)␊
4068# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)␊
4069# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)␊
4070# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)␊
4071# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)␊
4072#define AVIVO_DACB_POWERDOWN␉␉␉␉␉0x7a50␊
4073# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)␊
4074# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)␊
4075# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)␊
4076# define AVIVO_DACB_POWERDOWN_RED ␊
4077␊
4078#define AVIVO_TMDSA_CNTL 0x7880␊
4079# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)␊
4080# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)␊
4081# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)␊
4082# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)␊
4083# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)␊
4084# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)␊
4085# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)␊
4086#define AVIVO_TMDSA_SOURCE_SELECT␉␉␉␉0x7884␊
4087/* 78a8 appears to be some kind of (reasonably tolerant) clock?␊
4088 * 78d0 definitely hits the transmitter, definitely clock. */␊
4089/* MYSTERY1 This appears to control dithering? */␊
4090#define AVIVO_TMDSA_BIT_DEPTH_CONTROL␉␉0x7894␊
4091# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)␊
4092# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)␊
4093# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)␊
4094# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)␊
4095# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)␊
4096# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)␊
4097# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)␊
4098# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)␊
4099#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0␊
4100# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)␊
4101# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)␊
4102# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)␊
4103# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)␊
4104#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8␊
4105# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)␊
4106# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)␊
4107#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900␊
4108#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904␊
4109# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)␊
4110# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)␊
4111# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)␊
4112# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)␊
4113# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)␊
4114# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)␊
4115# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)␊
4116# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)␊
4117# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)␊
4118# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)␊
4119# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)␊
4120# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)␊
4121␊
4122#define AVIVO_TMDSA_TRANSMITTER_CONTROL␉␉␉␉0x7910␊
4123#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE␉(1 << 0)␊
4124#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET ␉(1 << 1)␊
4125#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT␉(2)␊
4126#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL␉ (1 << 4)␊
4127# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)␊
4128#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN␉(1 << 6)␊
4129#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK␉ (1 << 8)␊
4130#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS␉(1 << 13)␊
4131#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK␉ (1 << 14)␊
4132#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS␉(1 << 15)␊
4133# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)␊
4134#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL␉(1 << 28)␊
4135# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)␊
4136#␉define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL␉(1 << 31)␊
4137␊
4138#define AVIVO_LVTMA_CNTL␉␉␉␉␉0x7a80␊
4139# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)␊
4140# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)␊
4141# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)␊
4142# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)␊
4143# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)␊
4144# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)␊
4145# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)␊
4146#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84␊
4147#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88␊
4148#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94␊
4149# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)␊
4150# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)␊
4151# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)␊
4152# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)␊
4153# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)␊
4154# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)␊
4155# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)␊
4156# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)␊
4157␊
4158␊
4159␊
4160#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0␊
4161# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)␊
4162# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)␊
4163# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)␊
4164# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)␊
4165␊
4166#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8␊
4167# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)␊
4168# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)␊
4169#define R500_LVTMA_CLOCK_ENABLE␉␉␉0x7b00␊
4170#define R600_LVTMA_CLOCK_ENABLE␉␉␉0x7b04␊
4171␊
4172#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04␊
4173#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08␊
4174# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)␊
4175# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)␊
4176# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)␊
4177# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)␊
4178# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)␊
4179# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)␊
4180# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)␊
4181# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)␊
4182# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)␊
4183# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)␊
4184# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)␊
4185␊
4186#define R500_LVTMA_TRANSMITTER_CONTROL␉␉␉ 0x7b10␊
4187#define R600_LVTMA_TRANSMITTER_CONTROL␉␉␉ 0x7b14␊
4188#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE␉ (1 << 0)␊
4189#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET ␉ (1 << 1)␊
4190#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)␊
4191#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL␉ (1 << 4)␊
4192# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)␊
4193#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN␉ (1 << 6)␊
4194#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK␉ (1 << 8)␊
4195#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS␉ (1 << 13)␊
4196#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK␉ (1 << 14)␊
4197#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS␉ (1 << 15)␊
4198# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)␊
4199#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL␉ (1 << 28)␊
4200# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)␊
4201#␉define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)␊
4202␊
4203#define R500_LVTMA_PWRSEQ_CNTL␉␉␉␉␉␉0x7af0␊
4204#define R600_LVTMA_PWRSEQ_CNTL␉␉␉␉␉␉0x7af4␊
4205#␉define AVIVO_LVTMA_PWRSEQ_EN␉␉␉␉␉ (1 << 0)␊
4206#␉define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK␉␉␉ (1 << 2)␊
4207#␉define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK␉␉␉ (1 << 3)␊
4208#␉define AVIVO_LVTMA_PWRSEQ_TARGET_STATE␉␉␉␉ (1 << 4)␊
4209#␉define AVIVO_LVTMA_SYNCEN␉␉␉␉␉ (1 << 8)␊
4210#␉define AVIVO_LVTMA_SYNCEN_OVRD␉␉␉␉␉ (1 << 9)␊
4211#␉define AVIVO_LVTMA_SYNCEN_POL␉␉␉␉␉ (1 << 10)␊
4212#␉define AVIVO_LVTMA_DIGON␉␉␉␉␉ (1 << 16)␊
4213#␉define AVIVO_LVTMA_DIGON_OVRD␉␉␉␉␉ (1 << 17)␊
4214#␉define AVIVO_LVTMA_DIGON_POL␉␉␉␉␉ (1 << 18)␊
4215#␉define AVIVO_LVTMA_BLON␉␉␉␉␉␉ (1 << 24)␊
4216#␉define AVIVO_LVTMA_BLON_OVRD␉␉␉␉␉ (1 << 25)␊
4217#␉define AVIVO_LVTMA_BLON_POL␉␉␉␉␉ (1 << 26)␊
4218␊
4219#define R500_LVTMA_PWRSEQ_STATE 0x7af4␊
4220#define R600_LVTMA_PWRSEQ_STATE 0x7af8␊
4221# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)␊
4222# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)␊
4223# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)␊
4224# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)␊
4225# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)␊
4226# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)␊
4227␊
4228#define AVIVO_LVDS_BACKLIGHT_CNTL␉␉␉0x7af8␊
4229#␉define AVIVO_LVDS_BACKLIGHT_CNTL_EN␉␉␉(1 << 0)␊
4230#␉define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK␉␉0x0000ff00␊
4231#␉define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT␉␉8␊
4232␊
4233#define AVIVO_DVOA_BIT_DEPTH_CONTROL␉␉␉0x7988␊
4234␊
4235#define AVIVO_GPIO_0 0x7e30␊
4236#define AVIVO_GPIO_1 0x7e40␊
4237#define AVIVO_GPIO_2 0x7e50␊
4238#define AVIVO_GPIO_3 0x7e60␊
4239␊
4240#define AVIVO_DC_GPIO_HPD_MASK 0x7e90␊
4241#define AVIVO_DC_GPIO_HPD_A 0x7e94␊
4242#define AVIVO_DC_GPIO_HPD_EN 0x7e98␊
4243#define AVIVO_DC_GPIO_HPD_Y 0x7e9c␊
4244␊
4245#define AVIVO_I2C_STATUS␉␉␉␉␉0x7d30␊
4246#␉define AVIVO_I2C_STATUS_DONE␉␉␉␉(1 << 0)␊
4247#␉define AVIVO_I2C_STATUS_NACK␉␉␉␉(1 << 1)␊
4248#␉define AVIVO_I2C_STATUS_HALT␉␉␉␉(1 << 2)␊
4249#␉define AVIVO_I2C_STATUS_GO␉␉␉␉(1 << 3)␊
4250#␉define AVIVO_I2C_STATUS_MASK␉␉␉␉0x7␊
4251/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe␊
4252 * DONE? */␊
4253#␉define AVIVO_I2C_STATUS_CMD_RESET␉␉␉0x7␊
4254#␉define AVIVO_I2C_STATUS_CMD_WAIT␉␉␉(1 << 3)␊
4255#define AVIVO_I2C_STOP␉␉␉␉␉␉0x7d34␊
4256#define AVIVO_I2C_START_CNTL␉␉␉␉0x7d38␊
4257#␉define AVIVO_I2C_START␉␉␉␉␉␉(1 << 8)␊
4258#␉define AVIVO_I2C_CONNECTOR0␉␉␉␉␉(0 << 16)␊
4259#␉define AVIVO_I2C_CONNECTOR1␉␉␉␉␉(1 << 16)␊
4260#define R520_I2C_START (1<<0)␊
4261#define R520_I2C_STOP (1<<1)␊
4262#define R520_I2C_RX (1<<2)␊
4263#define R520_I2C_EN (1<<8)␊
4264#define R520_I2C_DDC1 (0<<16)␊
4265#define R520_I2C_DDC2 (1<<16)␊
4266#define R520_I2C_DDC3 (2<<16)␊
4267#define R520_I2C_DDC_MASK (3<<16)␊
4268#define AVIVO_I2C_CONTROL2␉␉␉␉␉0x7d3c␊
4269#␉define AVIVO_I2C_7D3C_SIZE_SHIFT␉␉␉8␊
4270#␉define AVIVO_I2C_7D3C_SIZE_MASK␉␉␉␉(0xf << 8)␊
4271#define AVIVO_I2C_CONTROL3␉␉␉␉␉␉0x7d40␊
4272/* Reading is done 4 bytes at a time: read the bottom 8 bits from␊
4273 * 7d44, four times in a row.␊
4274 * Writing is a little more complex. First write DATA with␊
4275 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic␊
4276 * magic number, zz is, I think, the slave address, and yy is the byte␊
4277 * you want to write. */␊
4278#define AVIVO_I2C_DATA␉␉␉␉␉␉0x7d44␊
4279#define R520_I2C_ADDR_COUNT_MASK (0x7)␊
4280#define R520_I2C_DATA_COUNT_SHIFT (8)␊
4281#define R520_I2C_DATA_COUNT_MASK (0xF00)␊
4282#define AVIVO_I2C_CNTL␉␉␉␉␉␉0x7d50␊
4283#␉define AVIVO_I2C_EN␉␉␉␉␉␉␉(1 << 0)␊
4284#␉define AVIVO_I2C_RESET␉␉␉␉␉␉(1 << 8)␊
4285␊
4286#define R600_GENERAL_PWRMGT 0x618␊
4287#␉define R600_OPEN_DRAIN_PADS␉␉␉␉ (1 << 11)␊
4288␊
4289#define R600_LOWER_GPIO_ENABLE 0x710␊
4290#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718␊
4291#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c␊
4292#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720␊
4293#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724␊
4294␊
4295#define R600_MC_VM_FB_LOCATION 0x2180␊
4296#define R600_MC_VM_AGP_TOP 0x2184␊
4297#define R600_MC_VM_AGP_BOT 0x2188␊
4298#define R600_MC_VM_AGP_BASE 0x218c␊
4299#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190␊
4300#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194␊
4301#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198␊
4302␊
4303#define R700_MC_VM_FB_LOCATION 0x2024␊
4304#define R700_MC_VM_AGP_TOP 0x2028␊
4305#define R700_MC_VM_AGP_BOT 0x202c␊
4306#define R700_MC_VM_AGP_BASE 0x2030␊
4307␊
4308#define R600_HDP_NONSURFACE_BASE 0x2c04␊
4309␊
4310#define R600_BUS_CNTL 0x5420␊
4311#define R600_CONFIG_CNTL 0x5424␊
4312#define R600_CONFIG_MEMSIZE 0x5428␊
4313#define R600_CONFIG_F0_BASE 0x542C␊
4314#define R600_CONFIG_APER_SIZE 0x5430␊
4315␊
4316#define R600_ROM_CNTL 0x1600␊
4317# define R600_SCK_OVERWRITE (1 << 1)␊
4318# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28␊
4319# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)␊
4320␊
4321#define R600_CG_SPLL_FUNC_CNTL 0x600␊
4322# define R600_SPLL_BYPASS_EN (1 << 3)␊
4323#define R600_CG_SPLL_STATUS 0x60c␊
4324# define R600_SPLL_CHG_STATUS (1 << 1)␊
4325␊
4326#define R600_BIOS_0_SCRATCH 0x1724␊
4327#define R600_BIOS_1_SCRATCH 0x1728␊
4328#define R600_BIOS_2_SCRATCH 0x172c␊
4329#define R600_BIOS_3_SCRATCH 0x1730␊
4330#define R600_BIOS_4_SCRATCH 0x1734␊
4331#define R600_BIOS_5_SCRATCH 0x1738␊
4332#define R600_BIOS_6_SCRATCH 0x173c␊
4333#define R600_BIOS_7_SCRATCH 0x1740␊
4334␊
4335/* evergreen */␊
4336#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310␊
4337#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324␊
4338#define EVERGREEN_D3VGA_CONTROL 0x3e0␊
4339#define EVERGREEN_D4VGA_CONTROL 0x3e4␊
4340#define EVERGREEN_D5VGA_CONTROL 0x3e8␊
4341#define EVERGREEN_D6VGA_CONTROL 0x3ec␊
4342␊
4343#define EVERGREEN_P1PLL_SS_CNTL 0x414␊
4344#define EVERGREEN_P2PLL_SS_CNTL 0x454␊
4345# define EVERGREEN_PxPLL_SS_EN (1 << 12)␊
4346/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */␊
4347#define EVERGREEN_GRPH_ENABLE 0x6800␊
4348#define EVERGREEN_GRPH_CONTROL 0x6804␊
4349# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)␊
4350# define EVERGREEN_GRPH_DEPTH_8BPP 0␊
4351# define EVERGREEN_GRPH_DEPTH_16BPP 1␊
4352# define EVERGREEN_GRPH_DEPTH_32BPP 2␊
4353# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)␊
4354/* 8 BPP */␊
4355# define EVERGREEN_GRPH_FORMAT_INDEXED 0␊
4356/* 16 BPP */␊
4357# define EVERGREEN_GRPH_FORMAT_ARGB1555 0␊
4358# define EVERGREEN_GRPH_FORMAT_ARGB565 1␊
4359# define EVERGREEN_GRPH_FORMAT_ARGB4444 2␊
4360# define EVERGREEN_GRPH_FORMAT_AI88 3␊
4361# define EVERGREEN_GRPH_FORMAT_MONO16 4␊
4362# define EVERGREEN_GRPH_FORMAT_BGRA5551 5␊
4363/* 32 BPP */␊
4364# define EVERGREEN_GRPH_FORMAT_ARGB8888 0␊
4365# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1␊
4366# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2␊
4367# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3␊
4368# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4␊
4369# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5␊
4370# define EVERGREEN_GRPH_FORMAT_RGB111110 6␊
4371# define EVERGREEN_GRPH_FORMAT_BGR101111 7␊
4372#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c␊
4373# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)␊
4374# define EVERGREEN_GRPH_ENDIAN_NONE 0␊
4375# define EVERGREEN_GRPH_ENDIAN_8IN16 1␊
4376# define EVERGREEN_GRPH_ENDIAN_8IN32 2␊
4377# define EVERGREEN_GRPH_ENDIAN_8IN64 3␊
4378# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)␊
4379# define EVERGREEN_GRPH_RED_SEL_R 0␊
4380# define EVERGREEN_GRPH_RED_SEL_G 1␊
4381# define EVERGREEN_GRPH_RED_SEL_B 2␊
4382# define EVERGREEN_GRPH_RED_SEL_A 3␊
4383# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)␊
4384# define EVERGREEN_GRPH_GREEN_SEL_G 0␊
4385# define EVERGREEN_GRPH_GREEN_SEL_B 1␊
4386# define EVERGREEN_GRPH_GREEN_SEL_A 2␊
4387# define EVERGREEN_GRPH_GREEN_SEL_R 3␊
4388# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)␊
4389# define EVERGREEN_GRPH_BLUE_SEL_B 0␊
4390# define EVERGREEN_GRPH_BLUE_SEL_A 1␊
4391# define EVERGREEN_GRPH_BLUE_SEL_R 2␊
4392# define EVERGREEN_GRPH_BLUE_SEL_G 3␊
4393# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)␊
4394# define EVERGREEN_GRPH_ALPHA_SEL_A 0␊
4395# define EVERGREEN_GRPH_ALPHA_SEL_R 1␊
4396# define EVERGREEN_GRPH_ALPHA_SEL_G 2␊
4397# define EVERGREEN_GRPH_ALPHA_SEL_B 3␊
4398#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810␊
4399#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814␊
4400# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0)␊
4401# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00␊
4402#define EVERGREEN_GRPH_PITCH 0x6818␊
4403#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c␊
4404#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820␊
4405#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824␊
4406#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828␊
4407#define EVERGREEN_GRPH_X_START 0x682c␊
4408#define EVERGREEN_GRPH_Y_START 0x6830␊
4409#define EVERGREEN_GRPH_X_END 0x6834␊
4410#define EVERGREEN_GRPH_Y_END 0x6838␊
4411␊
4412/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */␊
4413#define EVERGREEN_CUR_CONTROL 0x6998␊
4414# define EVERGREEN_CURSOR_EN (1 << 0)␊
4415# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)␊
4416# define EVERGREEN_CURSOR_MONO 0␊
4417# define EVERGREEN_CURSOR_24_1 1␊
4418# define EVERGREEN_CURSOR_24_8_PRE_MULT 2␊
4419# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3␊
4420# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)␊
4421# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)␊
4422# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)␊
4423# define EVERGREEN_CURSOR_URGENT_ALWAYS 0␊
4424# define EVERGREEN_CURSOR_URGENT_1_8 1␊
4425# define EVERGREEN_CURSOR_URGENT_1_4 2␊
4426# define EVERGREEN_CURSOR_URGENT_3_8 3␊
4427# define EVERGREEN_CURSOR_URGENT_1_2 4␊
4428#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c␊
4429# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000␊
4430#define EVERGREEN_CUR_SIZE 0x69a0␊
4431#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4␊
4432#define EVERGREEN_CUR_POSITION 0x69a8␊
4433#define EVERGREEN_CUR_HOT_SPOT 0x69ac␊
4434#define EVERGREEN_CUR_COLOR1 0x69b0␊
4435#define EVERGREEN_CUR_COLOR2 0x69b4␊
4436#define EVERGREEN_CUR_UPDATE 0x69b8␊
4437# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)␊
4438# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)␊
4439# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)␊
4440# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)␊
4441␊
4442/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */␊
4443#define EVERGREEN_DC_LUT_RW_MODE 0x69e0␊
4444#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4␊
4445#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8␊
4446#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec␊
4447#define EVERGREEN_DC_LUT_30_COLOR 0x69f0␊
4448#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4␊
4449#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8␊
4450#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc␊
4451#define EVERGREEN_DC_LUT_CONTROL 0x6a00␊
4452#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04␊
4453#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08␊
4454#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c␊
4455#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10␊
4456#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14␊
4457#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18␊
4458␊
4459#define EVERGREEN_DATA_FORMAT 0x6b00␊
4460# define EVERGREEN_INTERLEAVE_EN (1 << 0)␊
4461#define EVERGREEN_DESKTOP_HEIGHT 0x6b04␊
4462␊
4463#define EVERGREEN_VIEWPORT_START 0x6d70␊
4464#define EVERGREEN_VIEWPORT_SIZE 0x6d74␊
4465␊
4466/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */␊
4467#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)␊
4468#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0)␊
4469#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0)␊
4470#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0)␊
4471#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0)␊
4472#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0)␊
4473␊
4474/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */␊
4475#define EVERGREEN_CRTC_CONTROL 0x6e70␊
4476# define EVERGREEN_CRTC_MASTER_EN (1 << 0)␊
4477#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4␊
4478␊
4479#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0␊
4480#define EVERGREEN_DC_GPIO_HPD_A 0x64b4␊
4481#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8␊
4482#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc␊
4483␊
4484#define R300_GB_TILE_CONFIG␉␉␉␉0x4018␊
4485# define R300_ENABLE_TILING (1 << 0)␊
4486# define R300_PIPE_COUNT_RV350 (0 << 1)␊
4487# define R300_PIPE_COUNT_R300 (3 << 1)␊
4488# define R300_PIPE_COUNT_R420_3P (6 << 1)␊
4489# define R300_PIPE_COUNT_R420 (7 << 1)␊
4490# define R300_TILE_SIZE_8 (0 << 4)␊
4491# define R300_TILE_SIZE_16 (1 << 4)␊
4492# define R300_TILE_SIZE_32 (2 << 4)␊
4493# define R300_SUBPIXEL_1_12 (0 << 16)␊
4494# define R300_SUBPIXEL_1_16 (1 << 16)␊
4495#define R300_GB_SELECT␉␉␉␉ 0x401c␊
4496#define R300_GB_ENABLE␉␉␉␉ 0x4008␊
4497#define R300_GB_AA_CONFIG␉␉␉␉0x4020␊
4498#define R400_GB_PIPE_SELECT 0x402c␊
4499#define R300_GB_MSPOS0␉␉␉␉ 0x4010␊
4500# define R300_MS_X0_SHIFT 0␊
4501# define R300_MS_Y0_SHIFT 4␊
4502# define R300_MS_X1_SHIFT 8␊
4503# define R300_MS_Y1_SHIFT 12␊
4504# define R300_MS_X2_SHIFT 16␊
4505# define R300_MS_Y2_SHIFT 20␊
4506# define R300_MSBD0_Y_SHIFT 24␊
4507# define R300_MSBD0_X_SHIFT 28␊
4508#define R300_GB_MSPOS1␉␉␉␉ 0x4014␊
4509# define R300_MS_X3_SHIFT 0␊
4510# define R300_MS_Y3_SHIFT 4␊
4511# define R300_MS_X4_SHIFT 8␊
4512# define R300_MS_Y4_SHIFT 12␊
4513# define R300_MS_X5_SHIFT 16␊
4514# define R300_MS_Y5_SHIFT 20␊
4515# define R300_MSBD1_SHIFT 24␊
4516␊
4517#define R300_GA_ENHANCE␉␉␉␉ 0x4274␊
4518# define R300_GA_DEADLOCK_CNTL (1 << 0)␊
4519# define R300_GA_FASTSYNC_CNTL (1 << 1)␊
4520␊
4521#define R300_GA_POLY_MODE␉␉␉␉0x4288␊
4522# define R300_FRONT_PTYPE_POINT (0 << 4)␊
4523# define R300_FRONT_PTYPE_LINE (1 << 4)␊
4524# define R300_FRONT_PTYPE_TRIANGE (2 << 4)␊
4525# define R300_BACK_PTYPE_POINT (0 << 7)␊
4526# define R300_BACK_PTYPE_LINE (1 << 7)␊
4527# define R300_BACK_PTYPE_TRIANGE (2 << 7)␊
4528#define R300_GA_ROUND_MODE␉␉␉␉0x428c␊
4529# define R300_GEOMETRY_ROUND_TRUNC (0 << 0)␊
4530# define R300_GEOMETRY_ROUND_NEAREST (1 << 0)␊
4531# define R300_COLOR_ROUND_TRUNC (0 << 2)␊
4532# define R300_COLOR_ROUND_NEAREST (1 << 2)␊
4533#define R300_GA_COLOR_CONTROL␉␉␉ 0x4278␊
4534# define R300_RGB0_SHADING_SOLID (0 << 0)␊
4535# define R300_RGB0_SHADING_FLAT (1 << 0)␊
4536# define R300_RGB0_SHADING_GOURAUD (2 << 0)␊
4537# define R300_ALPHA0_SHADING_SOLID (0 << 2)␊
4538# define R300_ALPHA0_SHADING_FLAT (1 << 2)␊
4539# define R300_ALPHA0_SHADING_GOURAUD (2 << 2)␊
4540# define R300_RGB1_SHADING_SOLID (0 << 4)␊
4541# define R300_RGB1_SHADING_FLAT (1 << 4)␊
4542# define R300_RGB1_SHADING_GOURAUD (2 << 4)␊
4543# define R300_ALPHA1_SHADING_SOLID (0 << 6)␊
4544# define R300_ALPHA1_SHADING_FLAT (1 << 6)␊
4545# define R300_ALPHA1_SHADING_GOURAUD (2 << 6)␊
4546# define R300_RGB2_SHADING_SOLID (0 << 8)␊
4547# define R300_RGB2_SHADING_FLAT (1 << 8)␊
4548# define R300_RGB2_SHADING_GOURAUD (2 << 8)␊
4549# define R300_ALPHA2_SHADING_SOLID (0 << 10)␊
4550# define R300_ALPHA2_SHADING_FLAT (1 << 10)␊
4551# define R300_ALPHA2_SHADING_GOURAUD (2 << 10)␊
4552# define R300_RGB3_SHADING_SOLID (0 << 12)␊
4553# define R300_RGB3_SHADING_FLAT (1 << 12)␊
4554# define R300_RGB3_SHADING_GOURAUD (2 << 12)␊
4555# define R300_ALPHA3_SHADING_SOLID (0 << 14)␊
4556# define R300_ALPHA3_SHADING_FLAT (1 << 14)␊
4557# define R300_ALPHA3_SHADING_GOURAUD (2 << 14)␊
4558#define R300_GA_OFFSET␉␉␉␉ 0x4290␊
4559␊
4560#define R500_SU_REG_DEST 0x42c8␊
4561␊
4562#define R300_VAP_CNTL_STATUS␉␉␉␉0x2140␊
4563# define R300_PVS_BYPASS (1 << 8)␊
4564#define R300_VAP_PVS_STATE_FLUSH_REG␉␉ 0x2284␊
4565#define R300_VAP_CNTL␉␉␉␉ 0x2080␊
4566# define R300_PVS_NUM_SLOTS_SHIFT 0␊
4567# define R300_PVS_NUM_CNTLRS_SHIFT 4␊
4568# define R300_PVS_NUM_FPUS_SHIFT 8␊
4569# define R300_VF_MAX_VTX_NUM_SHIFT 18␊
4570# define R300_GL_CLIP_SPACE_DEF (0 << 22)␊
4571# define R300_DX_CLIP_SPACE_DEF (1 << 22)␊
4572# define R500_TCL_STATE_OPTIMIZATION (1 << 23)␊
4573#define R300_VAP_VTE_CNTL␉␉␉␉0x20B0␊
4574# define R300_VPORT_X_SCALE_ENA (1 << 0)␊
4575# define R300_VPORT_X_OFFSET_ENA (1 << 1)␊
4576# define R300_VPORT_Y_SCALE_ENA (1 << 2)␊
4577# define R300_VPORT_Y_OFFSET_ENA (1 << 3)␊
4578# define R300_VPORT_Z_SCALE_ENA (1 << 4)␊
4579# define R300_VPORT_Z_OFFSET_ENA (1 << 5)␊
4580# define R300_VTX_XY_FMT (1 << 8)␊
4581# define R300_VTX_Z_FMT (1 << 9)␊
4582# define R300_VTX_W0_FMT (1 << 10)␊
4583#define R300_VAP_VTX_STATE_CNTL␉␉ 0x2180␊
4584#define R300_VAP_PSC_SGN_NORM_CNTL␉␉ 0x21DC␊
4585#define R300_VAP_PROG_STREAM_CNTL_0␉␉ 0x2150␊
4586# define R300_DATA_TYPE_0_SHIFT 0␊
4587# define R300_DATA_TYPE_FLOAT_1 0␊
4588# define R300_DATA_TYPE_FLOAT_2 1␊
4589# define R300_DATA_TYPE_FLOAT_3 2␊
4590# define R300_DATA_TYPE_FLOAT_4 3␊
4591# define R300_DATA_TYPE_BYTE 4␊
4592# define R300_DATA_TYPE_D3DCOLOR 5␊
4593# define R300_DATA_TYPE_SHORT_2 6␊
4594# define R300_DATA_TYPE_SHORT_4 7␊
4595# define R300_DATA_TYPE_VECTOR_3_TTT 8␊
4596# define R300_DATA_TYPE_VECTOR_3_EET 9␊
4597# define R300_SKIP_DWORDS_0_SHIFT 4␊
4598# define R300_DST_VEC_LOC_0_SHIFT 8␊
4599# define R300_LAST_VEC_0 (1 << 13)␊
4600# define R300_SIGNED_0 (1 << 14)␊
4601# define R300_NORMALIZE_0 (1 << 15)␊
4602# define R300_DATA_TYPE_1_SHIFT 16␊
4603# define R300_SKIP_DWORDS_1_SHIFT 20␊
4604# define R300_DST_VEC_LOC_1_SHIFT 24␊
4605# define R300_LAST_VEC_1 (1 << 29)␊
4606# define R300_SIGNED_1 (1 << 30)␊
4607# define R300_NORMALIZE_1 (1 << 31)␊
4608#define R300_VAP_PROG_STREAM_CNTL_1␉␉ 0x2154␊
4609# define R300_DATA_TYPE_2_SHIFT 0␊
4610# define R300_SKIP_DWORDS_2_SHIFT 4␊
4611# define R300_DST_VEC_LOC_2_SHIFT 8␊
4612# define R300_LAST_VEC_2 (1 << 13)␊
4613# define R300_SIGNED_2 (1 << 14)␊
4614# define R300_NORMALIZE_2 (1 << 15)␊
4615# define R300_DATA_TYPE_3_SHIFT 16␊
4616# define R300_SKIP_DWORDS_3_SHIFT 20␊
4617# define R300_DST_VEC_LOC_3_SHIFT 24␊
4618# define R300_LAST_VEC_3 (1 << 29)␊
4619# define R300_SIGNED_3 (1 << 30)␊
4620# define R300_NORMALIZE_3 (1 << 31)␊
4621#define R300_VAP_PROG_STREAM_CNTL_EXT_0␉ 0x21e0␊
4622# define R300_SWIZZLE_SELECT_X_0_SHIFT 0␊
4623# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3␊
4624# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6␊
4625# define R300_SWIZZLE_SELECT_W_0_SHIFT 9␊
4626# define R300_SWIZZLE_SELECT_X 0␊
4627# define R300_SWIZZLE_SELECT_Y 1␊
4628# define R300_SWIZZLE_SELECT_Z 2␊
4629# define R300_SWIZZLE_SELECT_W 3␊
4630# define R300_SWIZZLE_SELECT_FP_ZERO 4␊
4631# define R300_SWIZZLE_SELECT_FP_ONE 5␊
4632# define R300_WRITE_ENA_0_SHIFT 12␊
4633# define R300_WRITE_ENA_X 1␊
4634# define R300_WRITE_ENA_Y 2␊
4635# define R300_WRITE_ENA_Z 4␊
4636# define R300_WRITE_ENA_W 8␊
4637# define R300_SWIZZLE_SELECT_X_1_SHIFT 16␊
4638# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19␊
4639# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22␊
4640# define R300_SWIZZLE_SELECT_W_1_SHIFT 25␊
4641# define R300_WRITE_ENA_1_SHIFT 28␊
4642#define R300_VAP_PROG_STREAM_CNTL_EXT_1␉ 0x21e4␊
4643# define R300_SWIZZLE_SELECT_X_2_SHIFT 0␊
4644# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3␊
4645# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6␊
4646# define R300_SWIZZLE_SELECT_W_2_SHIFT 9␊
4647# define R300_WRITE_ENA_2_SHIFT 12␊
4648# define R300_SWIZZLE_SELECT_X_3_SHIFT 16␊
4649# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19␊
4650# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22␊
4651# define R300_SWIZZLE_SELECT_W_3_SHIFT 25␊
4652# define R300_WRITE_ENA_3_SHIFT 28␊
4653#define R300_VAP_PVS_CODE_CNTL_0␉␉␉0x22D0␊
4654# define R300_PVS_FIRST_INST_SHIFT 0␊
4655# define R300_PVS_XYZW_VALID_INST_SHIFT 10␊
4656# define R300_PVS_LAST_INST_SHIFT 20␊
4657#define R300_VAP_PVS_CODE_CNTL_1␉␉␉0x22D8␊
4658# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0␊
4659#define R300_VAP_PVS_VECTOR_INDX_REG␉␉ 0x2200␊
4660# define R300_PVS_CODE_START 0␊
4661# define R300_PVS_CONST_START 512␊
4662# define R500_PVS_CONST_START 1024␊
4663# define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START)␊
4664# define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START)␊
4665# define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START)␊
4666#define R300_VAP_PVS_VECTOR_DATA_REG␉␉ 0x2204␊
4667/* PVS instructions */␊
4668/* Opcode and dst instruction */␊
4669#define R300_PVS_DST_OPCODE(x) ((x) << 0)␊
4670/* Vector ops */␊
4671# define R300_VECTOR_NO_OP 0␊
4672# define R300_VE_DOT_PRODUCT 1␊
4673# define R300_VE_MULTIPLY 2␊
4674# define R300_VE_ADD 3␊
4675# define R300_VE_MULTIPLY_ADD 4␊
4676# define R300_VE_DISTANCE_VECTOR 5␊
4677# define R300_VE_FRACTION 6␊
4678# define R300_VE_MAXIMUM 7␊
4679# define R300_VE_MINIMUM 8␊
4680# define R300_VE_SET_GREATER_THAN_EQUAL 9␊
4681# define R300_VE_SET_LESS_THAN 10␊
4682# define R300_VE_MULTIPLYX2_ADD 11␊
4683# define R300_VE_MULTIPLY_CLAMP 12␊
4684# define R300_VE_FLT2FIX_DX 13␊
4685# define R300_VE_FLT2FIX_DX_RND 14␊
4686/* R500 additions */␊
4687# define R500_VE_PRED_SET_EQ_PUSH 15␊
4688# define R500_VE_PRED_SET_GT_PUSH 16␊
4689# define R500_VE_PRED_SET_GTE_PUSH 17␊
4690# define R500_VE_PRED_SET_NEQ_PUSH 18␊
4691# define R500_VE_COND_WRITE_EQ 19␊
4692# define R500_VE_COND_WRITE_GT 20␊
4693# define R500_VE_COND_WRITE_GTE 21␊
4694# define R500_VE_COND_WRITE_NEQ 22␊
4695# define R500_VE_COND_MUX_EQ 23␊
4696# define R500_VE_COND_MUX_GT 24␊
4697# define R500_VE_COND_MUX_GTE 25␊
4698# define R500_VE_SET_GREATER_THAN 26␊
4699# define R500_VE_SET_EQUAL 27␊
4700# define R500_VE_SET_NOT_EQUAL 28␊
4701/* Math ops */␊
4702# define R300_MATH_NO_OP 0␊
4703# define R300_ME_EXP_BASE2_DX 1␊
4704# define R300_ME_LOG_BASE2_DX 2␊
4705# define R300_ME_EXP_BASEE_FF 3␊
4706# define R300_ME_LIGHT_COEFF_DX 4␊
4707# define R300_ME_POWER_FUNC_FF 5␊
4708# define R300_ME_RECIP_DX 6␊
4709# define R300_ME_RECIP_FF 7␊
4710# define R300_ME_RECIP_SQRT_DX 8␊
4711# define R300_ME_RECIP_SQRT_FF 9␊
4712# define R300_ME_MULTIPLY 10␊
4713# define R300_ME_EXP_BASE2_FULL_DX 11␊
4714# define R300_ME_LOG_BASE2_FULL_DX 12␊
4715# define R300_ME_POWER_FUNC_FF_CLAMP_B 13␊
4716# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14␊
4717# define R300_ME_POWER_FUNC_FF_CLAMP_01 15␊
4718# define R300_ME_SIN 16␊
4719# define R300_ME_COS 17␊
4720/* R500 additions */␊
4721# define R500_ME_LOG_BASE2_IEEE 18␊
4722# define R500_ME_RECIP_IEEE 19␊
4723# define R500_ME_RECIP_SQRT_IEEE 20␊
4724# define R500_ME_PRED_SET_EQ 21␊
4725# define R500_ME_PRED_SET_GT 22␊
4726# define R500_ME_PRED_SET_GTE 23␊
4727# define R500_ME_PRED_SET_NEQ 24␊
4728# define R500_ME_PRED_SET_CLR 25␊
4729# define R500_ME_PRED_SET_INV 26␊
4730# define R500_ME_PRED_SET_POP 27␊
4731# define R500_ME_PRED_SET_RESTORE 28␊
4732/* macro */␊
4733# define R300_PVS_MACRO_OP_2CLK_MADD 0␊
4734# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1␊
4735#define R300_PVS_DST_MATH_INST (1 << 6)␊
4736#define R300_PVS_DST_MACRO_INST (1 << 7)␊
4737#define R300_PVS_DST_REG_TYPE(x) ((x) << 8)␊
4738# define R300_PVS_DST_REG_TEMPORARY 0␊
4739# define R300_PVS_DST_REG_A0 1␊
4740# define R300_PVS_DST_REG_OUT 2␊
4741# define R500_PVS_DST_REG_OUT_REPL_X 3␊
4742# define R300_PVS_DST_REG_ALT_TEMPORARY 4␊
4743# define R300_PVS_DST_REG_INPUT 5␊
4744#define R300_PVS_DST_ADDR_MODE_1 (1 << 12)␊
4745#define R300_PVS_DST_OFFSET(x) ((x) << 13)␊
4746#define R300_PVS_DST_WE_X (1 << 20)␊
4747#define R300_PVS_DST_WE_Y (1 << 21)␊
4748#define R300_PVS_DST_WE_Z (1 << 22)␊
4749#define R300_PVS_DST_WE_W (1 << 23)␊
4750#define R300_PVS_DST_VE_SAT (1 << 24)␊
4751#define R300_PVS_DST_ME_SAT (1 << 25)␊
4752#define R300_PVS_DST_PRED_ENABLE (1 << 26)␊
4753#define R300_PVS_DST_PRED_SENSE (1 << 27)␊
4754#define R300_PVS_DST_DUAL_MATH_OP (1 << 28)␊
4755#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29)␊
4756#define R300_PVS_DST_ADDR_MODE_0 (1 << 31)␊
4757/* src operand instruction */␊
4758#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0)␊
4759# define R300_PVS_SRC_REG_TEMPORARY 0␊
4760# define R300_PVS_SRC_REG_INPUT 1␊
4761# define R300_PVS_SRC_REG_CONSTANT 2␊
4762# define R300_PVS_SRC_REG_ALT_TEMPORARY 3␊
4763#define R300_SPARE_0 (1 << 2)␊
4764#define R300_PVS_SRC_ABS_XYZW (1 << 3)␊
4765#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)␊
4766#define R300_PVS_SRC_OFFSET(x) ((x) << 5)␊
4767#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13)␊
4768#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16)␊
4769#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19)␊
4770#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22)␊
4771# define R300_PVS_SRC_SELECT_X 0␊
4772# define R300_PVS_SRC_SELECT_Y 1␊
4773# define R300_PVS_SRC_SELECT_Z 2␊
4774# define R300_PVS_SRC_SELECT_W 3␊
4775# define R300_PVS_SRC_SELECT_FORCE_0 4␊
4776# define R300_PVS_SRC_SELECT_FORCE_1 5␊
4777#define R300_PVS_SRC_NEG_X (1 << 25)␊
4778#define R300_PVS_SRC_NEG_Y (1 << 26)␊
4779#define R300_PVS_SRC_NEG_Z (1 << 27)␊
4780#define R300_PVS_SRC_NEG_W (1 << 28)␊
4781#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29)␊
4782#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)␊
4783␊
4784#define R300_VAP_PVS_CONST_CNTL 0x22d4␊
4785# define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0)␊
4786# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16)␊
4787␊
4788#define R300_VAP_PVS_FLOW_CNTL_OPC␉␉ 0x22dc␊
4789#define R300_VAP_OUT_VTX_FMT_0␉␉␉ 0x2090␊
4790# define R300_VTX_POS_PRESENT (1 << 0)␊
4791# define R300_VTX_COLOR_0_PRESENT (1 << 1)␊
4792# define R300_VTX_COLOR_1_PRESENT (1 << 2)␊
4793# define R300_VTX_COLOR_2_PRESENT (1 << 3)␊
4794# define R300_VTX_COLOR_3_PRESENT (1 << 4)␊
4795# define R300_VTX_PT_SIZE_PRESENT (1 << 16)␊
4796#define R300_VAP_OUT_VTX_FMT_1␉␉␉ 0x2094␊
4797# define R300_TEX_0_COMP_CNT_SHIFT 0␊
4798# define R300_TEX_1_COMP_CNT_SHIFT 3␊
4799# define R300_TEX_2_COMP_CNT_SHIFT 6␊
4800# define R300_TEX_3_COMP_CNT_SHIFT 9␊
4801# define R300_TEX_4_COMP_CNT_SHIFT 12␊
4802# define R300_TEX_5_COMP_CNT_SHIFT 15␊
4803# define R300_TEX_6_COMP_CNT_SHIFT 18␊
4804# define R300_TEX_7_COMP_CNT_SHIFT 21␊
4805#define R300_VAP_VTX_SIZE␉␉␉␉0x20b4␊
4806#define R300_VAP_GB_VERT_CLIP_ADJ␉␉ 0x2220␊
4807#define R300_VAP_GB_VERT_DISC_ADJ␉␉ 0x2224␊
4808#define R300_VAP_GB_HORZ_CLIP_ADJ␉␉ 0x2228␊
4809#define R300_VAP_GB_HORZ_DISC_ADJ␉␉ 0x222c␊
4810#define R300_VAP_CLIP_CNTL␉␉␉␉0x221c␊
4811# define R300_UCP_ENA_0 (1 << 0)␊
4812# define R300_UCP_ENA_1 (1 << 1)␊
4813# define R300_UCP_ENA_2 (1 << 2)␊
4814# define R300_UCP_ENA_3 (1 << 3)␊
4815# define R300_UCP_ENA_4 (1 << 4)␊
4816# define R300_UCP_ENA_5 (1 << 5)␊
4817# define R300_PS_UCP_MODE_SHIFT 14␊
4818# define R300_CLIP_DISABLE (1 << 16)␊
4819# define R300_UCP_CULL_ONLY_ENA (1 << 17)␊
4820# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)␊
4821#define R300_VAP_PVS_STATE_FLUSH_REG␉␉␉0x2284␊
4822␊
4823#define R500_VAP_INDEX_OFFSET␉␉␉ 0x208c␊
4824␊
4825#define R300_SU_TEX_WRAP␉␉␉␉0x42a0␊
4826#define R300_SU_POLY_OFFSET_ENABLE␉␉ 0x42b4␊
4827#define R300_SU_CULL_MODE␉␉␉␉0x42b8␊
4828# define R300_CULL_FRONT (1 << 0)␊
4829# define R300_CULL_BACK (1 << 1)␊
4830# define R300_FACE_POS (0 << 2)␊
4831# define R300_FACE_NEG (1 << 2)␊
4832#define R300_SU_DEPTH_SCALE␉␉␉␉0x42c0␊
4833#define R300_SU_DEPTH_OFFSET␉␉␉ 0x42c4␊
4834␊
4835#define R300_RS_COUNT␉␉␉␉ 0x4300␊
4836#␉define R300_RS_COUNT_IT_COUNT_SHIFT␉␉0␊
4837#␉define R300_RS_COUNT_IC_COUNT_SHIFT␉␉7␊
4838#␉define R300_RS_COUNT_HIRES_EN␉␉␉(1 << 18)␊
4839␊
4840#define R300_RS_IP_0␉␉␉␉ 0x4310␊
4841#define R300_RS_IP_1␉␉␉␉ 0x4314␊
4842#␉define R300_RS_TEX_PTR(x)␉␉ ((x) << 0)␊
4843#␉define R300_RS_COL_PTR(x)␉␉ ((x) << 6)␊
4844#␉define R300_RS_COL_FMT(x)␉␉ ((x) << 9)␊
4845#␉define R300_RS_COL_FMT_RGBA␉␉ 0␊
4846#␉define R300_RS_COL_FMT_RGB0␉␉ 2␊
4847#␉define R300_RS_COL_FMT_RGB1␉␉ 3␊
4848#␉define R300_RS_COL_FMT_000A␉␉ 4␊
4849#␉define R300_RS_COL_FMT_0000␉␉ 5␊
4850#␉define R300_RS_COL_FMT_0001␉␉ 6␊
4851#␉define R300_RS_COL_FMT_111A␉␉ 8␊
4852#␉define R300_RS_COL_FMT_1110␉␉ 9␊
4853#␉define R300_RS_COL_FMT_1111␉␉ 10␊
4854#␉define R300_RS_SEL_S(x)␉␉ ((x) << 13)␊
4855#␉define R300_RS_SEL_T(x)␉␉ ((x) << 16)␊
4856#␉define R300_RS_SEL_R(x)␉␉ ((x) << 19)␊
4857#␉define R300_RS_SEL_Q(x)␉␉ ((x) << 22)␊
4858#␉define R300_RS_SEL_C0␉␉ 0␊
4859#␉define R300_RS_SEL_C1␉␉ 1␊
4860#␉define R300_RS_SEL_C2␉␉ 2␊
4861#␉define R300_RS_SEL_C3␉␉ 3␊
4862#␉define R300_RS_SEL_K0␉␉ 4␊
4863#␉define R300_RS_SEL_K1␉␉ 5␊
4864#define R300_RS_INST_COUNT␉␉␉␉0x4304␊
4865#␉define R300_INST_COUNT_RS(x)␉␉ ((x) << 0)␊
4866#␉define R300_RS_W_EN␉␉␉ (1 << 4)␊
4867#␉define R300_TX_OFFSET_RS(x)␉␉ ((x) << 5)␊
4868#define R300_RS_INST_0␉␉␉␉ 0x4330␊
4869#define R300_RS_INST_1␉␉␉␉ 0x4334␊
4870#␉define R300_INST_TEX_ID(x)␉␉ ((x) << 0)␊
4871# define R300_RS_INST_TEX_CN_WRITE␉␉(1 << 3)␊
4872#␉define R300_INST_TEX_ADDR(x)␉␉ ((x) << 6)␊
4873␊
4874#define R300_TX_INVALTAGS␉␉␉␉0x4100␊
4875#define R300_TX_FILTER0_0␉␉␉␉0x4400␊
4876#define R300_TX_FILTER0_1␉␉␉␉0x4404␊
4877#define R300_TX_FILTER0_2␉␉␉␉0x4408␊
4878# define R300_TX_CLAMP_S(x) ((x) << 0)␊
4879# define R300_TX_CLAMP_T(x) ((x) << 3)␊
4880# define R300_TX_CLAMP_R(x) ((x) << 6)␊
4881# define R300_TX_CLAMP_WRAP 0␊
4882# define R300_TX_CLAMP_MIRROR 1␊
4883# define R300_TX_CLAMP_CLAMP_LAST 2␊
4884# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3␊
4885# define R300_TX_CLAMP_CLAMP_BORDER 4␊
4886# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5␊
4887# define R300_TX_CLAMP_CLAMP_GL 6␊
4888# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7␊
4889# define R300_TX_MAG_FILTER_NEAREST (1 << 9)␊
4890# define R300_TX_MIN_FILTER_NEAREST (1 << 11)␊
4891# define R300_TX_MAG_FILTER_LINEAR (2 << 9)␊
4892# define R300_TX_MIN_FILTER_LINEAR (2 << 11)␊
4893# define R300_TX_ID_SHIFT 28␊
4894#define R300_TX_FILTER1_0␉␉␉␉0x4440␊
4895#define R300_TX_FILTER1_1␉␉␉␉0x4444␊
4896#define R300_TX_FILTER1_2␉␉␉␉0x4448␊
4897#define R300_TX_FORMAT0_0␉␉␉␉0x4480␊
4898#define R300_TX_FORMAT0_1␉␉␉␉0x4484␊
4899#define R300_TX_FORMAT0_2␉␉␉␉0x4488␊
4900# define R300_TXWIDTH_SHIFT 0␊
4901# define R300_TXHEIGHT_SHIFT 11␊
4902# define R300_NUM_LEVELS_SHIFT 26␊
4903# define R300_NUM_LEVELS_MASK 0x␊
4904# define R300_TXPROJECTED (1 << 30)␊
4905# define R300_TXPITCH_EN (1 << 31)␊
4906#define R300_TX_FORMAT1_0␉␉␉␉0x44c0␊
4907#define R300_TX_FORMAT1_1␉␉␉␉0x44c4␊
4908#define R300_TX_FORMAT1_2␉␉␉␉0x44c8␊
4909#␉define R300_TX_FORMAT_X8␉␉ 0x0␊
4910#␉define R300_TX_FORMAT_X16␉␉ 0x1␊
4911#␉define R300_TX_FORMAT_Y4X4␉␉ 0x2␊
4912#␉define R300_TX_FORMAT_Y8X8␉␉ 0x3␊
4913#␉define R300_TX_FORMAT_Y16X16␉␉ 0x4␊
4914#␉define R300_TX_FORMAT_Z3Y3X2␉␉ 0x5␊
4915#␉define R300_TX_FORMAT_Z5Y6X5␉␉ 0x6␊
4916#␉define R300_TX_FORMAT_Z6Y5X5␉␉ 0x7␊
4917#␉define R300_TX_FORMAT_Z11Y11X10␉␉ 0x8␊
4918#␉define R300_TX_FORMAT_Z10Y11X11␉␉ 0x9␊
4919#␉define R300_TX_FORMAT_W4Z4Y4X4␉␉ 0xA␊
4920#␉define R300_TX_FORMAT_W1Z5Y5X5␉␉ 0xB␊
4921#␉define R300_TX_FORMAT_W8Z8Y8X8␉␉ 0xC␊
4922#␉define R300_TX_FORMAT_W2Z10Y10X10␉ 0xD␊
4923#␉define R300_TX_FORMAT_W16Z16Y16X16␉ 0xE␊
4924#␉define R300_TX_FORMAT_DXT1␉ ␉ 0xF␊
4925#␉define R300_TX_FORMAT_DXT3␉ ␉ 0x10␊
4926#␉define R300_TX_FORMAT_DXT5␉ ␉ 0x11␊
4927#␉define R300_TX_FORMAT_D3DMFT_CxV8U8␉ 0x12 /* no swizzle */␊
4928#␉define R300_TX_FORMAT_A8R8G8B8␉ ␉ 0x13 /* no swizzle */␊
4929#␉define R300_TX_FORMAT_B8G8_B8G8␉ ␉ 0x14 /* no swizzle */␊
4930#␉define R300_TX_FORMAT_G8R8_G8B8␉ ␉ 0x15 /* no swizzle */␊
4931#␉define R300_TX_FORMAT_VYUY422␉ ␉ 0x14 /* no swizzle */␊
4932#␉define R300_TX_FORMAT_YVYU422␉ ␉ 0x15 /* no swizzle */␊
4933#␉define R300_TX_FORMAT_X24_Y8␉ ␉ 0x1e␊
4934#␉define R300_TX_FORMAT_X32␉ ␉ 0x1e␊
4935␉/* Floating point formats */␊
4936␉/* Note - hardware supports both 16 and 32 bit floating point */␊
4937#␉define R300_TX_FORMAT_FL_I16␉ ␉ 0x18␊
4938#␉define R300_TX_FORMAT_FL_I16A16␉ ␉ 0x19␊
4939#␉define R300_TX_FORMAT_FL_R16G16B16A16␉ 0x1A␊
4940#␉define R300_TX_FORMAT_FL_I32␉ ␉ 0x1B␊
4941#␉define R300_TX_FORMAT_FL_I32A32␉ ␉ 0x1C␊
4942#␉define R300_TX_FORMAT_FL_R32G32B32A32␉ 0x1D␊
4943␉/* alpha modes, convenience mostly */␊
4944␉/* if you have alpha, pick constant appropriate to the␊
4945␉ number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */␊
4946# ␉define R300_TX_FORMAT_ALPHA_1CH␉␉ 0x000␊
4947# ␉define R300_TX_FORMAT_ALPHA_2CH␉␉ 0x200␊
4948# ␉define R300_TX_FORMAT_ALPHA_4CH␉␉ 0x600␊
4949# ␉define R300_TX_FORMAT_ALPHA_NONE␉ 0xA00␊
4950␉/* Swizzling */␊
4951␉/* constants */␊
4952#␉define R300_TX_FORMAT_X␉␉0␊
4953#␉define R300_TX_FORMAT_Y␉␉1␊
4954#␉define R300_TX_FORMAT_Z␉␉2␊
4955#␉define R300_TX_FORMAT_W␉␉3␊
4956#␉define R300_TX_FORMAT_ZERO␉4␊
4957#␉define R300_TX_FORMAT_ONE␉5␊
4958␉/* 2.0*Z, everything above 1.0 is set to 0.0 */␊
4959#␉define R300_TX_FORMAT_CUT_Z␉6␊
4960␉/* 2.0*W, everything above 1.0 is set to 0.0 */␊
4961#␉define R300_TX_FORMAT_CUT_W␉7␊
4962␊
4963#␉define R300_TX_FORMAT_B_SHIFT␉18␊
4964#␉define R300_TX_FORMAT_G_SHIFT␉15␊
4965#␉define R300_TX_FORMAT_R_SHIFT␉12␊
4966#␉define R300_TX_FORMAT_A_SHIFT␉9␊
4967␊
4968␉/* Convenience macro to take care of layout and swizzling */␊
4969#␉define R300_EASY_TX_FORMAT(B, G, R, A, FMT)␉(␉␉\␊
4970␉␉((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT)␉␉\␊
4971␉␉| ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT)␉\␊
4972␉␉| ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT)␉\␊
4973␉␉| ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT)␉\␊
4974␉␉| (R300_TX_FORMAT_##FMT)␉␉␉␉\␊
4975␉␉)␊
4976␊
4977# define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22)␊
4978# define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)␊
4979# define R300_TX_FORMAT_SWAP_YUV (1 << 24)␊
4980␊
4981# define R300_TX_FORMAT_CACHE_WHOLE (0 << 27)␊
4982# define R300_TX_FORMAT_CACHE_HALF_REGION_0 (2 << 27)␊
4983# define R300_TX_FORMAT_CACHE_HALF_REGION_1 (3 << 27)␊
4984# define R300_TX_FORMAT_CACHE_FOURTH_REGION_0 (4 << 27)␊
4985# define R300_TX_FORMAT_CACHE_FOURTH_REGION_1 (5 << 27)␊
4986# define R300_TX_FORMAT_CACHE_FOURTH_REGION_2 (6 << 27)␊
4987# define R300_TX_FORMAT_CACHE_FOURTH_REGION_3 (7 << 27)␊
4988␊
4989#define R300_TX_FORMAT2_0␉␉␉␉0x4500␊
4990#define R300_TX_FORMAT2_1␉␉␉␉0x4504␊
4991#define R300_TX_FORMAT2_2␉␉␉␉0x4508␊
4992# define R500_TXWIDTH_11 (1 << 15)␊
4993# define R500_TXHEIGHT_11 (1 << 16)␊
4994␊
4995#define R300_TX_OFFSET_0␉␉␉␉0x4540␊
4996#define R300_TX_OFFSET_1␉␉␉␉0x4544␊
4997#define R300_TX_OFFSET_2␉␉␉␉0x4548␊
4998# define R300_ENDIAN_SWAP_16_BIT (1 << 0)␊
4999# define R300_ENDIAN_SWAP_32_BIT (2 << 0)␊
5000# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)␊
5001# define R300_MACRO_TILE (1 << 2)␊
5002␊
5003#define R300_TX_BORDER_COLOR_0␉␉␉ 0x45c0␊
5004␊
5005#define R300_TX_ENABLE␉␉␉␉ 0x4104␊
5006# define R300_TEX_0_ENABLE (1 << 0)␊
5007# define R300_TEX_1_ENABLE (1 << 1)␊
5008# define R300_TEX_2_ENABLE (1 << 2)␊
5009␊
5010#define R300_US_W_FMT␉␉␉␉ 0x46b4␊
5011#define R300_US_OUT_FMT_1␉␉␉␉0x46a8␊
5012#define R300_US_OUT_FMT_2␉␉␉␉0x46ac␊
5013#define R300_US_OUT_FMT_3␉␉␉␉0x46b0␊
5014#define R300_US_OUT_FMT_0␉␉␉␉0x46a4␊
5015# define R300_OUT_FMT_C4_8 (0 << 0)␊
5016# define R300_OUT_FMT_C4_10 (1 << 0)␊
5017# define R300_OUT_FMT_C4_10_GAMMA (2 << 0)␊
5018# define R300_OUT_FMT_C_16 (3 << 0)␊
5019# define R300_OUT_FMT_C2_16 (4 << 0)␊
5020# define R300_OUT_FMT_C4_16 (5 << 0)␊
5021# define R300_OUT_FMT_C_16_MPEG (6 << 0)␊
5022# define R300_OUT_FMT_C2_16_MPEG (7 << 0)␊
5023# define R300_OUT_FMT_C2_4 (8 << 0)␊
5024# define R300_OUT_FMT_C_3_3_2 (9 << 0)␊
5025# define R300_OUT_FMT_C_5_6_5 (10 << 0)␊
5026# define R300_OUT_FMT_C_11_11_10 (11 << 0)␊
5027# define R300_OUT_FMT_C_10_11_11 (12 << 0)␊
5028# define R300_OUT_FMT_C_2_10_10_10 (13 << 0)␊
5029# define R300_OUT_FMT_UNUSED (15 << 0)␊
5030# define R300_OUT_FMT_C_16_FP (16 << 0)␊
5031# define R300_OUT_FMT_C2_16_FP (17 << 0)␊
5032# define R300_OUT_FMT_C4_16_FP (18 << 0)␊
5033# define R300_OUT_FMT_C_32_FP (19 << 0)␊
5034# define R300_OUT_FMT_C2_32_FP (20 << 0)␊
5035# define R300_OUT_FMT_C4_32_FP (21 << 0)␊
5036# define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8)␊
5037# define R300_OUT_FMT_C0_SEL_RED (1 << 8)␊
5038# define R300_OUT_FMT_C0_SEL_GREEN (2 << 8)␊
5039# define R300_OUT_FMT_C0_SEL_BLUE (3 << 8)␊
5040# define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10)␊
5041# define R300_OUT_FMT_C1_SEL_RED (1 << 10)␊
5042# define R300_OUT_FMT_C1_SEL_GREEN (2 << 10)␊
5043# define R300_OUT_FMT_C1_SEL_BLUE (3 << 10)␊
5044# define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12)␊
5045# define R300_OUT_FMT_C2_SEL_RED (1 << 12)␊
5046# define R300_OUT_FMT_C2_SEL_GREEN (2 << 12)␊
5047# define R300_OUT_FMT_C2_SEL_BLUE (3 << 12)␊
5048# define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14)␊
5049# define R300_OUT_FMT_C3_SEL_RED (1 << 14)␊
5050# define R300_OUT_FMT_C3_SEL_GREEN (2 << 14)␊
5051# define R300_OUT_FMT_C3_SEL_BLUE (3 << 14)␊
5052#define R300_US_CONFIG␉␉␉␉ 0x4600␊
5053# define R300_NLEVEL_SHIFT 0␊
5054# define R300_FIRST_TEX (1 << 3)␊
5055# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)␊
5056#define R300_US_PIXSIZE␉␉␉␉ 0x4604␊
5057#define R300_US_CODE_OFFSET␉␉␉␉0x4608␊
5058# define R300_ALU_CODE_OFFSET(x) ((x) << 0)␊
5059# define R300_ALU_CODE_SIZE(x) ((x) << 6)␊
5060# define R300_TEX_CODE_OFFSET(x) ((x) << 13)␊
5061# define R300_TEX_CODE_SIZE(x) ((x) << 18)␊
5062#define R300_US_CODE_ADDR_0␉␉␉␉0x4610␊
5063# define R300_ALU_START(x) ((x) << 0)␊
5064# define R300_ALU_SIZE(x) ((x) << 6)␊
5065# define R300_TEX_START(x) ((x) << 12)␊
5066# define R300_TEX_SIZE(x) ((x) << 17)␊
5067# define R300_RGBA_OUT (1 << 22)␊
5068# define R300_W_OUT (1 << 23)␊
5069#define R300_US_CODE_ADDR_1␉␉␉␉0x4614␊
5070#define R300_US_CODE_ADDR_2␉␉␉␉0x4618␊
5071#define R300_US_CODE_ADDR_3␉␉␉␉0x461c␊
5072#define R300_US_TEX_INST_0␉␉␉␉0x4620␊
5073#define R300_US_TEX_INST_1␉␉␉␉0x4624␊
5074#define R300_US_TEX_INST_2␉␉␉␉0x4628␊
5075#define R300_US_TEX_INST(x)␉␉␉ (R300_US_TEX_INST_0 + (x)*4)␊
5076# define R300_TEX_SRC_ADDR(x) ((x) << 0)␊
5077# define R300_TEX_DST_ADDR(x) ((x) << 6)␊
5078# define R300_TEX_ID(x) ((x) << 11)␊
5079# define R300_TEX_INST(x) ((x) << 15)␊
5080# define R300_TEX_INST_NOP 0␊
5081# define R300_TEX_INST_LD 1␊
5082# define R300_TEX_INST_TEXKILL 2␊
5083# define R300_TEX_INST_PROJ 3␊
5084# define R300_TEX_INST_LODBIAS 4␊
5085#define R300_US_ALU_RGB_ADDR_0␉␉␉ 0x46c0␊
5086#define R300_US_ALU_RGB_ADDR_1␉␉␉ 0x46c4␊
5087#define R300_US_ALU_RGB_ADDR_2␉␉␉ 0x46c8␊
5088#define R300_US_ALU_RGB_ADDR(x)␉␉␉ (R300_US_ALU_RGB_ADDR_0 + (x)*4)␊
5089/* for ADDR0-2, values 0-31 specify a location in the pixel stack,␊
5090 values 32-63 specify a constant */␊
5091# define R300_ALU_RGB_ADDR0(x) ((x) << 0)␊
5092# define R300_ALU_RGB_ADDR1(x) ((x) << 6)␊
5093# define R300_ALU_RGB_ADDR2(x) ((x) << 12)␊
5094# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5))␊
5095/* ADDRD - where on the pixel stack the result of this instruction␊
5096 will be written */␊
5097# define R300_ALU_RGB_ADDRD(x) ((x) << 18)␊
5098# define R300_ALU_RGB_WMASK(x) ((x) << 23)␊
5099# define R300_ALU_RGB_OMASK(x) ((x) << 26)␊
5100# define R300_ALU_RGB_MASK_NONE 0␊
5101# define R300_ALU_RGB_MASK_R 1␊
5102# define R300_ALU_RGB_MASK_G 2␊
5103# define R300_ALU_RGB_MASK_B 4␊
5104# define R300_ALU_RGB_MASK_RGB 7␊
5105# define R300_ALU_RGB_TARGET_A (0 << 29)␊
5106# define R300_ALU_RGB_TARGET_B (1 << 29)␊
5107# define R300_ALU_RGB_TARGET_C (2 << 29)␊
5108# define R300_ALU_RGB_TARGET_D (3 << 29)␊
5109#define R300_US_ALU_RGB_INST_0␉␉␉ 0x48c0␊
5110#define R300_US_ALU_RGB_INST_1␉␉␉ 0x48c4␊
5111#define R300_US_ALU_RGB_INST_2␉␉␉ 0x48c8␊
5112#define R300_US_ALU_RGB_INST(x)␉␉␉ (R300_US_ALU_RGB_INST_0 + (x)*4)␊
5113# define R300_ALU_RGB_SEL_A(x) ((x) << 0)␊
5114# define R300_ALU_RGB_SRC0_RGB 0␊
5115# define R300_ALU_RGB_SRC0_RRR 1␊
5116# define R300_ALU_RGB_SRC0_GGG 2␊
5117# define R300_ALU_RGB_SRC0_BBB 3␊
5118# define R300_ALU_RGB_SRC1_RGB 4␊
5119# define R300_ALU_RGB_SRC1_RRR 5␊
5120# define R300_ALU_RGB_SRC1_GGG 6␊
5121# define R300_ALU_RGB_SRC1_BBB 7␊
5122# define R300_ALU_RGB_SRC2_RGB 8␊
5123# define R300_ALU_RGB_SRC2_RRR 9␊
5124# define R300_ALU_RGB_SRC2_GGG 10␊
5125# define R300_ALU_RGB_SRC2_BBB 11␊
5126# define R300_ALU_RGB_SRC0_AAA 12␊
5127# define R300_ALU_RGB_SRC1_AAA 13␊
5128# define R300_ALU_RGB_SRC2_AAA 14␊
5129# define R300_ALU_RGB_SRCP_RGB 15␊
5130# define R300_ALU_RGB_SRCP_RRR 16␊
5131# define R300_ALU_RGB_SRCP_GGG 17␊
5132# define R300_ALU_RGB_SRCP_BBB 18␊
5133# define R300_ALU_RGB_SRCP_AAA 19␊
5134# define R300_ALU_RGB_0_0 20␊
5135# define R300_ALU_RGB_1_0 21␊
5136# define R300_ALU_RGB_0_5 22␊
5137# define R300_ALU_RGB_SRC0_GBR 23␊
5138# define R300_ALU_RGB_SRC1_GBR 24␊
5139# define R300_ALU_RGB_SRC2_GBR 25␊
5140# define R300_ALU_RGB_SRC0_BRG 26␊
5141# define R300_ALU_RGB_SRC1_BRG 27␊
5142# define R300_ALU_RGB_SRC2_BRG 28␊
5143# define R300_ALU_RGB_SRC0_ABG 29␊
5144# define R300_ALU_RGB_SRC1_ABG 30␊
5145# define R300_ALU_RGB_SRC2_ABG 31␊
5146# define R300_ALU_RGB_MOD_A(x) ((x) << 5)␊
5147# define R300_ALU_RGB_MOD_NOP 0␊
5148# define R300_ALU_RGB_MOD_NEG 1␊
5149# define R300_ALU_RGB_MOD_ABS 2␊
5150# define R300_ALU_RGB_MOD_NAB 3␊
5151# define R300_ALU_RGB_SEL_B(x) ((x) << 7)␊
5152# define R300_ALU_RGB_MOD_B(x) ((x) << 12)␊
5153# define R300_ALU_RGB_SEL_C(x) ((x) << 14)␊
5154# define R300_ALU_RGB_MOD_C(x) ((x) << 19)␊
5155# define R300_ALU_RGB_SRCP_OP(x) ((x) << 21)␊
5156# define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0␉0␊
5157# define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0␉1␊
5158# define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0␉2␊
5159# define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0␉3␊
5160# define R300_ALU_RGB_OP(x) ((x) << 23)␊
5161# define R300_ALU_RGB_OP_MAD 0␊
5162# define R300_ALU_RGB_OP_DP3 1␊
5163# define R300_ALU_RGB_OP_DP4 2␊
5164# define R300_ALU_RGB_OP_D2A 3␊
5165# define R300_ALU_RGB_OP_MIN 4␊
5166# define R300_ALU_RGB_OP_MAX 5␊
5167# define R300_ALU_RGB_OP_CND 7␊
5168# define R300_ALU_RGB_OP_CMP 8␊
5169# define R300_ALU_RGB_OP_FRC 9␊
5170# define R300_ALU_RGB_OP_SOP 10␊
5171# define R300_ALU_RGB_OMOD(x) ((x) << 27)␊
5172# define R300_ALU_RGB_OMOD_NONE 0␊
5173# define R300_ALU_RGB_OMOD_MUL_2 1␊
5174# define R300_ALU_RGB_OMOD_MUL_4 2␊
5175# define R300_ALU_RGB_OMOD_MUL_8 3␊
5176# define R300_ALU_RGB_OMOD_DIV_2 4␊
5177# define R300_ALU_RGB_OMOD_DIV_4 5␊
5178# define R300_ALU_RGB_OMOD_DIV_8 6␊
5179# define R300_ALU_RGB_CLAMP (1 << 30)␊
5180# define R300_ALU_RGB_INSERT_NOP (1 << 31)␊
5181#define R300_US_ALU_ALPHA_ADDR_0␉␉ 0x47c0␊
5182#define R300_US_ALU_ALPHA_ADDR_1␉␉ 0x47c4␊
5183#define R300_US_ALU_ALPHA_ADDR_2␉␉ 0x47c8␊
5184#define R300_US_ALU_ALPHA_ADDR(x)␉␉ (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)␊
5185/* for ADDR0-2, values 0-31 specify a location in the pixel stack,␊
5186 values 32-63 specify a constant */␊
5187# define R300_ALU_ALPHA_ADDR0(x) ((x) << 0)␊
5188# define R300_ALU_ALPHA_ADDR1(x) ((x) << 6)␊
5189# define R300_ALU_ALPHA_ADDR2(x) ((x) << 12)␊
5190# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5))␊
5191/* ADDRD - where on the pixel stack the result of this instruction␊
5192 will be written */␊
5193# define R300_ALU_ALPHA_ADDRD(x) ((x) << 18)␊
5194# define R300_ALU_ALPHA_WMASK(x) ((x) << 23)␊
5195# define R300_ALU_ALPHA_OMASK(x) ((x) << 24)␊
5196# define R300_ALU_ALPHA_OMASK_W(x) ((x) << 27)␊
5197# define R300_ALU_ALPHA_MASK_NONE 0␊
5198# define R300_ALU_ALPHA_MASK_A 1␊
5199# define R300_ALU_ALPHA_TARGET_A (0 << 25)␊
5200# define R300_ALU_ALPHA_TARGET_B (1 << 25)␊
5201# define R300_ALU_ALPHA_TARGET_C (2 << 25)␊
5202# define R300_ALU_ALPHA_TARGET_D (3 << 25)␊
5203#define R300_US_ALU_ALPHA_INST_0␉␉ 0x49c0␊
5204#define R300_US_ALU_ALPHA_INST_1␉␉ 0x49c4␊
5205#define R300_US_ALU_ALPHA_INST_2␉␉ 0x49c8␊
5206#define R300_US_ALU_ALPHA_INST(x)␉␉ (R300_US_ALU_ALPHA_INST_0 + (x)*4)␊
5207# define R300_ALU_ALPHA_SEL_A(x) ((x) << 0)␊
5208# define R300_ALU_ALPHA_SRC0_R 0␊
5209# define R300_ALU_ALPHA_SRC0_G 1␊
5210# define R300_ALU_ALPHA_SRC0_B 2␊
5211# define R300_ALU_ALPHA_SRC1_R 3␊
5212# define R300_ALU_ALPHA_SRC1_G 4␊
5213# define R300_ALU_ALPHA_SRC1_B 5␊
5214# define R300_ALU_ALPHA_SRC2_R 6␊
5215# define R300_ALU_ALPHA_SRC2_G 7␊
5216# define R300_ALU_ALPHA_SRC2_B 8␊
5217# define R300_ALU_ALPHA_SRC0_A 9␊
5218# define R300_ALU_ALPHA_SRC1_A 10␊
5219# define R300_ALU_ALPHA_SRC2_A 11␊
5220# define R300_ALU_ALPHA_SRCP_R 12␊
5221# define R300_ALU_ALPHA_SRCP_G 13␊
5222# define R300_ALU_ALPHA_SRCP_B 14␊
5223# define R300_ALU_ALPHA_SRCP_A 15␊
5224# define R300_ALU_ALPHA_0_0 16␊
5225# define R300_ALU_ALPHA_1_0 17␊
5226# define R300_ALU_ALPHA_0_5 18␊
5227# define R300_ALU_ALPHA_MOD_A(x) ((x) << 5)␊
5228# define R300_ALU_ALPHA_MOD_NOP 0␊
5229# define R300_ALU_ALPHA_MOD_NEG 1␊
5230# define R300_ALU_ALPHA_MOD_ABS 2␊
5231# define R300_ALU_ALPHA_MOD_NAB 3␊
5232# define R300_ALU_ALPHA_SEL_B(x) ((x) << 7)␊
5233# define R300_ALU_ALPHA_MOD_B(x) ((x) << 12)␊
5234# define R300_ALU_ALPHA_SEL_C(x) ((x) << 14)␊
5235# define R300_ALU_ALPHA_MOD_C(x) ((x) << 19)␊
5236# define R300_ALU_ALPHA_SRCP_OP(x) ((x) << 21)␊
5237# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0␉0␊
5238# define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0␉1␊
5239# define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0␉2␊
5240# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0␉3␊
5241# define R300_ALU_ALPHA_OP(x) ((x) << 23)␊
5242# define R300_ALU_ALPHA_OP_MAD 0␊
5243# define R300_ALU_ALPHA_OP_DP 1␊
5244# define R300_ALU_ALPHA_OP_MIN 2␊
5245# define R300_ALU_ALPHA_OP_MAX 3␊
5246# define R300_ALU_ALPHA_OP_CND 5␊
5247# define R300_ALU_ALPHA_OP_CMP 6␊
5248# define R300_ALU_ALPHA_OP_FRC 7␊
5249# define R300_ALU_ALPHA_OP_EX2 8␊
5250# define R300_ALU_ALPHA_OP_LN2 9␊
5251# define R300_ALU_ALPHA_OP_RCP 10␊
5252# define R300_ALU_ALPHA_OP_RSQ 11␊
5253# define R300_ALU_ALPHA_OMOD(x) ((x) << 27)␊
5254# define R300_ALU_ALPHA_OMOD_NONE 0␊
5255# define R300_ALU_ALPHA_OMOD_MUL_2 1␊
5256# define R300_ALU_ALPHA_OMOD_MUL_4 2␊
5257# define R300_ALU_ALPHA_OMOD_MUL_8 3␊
5258# define R300_ALU_ALPHA_OMOD_DIV_2 4␊
5259# define R300_ALU_ALPHA_OMOD_DIV_4 5␊
5260# define R300_ALU_ALPHA_OMOD_DIV_8 6␊
5261# define R300_ALU_ALPHA_CLAMP (1 << 30)␊
5262␊
5263#define R300_US_ALU_CONST_R_0 0x4c00␊
5264#define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)␊
5265#define R300_US_ALU_CONST_G_0 0x4c04␊
5266#define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)␊
5267#define R300_US_ALU_CONST_B_0 0x4c08␊
5268#define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)␊
5269#define R300_US_ALU_CONST_A_0 0x4c0c␊
5270#define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)␊
5271␊
5272#define R300_FG_DEPTH_SRC␉␉␉␉0x4bd8␊
5273#define R300_FG_FOG_BLEND␉␉␉␉0x4bc0␊
5274#define R300_FG_ALPHA_FUNC␉␉␉␉0x4bd4␊
5275␊
5276#define R300_DST_PIPE_CONFIG␉␉ 0x170c␊
5277# define R300_PIPE_AUTO_CONFIG (1 << 31)␊
5278#define R300_RB2D_DSTCACHE_MODE␉␉ 0x3428␊
5279#define R300_RB2D_DSTCACHE_MODE␉␉ 0x3428␊
5280# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)␊
5281# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)␊
5282#define R300_RB2D_DSTCACHE_CTLSTAT␉␉ 0x342c /* use DSTCACHE_CTLSTAT instead */␊
5283#define R300_DSTCACHE_CTLSTAT␉␉ 0x1714␊
5284# define R300_DC_FLUSH_2D (1 << 0)␊
5285# define R300_DC_FREE_2D (1 << 2)␊
5286# define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D)␊
5287# define R300_RB2D_DC_BUSY (1 << 31)␊
5288#define R300_RB3D_DSTCACHE_CTLSTAT␉␉ 0x4e4c␊
5289# define R300_DC_FLUSH_3D (2 << 0)␊
5290# define R300_DC_FREE_3D (2 << 2)␊
5291# define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D)␊
5292# define R300_DC_FINISH_3D (1 << 4)␊
5293#define R300_RB3D_ZCACHE_CTLSTAT␉␉␉0x4f18␊
5294# define R300_ZC_FLUSH (1 << 0)␊
5295# define R300_ZC_FREE (1 << 1)␊
5296# define R300_ZC_FLUSH_ALL 0x3␊
5297#define R300_RB3D_ZSTENCILCNTL␉␉␉ 0x4f04␊
5298#define R300_RB3D_ZCACHE_CTLSTAT␉␉ 0x4f18␊
5299#define R300_RB3D_BW_CNTL␉␉␉␉0x4f1c␊
5300#define R300_RB3D_ZCNTL␉␉␉␉ 0x4f00␊
5301#define R300_RB3D_ZTOP␉␉␉␉ 0x4f14␊
5302#define R300_RB3D_ROPCNTL␉␉␉␉0x4e18␊
5303#define R300_RB3D_BLENDCNTL␉␉␉␉0x4e04␊
5304# define R300_ALPHA_BLEND_ENABLE (1 << 0)␊
5305# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)␊
5306# define R300_READ_ENABLE (1 << 2)␊
5307#define R300_RB3D_ABLENDCNTL␉␉␉ 0x4e08␊
5308#define R300_RB3D_DSTCACHE_CTLSTAT␉␉ 0x4e4c␊
5309#define R300_RB3D_COLOROFFSET0␉␉␉ 0x4e28␊
5310#define R300_RB3D_COLORPITCH0␉␉␉ 0x4e38␊
5311# define R300_COLORTILE (1 << 16)␊
5312# define R300_COLORENDIAN_WORD (1 << 19)␊
5313# define R300_COLORENDIAN_DWORD (2 << 19)␊
5314# define R300_COLORENDIAN_HALF_DWORD (3 << 19)␊
5315# define R300_COLORFORMAT_ARGB1555 (3 << 21)␊
5316# define R300_COLORFORMAT_RGB565 (4 << 21)␊
5317# define R300_COLORFORMAT_ARGB8888 (6 << 21)␊
5318# define R300_COLORFORMAT_ARGB32323232 (7 << 21)␊
5319# define R300_COLORFORMAT_I8 (9 << 21)␊
5320# define R300_COLORFORMAT_ARGB16161616 (10 << 21)␊
5321# define R300_COLORFORMAT_VYUY (11 << 21)␊
5322# define R300_COLORFORMAT_YVYU (12 << 21)␊
5323# define R300_COLORFORMAT_UV88 (13 << 21)␊
5324# define R300_COLORFORMAT_ARGB4444 (15 << 21)␊
5325␊
5326#define R300_RB3D_AARESOLVE_CTL␉␉␉ 0x4e88␊
5327#define R300_RB3D_COLOR_CHANNEL_MASK␉ 0x4e0c␊
5328# define R300_BLUE_MASK_EN (1 << 0)␊
5329# define R300_GREEN_MASK_EN (1 << 1)␊
5330# define R300_RED_MASK_EN (1 << 2)␊
5331# define R300_ALPHA_MASK_EN (1 << 3)␊
5332#define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14␊
5333#define R300_RB3D_DSTCACHE_CTLSTAT␉␉ 0x4e4c␊
5334#define R300_RB3D_CCTL␉␉␉␉ 0x4e00␊
5335#define R300_RB3D_DITHER_CTL␉␉␉ 0x4e50␊
5336␊
5337#define R300_SC_EDGERULE␉␉␉␉0x43a8␊
5338#define R300_SC_SCISSOR0␉␉␉␉0x43e0␊
5339#define R300_SC_SCISSOR1␉␉␉␉0x43e4␊
5340# define R300_SCISSOR_X_SHIFT 0␊
5341# define R300_SCISSOR_Y_SHIFT 13␊
5342#define R300_SC_CLIP_0_A␉␉␉␉0x43b0␊
5343#define R300_SC_CLIP_0_B␉␉␉␉0x43b4␊
5344# define R300_CLIP_X_SHIFT 0␊
5345# define R300_CLIP_Y_SHIFT 13␊
5346#define R300_SC_CLIP_RULE␉␉␉␉0x43d0␊
5347#define R300_SC_SCREENDOOR␉␉␉␉0x43e8␊
5348␊
5349/* R500 US has to be loaded through an index/data pair */␊
5350#define R500_GA_US_VECTOR_INDEX␉␉␉␉0x4250␊
5351# define R500_US_VECTOR_TYPE_INST␉␉␉(0 << 16)␊
5352# define R500_US_VECTOR_TYPE_CONST␉␉␉(1 << 16)␊
5353# define R500_US_VECTOR_CLAMP␉␉␉␉(1 << 17)␊
5354# define R500_US_VECTOR_INST_INDEX(x)␉␉␉((x) | R500_US_VECTOR_TYPE_INST)␊
5355# define R500_US_VECTOR_CONST_INDEX(x)␉␉((x) | R500_US_VECTOR_TYPE_CONST)␊
5356#define R500_GA_US_VECTOR_DATA␉␉␉␉0x4254␊
5357␊
5358/*␊
5359 * The R500 unified shader (US) registers come in banks of 512 each, one␊
5360 * for each instruction slot in the shader. You can't touch them directly.␊
5361 * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive␊
5362 * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the␊
5363 * instruction is fully specified.␊
5364 */␊
5365#define R500_US_ALU_ALPHA_INST_0␉␉␉0xa800␊
5366# define R500_ALPHA_OP_MAD␉␉␉␉0␊
5367# define R500_ALPHA_OP_DP␉␉␉␉1␊
5368# define R500_ALPHA_OP_MIN␉␉␉␉2␊
5369# define R500_ALPHA_OP_MAX␉␉␉␉3␊
5370/* #define R500_ALPHA_OP_RESERVED␉␉␉4 */␊
5371# define R500_ALPHA_OP_CND␉␉␉␉5␊
5372# define R500_ALPHA_OP_CMP␉␉␉␉6␊
5373# define R500_ALPHA_OP_FRC␉␉␉␉7␊
5374# define R500_ALPHA_OP_EX2␉␉␉␉8␊
5375# define R500_ALPHA_OP_LN2␉␉␉␉9␊
5376# define R500_ALPHA_OP_RCP␉␉␉␉10␊
5377# define R500_ALPHA_OP_RSQ␉␉␉␉11␊
5378# define R500_ALPHA_OP_SIN␉␉␉␉12␊
5379# define R500_ALPHA_OP_COS␉␉␉␉13␊
5380# define R500_ALPHA_OP_MDH␉␉␉␉14␊
5381# define R500_ALPHA_OP_MDV␉␉␉␉15␊
5382# define R500_ALPHA_ADDRD(x)␉␉␉␉((x) << 4)␊
5383# define R500_ALPHA_ADDRD_REL␉␉␉␉(1 << 11)␊
5384# define R500_ALPHA_SEL_A_SRC0␉␉␉(0 << 12)␊
5385# define R500_ALPHA_SEL_A_SRC1␉␉␉(1 << 12)␊
5386# define R500_ALPHA_SEL_A_SRC2␉␉␉(2 << 12)␊
5387# define R500_ALPHA_SEL_A_SRCP␉␉␉(3 << 12)␊
5388# define R500_ALPHA_SWIZ_A_R␉␉␉␉(0 << 14)␊
5389# define R500_ALPHA_SWIZ_A_G␉␉␉␉(1 << 14)␊
5390# define R500_ALPHA_SWIZ_A_B␉␉␉␉(2 << 14)␊
5391# define R500_ALPHA_SWIZ_A_A␉␉␉␉(3 << 14)␊
5392# define R500_ALPHA_SWIZ_A_0␉␉␉␉(4 << 14)␊
5393# define R500_ALPHA_SWIZ_A_HALF␉␉␉(5 << 14)␊
5394# define R500_ALPHA_SWIZ_A_1␉␉␉␉(6 << 14)␊
5395/* #define R500_ALPHA_SWIZ_A_UNUSED␉␉␉(7 << 14) */␊
5396# define R500_ALPHA_MOD_A_NOP␉␉␉␉(0 << 17)␊
5397# define R500_ALPHA_MOD_A_NEG␉␉␉␉(1 << 17)␊
5398# define R500_ALPHA_MOD_A_ABS␉␉␉␉(2 << 17)␊
5399# define R500_ALPHA_MOD_A_NAB␉␉␉␉(3 << 17)␊
5400# define R500_ALPHA_SEL_B_SRC0␉␉␉(0 << 19)␊
5401# define R500_ALPHA_SEL_B_SRC1␉␉␉(1 << 19)␊
5402# define R500_ALPHA_SEL_B_SRC2␉␉␉(2 << 19)␊
5403# define R500_ALPHA_SEL_B_SRCP␉␉␉(3 << 19)␊
5404# define R500_ALPHA_SWIZ_B_R␉␉␉␉(0 << 21)␊
5405# define R500_ALPHA_SWIZ_B_G␉␉␉␉(1 << 21)␊
5406# define R500_ALPHA_SWIZ_B_B␉␉␉␉(2 << 21)␊
5407# define R500_ALPHA_SWIZ_B_A␉␉␉␉(3 << 21)␊
5408# define R500_ALPHA_SWIZ_B_0␉␉␉␉(4 << 21)␊
5409# define R500_ALPHA_SWIZ_B_HALF␉␉␉(5 << 21)␊
5410# define R500_ALPHA_SWIZ_B_1␉␉␉␉(6 << 21)␊
5411/* #define R500_ALPHA_SWIZ_B_UNUSED␉␉␉(7 << 21) */␊
5412# define R500_ALPHA_MOD_B_NOP␉␉␉␉(0 << 24)␊
5413# define R500_ALPHA_MOD_B_NEG␉␉␉␉(1 << 24)␊
5414# define R500_ALPHA_MOD_B_ABS␉␉␉␉(2 << 24)␊
5415# define R500_ALPHA_MOD_B_NAB␉␉␉␉(3 << 24)␊
5416# define R500_ALPHA_OMOD_IDENTITY␉␉␉(0 << 26)␊
5417# define R500_ALPHA_OMOD_MUL_2␉␉␉(1 << 26)␊
5418# define R500_ALPHA_OMOD_MUL_4␉␉␉(2 << 26)␊
5419# define R500_ALPHA_OMOD_MUL_8␉␉␉(3 << 26)␊
5420# define R500_ALPHA_OMOD_DIV_2␉␉␉(4 << 26)␊
5421# define R500_ALPHA_OMOD_DIV_4␉␉␉(5 << 26)␊
5422# define R500_ALPHA_OMOD_DIV_8␉␉␉(6 << 26)␊
5423# define R500_ALPHA_OMOD_DISABLE␉␉␉(7 << 26)␊
5424# define R500_ALPHA_TARGET(x)␉␉␉␉((x) << 29)␊
5425# define R500_ALPHA_W_OMASK␉␉␉␉(1 << 31)␊
5426#define R500_US_ALU_ALPHA_ADDR_0␉␉␉0x9800␊
5427# define R500_ALPHA_ADDR0(x)␉␉␉␉((x) << 0)␊
5428# define R500_ALPHA_ADDR0_CONST␉␉␉(1 << 8)␊
5429# define R500_ALPHA_ADDR0_REL␉␉␉␉(1 << 9)␊
5430# define R500_ALPHA_ADDR1(x)␉␉␉␉((x) << 10)␊
5431# define R500_ALPHA_ADDR1_CONST␉␉␉(1 << 18)␊
5432# define R500_ALPHA_ADDR1_REL␉␉␉␉(1 << 19)␊
5433# define R500_ALPHA_ADDR2(x)␉␉␉␉((x) << 20)␊
5434# define R500_ALPHA_ADDR2_CONST␉␉␉(1 << 28)␊
5435# define R500_ALPHA_ADDR2_REL␉␉␉␉(1 << 29)␊
5436# define R500_ALPHA_SRCP_OP_1_MINUS_2A0␉␉(0 << 30)␊
5437# define R500_ALPHA_SRCP_OP_A1_MINUS_A0␉␉(1 << 30)␊
5438# define R500_ALPHA_SRCP_OP_A1_PLUS_A0␉␉(2 << 30)␊
5439# define R500_ALPHA_SRCP_OP_1_MINUS_A0␉␉(3 << 30)␊
5440#define R500_US_ALU_RGBA_INST_0␉␉␉␉0xb000␊
5441# define R500_ALU_RGBA_OP_MAD␉␉␉␉(0 << 0)␊
5442# define R500_ALU_RGBA_OP_DP3␉␉␉␉(1 << 0)␊
5443# define R500_ALU_RGBA_OP_DP4␉␉␉␉(2 << 0)␊
5444# define R500_ALU_RGBA_OP_D2A␉␉␉␉(3 << 0)␊
5445# define R500_ALU_RGBA_OP_MIN␉␉␉␉(4 << 0)␊
5446# define R500_ALU_RGBA_OP_MAX␉␉␉␉(5 << 0)␊
5447/* #define R500_ALU_RGBA_OP_RESERVED␉␉␉(6 << 0) */␊
5448# define R500_ALU_RGBA_OP_CND␉␉␉␉(7 << 0)␊
5449# define R500_ALU_RGBA_OP_CMP␉␉␉␉(8 << 0)␊
5450# define R500_ALU_RGBA_OP_FRC␉␉␉␉(9 << 0)␊
5451# define R500_ALU_RGBA_OP_SOP␉␉␉␉(10 << 0)␊
5452# define R500_ALU_RGBA_OP_MDH␉␉␉␉(11 << 0)␊
5453# define R500_ALU_RGBA_OP_MDV␉␉␉␉(12 << 0)␊
5454# define R500_ALU_RGBA_ADDRD(x)␉␉␉((x) << 4)␊
5455# define R500_ALU_RGBA_ADDRD_REL␉␉␉(1 << 11)␊
5456# define R500_ALU_RGBA_SEL_C_SRC0␉␉␉(0 << 12)␊
5457# define R500_ALU_RGBA_SEL_C_SRC1␉␉␉(1 << 12)␊
5458# define R500_ALU_RGBA_SEL_C_SRC2␉␉␉(2 << 12)␊
5459# define R500_ALU_RGBA_SEL_C_SRCP␉␉␉(3 << 12)␊
5460# define R500_ALU_RGBA_R_SWIZ_R␉␉␉(0 << 14)␊
5461# define R500_ALU_RGBA_R_SWIZ_G␉␉␉(1 << 14)␊
5462# define R500_ALU_RGBA_R_SWIZ_B␉␉␉(2 << 14)␊
5463# define R500_ALU_RGBA_R_SWIZ_A␉␉␉(3 << 14)␊
5464# define R500_ALU_RGBA_R_SWIZ_0␉␉␉(4 << 14)␊
5465# define R500_ALU_RGBA_R_SWIZ_HALF␉␉␉(5 << 14)␊
5466# define R500_ALU_RGBA_R_SWIZ_1␉␉␉(6 << 14)␊
5467/* #define R500_ALU_RGBA_R_SWIZ_UNUSED␉␉␉(7 << 14) */␊
5468# define R500_ALU_RGBA_G_SWIZ_R␉␉␉(0 << 17)␊
5469# define R500_ALU_RGBA_G_SWIZ_G␉␉␉(1 << 17)␊
5470# define R500_ALU_RGBA_G_SWIZ_B␉␉␉(2 << 17)␊
5471# define R500_ALU_RGBA_G_SWIZ_A␉␉␉(3 << 17)␊
5472# define R500_ALU_RGBA_G_SWIZ_0␉␉␉(4 << 17)␊
5473# define R500_ALU_RGBA_G_SWIZ_HALF␉␉␉(5 << 17)␊
5474# define R500_ALU_RGBA_G_SWIZ_1␉␉␉(6 << 17)␊
5475/* #define R500_ALU_RGBA_G_SWIZ_UNUSED␉␉␉(7 << 17) */␊
5476# define R500_ALU_RGBA_B_SWIZ_R␉␉␉(0 << 20)␊
5477# define R500_ALU_RGBA_B_SWIZ_G␉␉␉(1 << 20)␊
5478# define R500_ALU_RGBA_B_SWIZ_B␉␉␉(2 << 20)␊
5479# define R500_ALU_RGBA_B_SWIZ_A␉␉␉(3 << 20)␊
5480# define R500_ALU_RGBA_B_SWIZ_0␉␉␉(4 << 20)␊
5481# define R500_ALU_RGBA_B_SWIZ_HALF␉␉␉(5 << 20)␊
5482# define R500_ALU_RGBA_B_SWIZ_1␉␉␉(6 << 20)␊
5483/* #define R500_ALU_RGBA_B_SWIZ_UNUSED␉␉␉(7 << 20) */␊
5484# define R500_ALU_RGBA_MOD_C_NOP␉␉␉(0 << 23)␊
5485# define R500_ALU_RGBA_MOD_C_NEG␉␉␉(1 << 23)␊
5486# define R500_ALU_RGBA_MOD_C_ABS␉␉␉(2 << 23)␊
5487# define R500_ALU_RGBA_MOD_C_NAB␉␉␉(3 << 23)␊
5488# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0␉␉(0 << 25)␊
5489# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1␉␉(1 << 25)␊
5490# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2␉␉(2 << 25)␊
5491# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP␉␉(3 << 25)␊
5492# define R500_ALU_RGBA_A_SWIZ_R␉␉␉(0 << 27)␊
5493# define R500_ALU_RGBA_A_SWIZ_G␉␉␉(1 << 27)␊
5494# define R500_ALU_RGBA_A_SWIZ_B␉␉␉(2 << 27)␊
5495# define R500_ALU_RGBA_A_SWIZ_A␉␉␉(3 << 27)␊
5496# define R500_ALU_RGBA_A_SWIZ_0␉␉␉(4 << 27)␊
5497# define R500_ALU_RGBA_A_SWIZ_HALF␉␉␉(5 << 27)␊
5498# define R500_ALU_RGBA_A_SWIZ_1␉␉␉(6 << 27)␊
5499/* #define R500_ALU_RGBA_A_SWIZ_UNUSED␉␉␉(7 << 27) */␊
5500# define R500_ALU_RGBA_ALPHA_MOD_C_NOP␉␉(0 << 30)␊
5501# define R500_ALU_RGBA_ALPHA_MOD_C_NEG␉␉(1 << 30)␊
5502# define R500_ALU_RGBA_ALPHA_MOD_C_ABS␉␉(2 << 30)␊
5503# define R500_ALU_RGBA_ALPHA_MOD_C_NAB␉␉(3 << 30)␊
5504#define R500_US_ALU_RGB_INST_0␉␉␉␉0xa000␊
5505# define R500_ALU_RGB_SEL_A_SRC0␉␉␉(0 << 0)␊
5506# define R500_ALU_RGB_SEL_A_SRC1␉␉␉(1 << 0)␊
5507# define R500_ALU_RGB_SEL_A_SRC2␉␉␉(2 << 0)␊
5508# define R500_ALU_RGB_SEL_A_SRCP␉␉␉(3 << 0)␊
5509# define R500_ALU_RGB_R_SWIZ_A_R␉␉␉(0 << 2)␊
5510# define R500_ALU_RGB_R_SWIZ_A_G␉␉␉(1 << 2)␊
5511# define R500_ALU_RGB_R_SWIZ_A_B␉␉␉(2 << 2)␊
5512# define R500_ALU_RGB_R_SWIZ_A_A␉␉␉(3 << 2)␊
5513# define R500_ALU_RGB_R_SWIZ_A_0␉␉␉(4 << 2)␊
5514# define R500_ALU_RGB_R_SWIZ_A_HALF␉␉␉(5 << 2)␊
5515# define R500_ALU_RGB_R_SWIZ_A_1␉␉␉(6 << 2)␊
5516/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED␉␉␉(7 << 2) */␊
5517# define R500_ALU_RGB_G_SWIZ_A_R␉␉␉(0 << 5)␊
5518# define R500_ALU_RGB_G_SWIZ_A_G␉␉␉(1 << 5)␊
5519# define R500_ALU_RGB_G_SWIZ_A_B␉␉␉(2 << 5)␊
5520# define R500_ALU_RGB_G_SWIZ_A_A␉␉␉(3 << 5)␊
5521# define R500_ALU_RGB_G_SWIZ_A_0␉␉␉(4 << 5)␊
5522# define R500_ALU_RGB_G_SWIZ_A_HALF␉␉␉(5 << 5)␊
5523# define R500_ALU_RGB_G_SWIZ_A_1␉␉␉(6 << 5)␊
5524/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED␉␉␉(7 << 5) */␊
5525# define R500_ALU_RGB_B_SWIZ_A_R␉␉␉(0 << 8)␊
5526# define R500_ALU_RGB_B_SWIZ_A_G␉␉␉(1 << 8)␊
5527# define R500_ALU_RGB_B_SWIZ_A_B␉␉␉(2 << 8)␊
5528# define R500_ALU_RGB_B_SWIZ_A_A␉␉␉(3 << 8)␊
5529# define R500_ALU_RGB_B_SWIZ_A_0␉␉␉(4 << 8)␊
5530# define R500_ALU_RGB_B_SWIZ_A_HALF␉␉␉(5 << 8)␊
5531# define R500_ALU_RGB_B_SWIZ_A_1␉␉␉(6 << 8)␊
5532/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED␉␉␉(7 << 8) */␊
5533# define R500_ALU_RGB_MOD_A_NOP␉␉␉(0 << 11)␊
5534# define R500_ALU_RGB_MOD_A_NEG␉␉␉(1 << 11)␊
5535# define R500_ALU_RGB_MOD_A_ABS␉␉␉(2 << 11)␊
5536# define R500_ALU_RGB_MOD_A_NAB␉␉␉(3 << 11)␊
5537# define R500_ALU_RGB_SEL_B_SRC0␉␉␉(0 << 13)␊
5538# define R500_ALU_RGB_SEL_B_SRC1␉␉␉(1 << 13)␊
5539# define R500_ALU_RGB_SEL_B_SRC2␉␉␉(2 << 13)␊
5540# define R500_ALU_RGB_SEL_B_SRCP␉␉␉(3 << 13)␊
5541# define R500_ALU_RGB_R_SWIZ_B_R␉␉␉(0 << 15)␊
5542# define R500_ALU_RGB_R_SWIZ_B_G␉␉␉(1 << 15)␊
5543# define R500_ALU_RGB_R_SWIZ_B_B␉␉␉(2 << 15)␊
5544# define R500_ALU_RGB_R_SWIZ_B_A␉␉␉(3 << 15)␊
5545# define R500_ALU_RGB_R_SWIZ_B_0␉␉␉(4 << 15)␊
5546# define R500_ALU_RGB_R_SWIZ_B_HALF␉␉␉(5 << 15)␊
5547# define R500_ALU_RGB_R_SWIZ_B_1␉␉␉(6 << 15)␊
5548/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED␉␉␉(7 << 15) */␊
5549# define R500_ALU_RGB_G_SWIZ_B_R␉␉␉(0 << 18)␊
5550# define R500_ALU_RGB_G_SWIZ_B_G␉␉␉(1 << 18)␊
5551# define R500_ALU_RGB_G_SWIZ_B_B␉␉␉(2 << 18)␊
5552# define R500_ALU_RGB_G_SWIZ_B_A␉␉␉(3 << 18)␊
5553# define R500_ALU_RGB_G_SWIZ_B_0␉␉␉(4 << 18)␊
5554# define R500_ALU_RGB_G_SWIZ_B_HALF␉␉␉(5 << 18)␊
5555# define R500_ALU_RGB_G_SWIZ_B_1␉␉␉(6 << 18)␊
5556/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED␉␉␉(7 << 18) */␊
5557# define R500_ALU_RGB_B_SWIZ_B_R␉␉␉(0 << 21)␊
5558# define R500_ALU_RGB_B_SWIZ_B_G␉␉␉(1 << 21)␊
5559# define R500_ALU_RGB_B_SWIZ_B_B␉␉␉(2 << 21)␊
5560# define R500_ALU_RGB_B_SWIZ_B_A␉␉␉(3 << 21)␊
5561# define R500_ALU_RGB_B_SWIZ_B_0␉␉␉(4 << 21)␊
5562# define R500_ALU_RGB_B_SWIZ_B_HALF␉␉␉(5 << 21)␊
5563# define R500_ALU_RGB_B_SWIZ_B_1␉␉␉(6 << 21)␊
5564/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED␉␉␉(7 << 21) */␊
5565# define R500_ALU_RGB_MOD_B_NOP␉␉␉(0 << 24)␊
5566# define R500_ALU_RGB_MOD_B_NEG␉␉␉(1 << 24)␊
5567# define R500_ALU_RGB_MOD_B_ABS␉␉␉(2 << 24)␊
5568# define R500_ALU_RGB_MOD_B_NAB␉␉␉(3 << 24)␊
5569# define R500_ALU_RGB_OMOD_IDENTITY␉␉␉(0 << 26)␊
5570# define R500_ALU_RGB_OMOD_MUL_2␉␉␉(1 << 26)␊
5571# define R500_ALU_RGB_OMOD_MUL_4␉␉␉(2 << 26)␊
5572# define R500_ALU_RGB_OMOD_MUL_8␉␉␉(3 << 26)␊
5573# define R500_ALU_RGB_OMOD_DIV_2␉␉␉(4 << 26)␊
5574# define R500_ALU_RGB_OMOD_DIV_4␉␉␉(5 << 26)␊
5575# define R500_ALU_RGB_OMOD_DIV_8␉␉␉(6 << 26)␊
5576# define R500_ALU_RGB_OMOD_DISABLE␉␉␉(7 << 26)␊
5577# define R500_ALU_RGB_TARGET(x)␉␉␉((x) << 29)␊
5578# define R500_ALU_RGB_WMASK␉␉␉␉(1 << 31)␊
5579#define R500_US_ALU_RGB_ADDR_0␉␉␉␉0x9000␊
5580# define R500_RGB_ADDR0(x)␉␉␉␉((x) << 0)␊
5581# define R500_RGB_ADDR0_CONST␉␉␉␉(1 << 8)␊
5582# define R500_RGB_ADDR0_REL␉␉␉␉(1 << 9)␊
5583# define R500_RGB_ADDR1(x)␉␉␉␉((x) << 10)␊
5584# define R500_RGB_ADDR1_CONST␉␉␉␉(1 << 18)␊
5585# define R500_RGB_ADDR1_REL␉␉␉␉(1 << 19)␊
5586# define R500_RGB_ADDR2(x)␉␉␉␉((x) << 20)␊
5587# define R500_RGB_ADDR2_CONST␉␉␉␉(1 << 28)␊
5588# define R500_RGB_ADDR2_REL␉␉␉␉(1 << 29)␊
5589# define R500_RGB_SRCP_OP_1_MINUS_2RGB0␉␉(0 << 30)␊
5590# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0␉␉(1 << 30)␊
5591# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0␉␉(2 << 30)␊
5592# define R500_RGB_SRCP_OP_1_MINUS_RGB0␉␉(3 << 30)␊
5593#define R500_US_CMN_INST_0␉␉␉␉0xb800␊
5594# define R500_INST_TYPE_ALU␉␉␉␉(0 << 0)␊
5595# define R500_INST_TYPE_OUT␉␉␉␉(1 << 0)␊
5596# define R500_INST_TYPE_FC␉␉␉␉(2 << 0)␊
5597# define R500_INST_TYPE_TEX␉␉␉␉(3 << 0)␊
5598# define R500_INST_TEX_SEM_WAIT␉␉␉(1 << 2)␊
5599# define R500_INST_RGB_PRED_SEL_NONE␉␉␉(0 << 3)␊
5600# define R500_INST_RGB_PRED_SEL_RGBA␉␉␉(1 << 3)␊
5601# define R500_INST_RGB_PRED_SEL_RRRR␉␉␉(2 << 3)␊
5602# define R500_INST_RGB_PRED_SEL_GGGG␉␉␉(3 << 3)␊
5603# define R500_INST_RGB_PRED_SEL_BBBB␉␉␉(4 << 3)␊
5604# define R500_INST_RGB_PRED_SEL_AAAA␉␉␉(5 << 3)␊
5605# define R500_INST_RGB_PRED_INV␉␉␉(1 << 6)␊
5606# define R500_INST_WRITE_INACTIVE␉␉␉(1 << 7)␊
5607# define R500_INST_LAST␉␉␉␉(1 << 8)␊
5608# define R500_INST_NOP␉␉␉␉(1 << 9)␊
5609# define R500_INST_ALU_WAIT␉␉␉␉(1 << 10)␊
5610# define R500_INST_RGB_WMASK_R␉␉␉(1 << 11)␊
5611# define R500_INST_RGB_WMASK_G␉␉␉(1 << 12)␊
5612# define R500_INST_RGB_WMASK_B␉␉␉(1 << 13)␊
5613# define R500_INST_ALPHA_WMASK␉␉␉(1 << 14)␊
5614# define R500_INST_RGB_OMASK_R␉␉␉(1 << 15)␊
5615# define R500_INST_RGB_OMASK_G␉␉␉(1 << 16)␊
5616# define R500_INST_RGB_OMASK_B␉␉␉(1 << 17)␊
5617# define R500_INST_ALPHA_OMASK␉␉␉(1 << 18)␊
5618# define R500_INST_RGB_CLAMP␉␉␉␉(1 << 19)␊
5619# define R500_INST_ALPHA_CLAMP␉␉␉(1 << 20)␊
5620# define R500_INST_ALU_RESULT_SEL␉␉␉(1 << 21)␊
5621# define R500_INST_ALPHA_PRED_INV␉␉␉(1 << 22)␊
5622# define R500_INST_ALU_RESULT_OP_EQ␉␉␉(0 << 23)␊
5623# define R500_INST_ALU_RESULT_OP_LT␉␉␉(1 << 23)␊
5624# define R500_INST_ALU_RESULT_OP_GE␉␉␉(2 << 23)␊
5625# define R500_INST_ALU_RESULT_OP_NE␉␉␉(3 << 23)␊
5626# define R500_INST_ALPHA_PRED_SEL_NONE␉␉(0 << 25)␊
5627# define R500_INST_ALPHA_PRED_SEL_RGBA␉␉(1 << 25)␊
5628# define R500_INST_ALPHA_PRED_SEL_RRRR␉␉(2 << 25)␊
5629# define R500_INST_ALPHA_PRED_SEL_GGGG␉␉(3 << 25)␊
5630# define R500_INST_ALPHA_PRED_SEL_BBBB␉␉(4 << 25)␊
5631# define R500_INST_ALPHA_PRED_SEL_AAAA␉␉(5 << 25)␊
5632/* XXX next four are kind of guessed */␊
5633# define R500_INST_STAT_WE_R␉␉␉␉(1 << 28)␊
5634# define R500_INST_STAT_WE_G␉␉␉␉(1 << 29)␊
5635# define R500_INST_STAT_WE_B␉␉␉␉(1 << 30)␊
5636# define R500_INST_STAT_WE_A␉␉␉␉(1 << 31)␊
5637/* note that these are 8 bit lengths, despite the offsets, at least for R500 */␊
5638#define R500_US_CODE_ADDR␉␉␉␉0x4630␊
5639# define R500_US_CODE_START_ADDR(x)␉␉␉((x) << 0)␊
5640# define R500_US_CODE_END_ADDR(x)␉␉␉((x) << 16)␊
5641#define R500_US_CODE_OFFSET␉␉␉␉0x4638␊
5642# define R500_US_CODE_OFFSET_ADDR(x)␉␉␉((x) << 0)␊
5643#define R500_US_CODE_RANGE␉␉␉␉0x4634␊
5644# define R500_US_CODE_RANGE_ADDR(x)␉␉␉((x) << 0)␊
5645# define R500_US_CODE_RANGE_SIZE(x)␉␉␉((x) << 16)␊
5646#define R500_US_CONFIG␉␉␉␉␉0x4600␊
5647# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO␉␉(1 << 1)␊
5648#define R500_US_FC_ADDR_0␉␉␉␉0xa000␊
5649# define R500_FC_BOOL_ADDR(x)␉␉␉␉((x) << 0)␊
5650# define R500_FC_INT_ADDR(x)␉␉␉␉((x) << 8)␊
5651# define R500_FC_JUMP_ADDR(x)␉␉␉␉((x) << 16)␊
5652# define R500_FC_JUMP_GLOBAL␉␉␉␉(1 << 31)␊
5653#define R500_US_FC_BOOL_CONST␉␉␉␉0x4620␊
5654# define R500_FC_KBOOL(x)␉␉␉␉(x)␊
5655#define R500_US_FC_CTRL␉␉␉␉␉0x4624␊
5656# define R500_FC_TEST_EN␉␉␉␉(1 << 30)␊
5657# define R500_FC_FULL_FC_EN␉␉␉␉(1 << 31)␊
5658#define R500_US_FC_INST_0␉␉␉␉0x9800␊
5659# define R500_FC_OP_JUMP␉␉␉␉(0 << 0)␊
5660# define R500_FC_OP_LOOP␉␉␉␉(1 << 0)␊
5661# define R500_FC_OP_ENDLOOP␉␉␉␉(2 << 0)␊
5662# define R500_FC_OP_REP␉␉␉␉(3 << 0)␊
5663# define R500_FC_OP_ENDREP␉␉␉␉(4 << 0)␊
5664# define R500_FC_OP_BREAKLOOP␉␉␉␉(5 << 0)␊
5665# define R500_FC_OP_BREAKREP␉␉␉␉(6 << 0)␊
5666# define R500_FC_OP_CONTINUE␉␉␉␉(7 << 0)␊
5667# define R500_FC_B_ELSE␉␉␉␉(1 << 4)␊
5668# define R500_FC_JUMP_ANY␉␉␉␉(1 << 5)␊
5669# define R500_FC_A_OP_NONE␉␉␉␉(0 << 6)␊
5670# define R500_FC_A_OP_POP␉␉␉␉(1 << 6)␊
5671# define R500_FC_A_OP_PUSH␉␉␉␉(2 << 6)␊
5672# define R500_FC_JUMP_FUNC(x)␉␉␉␉((x) << 8)␊
5673# define R500_FC_B_POP_CNT(x)␉␉␉␉((x) << 16)␊
5674# define R500_FC_B_OP0_NONE␉␉␉␉(0 << 24)␊
5675# define R500_FC_B_OP0_DECR␉␉␉␉(1 << 24)␊
5676# define R500_FC_B_OP0_INCR␉␉␉␉(2 << 24)␊
5677# define R500_FC_B_OP1_DECR␉␉␉␉(0 << 26)␊
5678# define R500_FC_B_OP1_NONE␉␉␉␉(1 << 26)␊
5679# define R500_FC_B_OP1_INCR␉␉␉␉(2 << 26)␊
5680# define R500_FC_IGNORE_UNCOVERED␉␉␉(1 << 28)␊
5681#define R500_US_FC_INT_CONST_0␉␉␉␉0x4c00␊
5682# define R500_FC_INT_CONST_KR(x)␉␉␉((x) << 0)␊
5683# define R500_FC_INT_CONST_KG(x)␉␉␉((x) << 8)␊
5684# define R500_FC_INT_CONST_KB(x)␉␉␉((x) << 16)␊
5685/* _0 through _15 */␊
5686#define R500_US_FORMAT0_0␉␉␉␉0x4640␊
5687# define R500_FORMAT_TXWIDTH(x)␉␉␉((x) << 0)␊
5688# define R500_FORMAT_TXHEIGHT(x)␉␉␉((x) << 11)␊
5689# define R500_FORMAT_TXDEPTH(x)␉␉␉((x) << 22)␊
5690/* _0 through _3 */␊
5691#define R500_US_OUT_FMT_0␉␉␉␉0x46a4␊
5692# define R500_OUT_FMT_C4_8␉␉␉␉(0 << 0)␊
5693# define R500_OUT_FMT_C4_10␉␉␉␉(1 << 0)␊
5694# define R500_OUT_FMT_C4_10_GAMMA␉␉␉(2 << 0)␊
5695# define R500_OUT_FMT_C_16␉␉␉␉(3 << 0)␊
5696# define R500_OUT_FMT_C2_16␉␉␉␉(4 << 0)␊
5697# define R500_OUT_FMT_C4_16␉␉␉␉(5 << 0)␊
5698# define R500_OUT_FMT_C_16_MPEG␉␉␉(6 << 0)␊
5699# define R500_OUT_FMT_C2_16_MPEG␉␉␉(7 << 0)␊
5700# define R500_OUT_FMT_C2_4␉␉␉␉(8 << 0)␊
5701# define R500_OUT_FMT_C_3_3_2␉␉␉␉(9 << 0)␊
5702# define R500_OUT_FMT_C_6_5_6␉␉␉␉(10 << 0)␊
5703# define R500_OUT_FMT_C_11_11_10␉␉␉(11 << 0)␊
5704# define R500_OUT_FMT_C_10_11_11␉␉␉(12 << 0)␊
5705# define R500_OUT_FMT_C_2_10_10_10␉␉␉(13 << 0)␊
5706/* #define R500_OUT_FMT_RESERVED␉␉␉(14 << 0) */␊
5707# define R500_OUT_FMT_UNUSED␉␉␉␉(15 << 0)␊
5708# define R500_OUT_FMT_C_16_FP␉␉␉␉(16 << 0)␊
5709# define R500_OUT_FMT_C2_16_FP␉␉␉(17 << 0)␊
5710# define R500_OUT_FMT_C4_16_FP␉␉␉(18 << 0)␊
5711# define R500_OUT_FMT_C_32_FP␉␉␉␉(19 << 0)␊
5712# define R500_OUT_FMT_C2_32_FP␉␉␉(20 << 0)␊
5713# define R500_OUT_FMT_C4_32_FP␉␉␉(21 << 0)␊
5714# define R500_C0_SEL_A␉␉␉␉(0 << 8)␊
5715# define R500_C0_SEL_R␉␉␉␉(1 << 8)␊
5716# define R500_C0_SEL_G␉␉␉␉(2 << 8)␊
5717# define R500_C0_SEL_B␉␉␉␉(3 << 8)␊
5718# define R500_C1_SEL_A␉␉␉␉(0 << 10)␊
5719# define R500_C1_SEL_R␉␉␉␉(1 << 10)␊
5720# define R500_C1_SEL_G␉␉␉␉(2 << 10)␊
5721# define R500_C1_SEL_B␉␉␉␉(3 << 10)␊
5722# define R500_C2_SEL_A␉␉␉␉(0 << 12)␊
5723# define R500_C2_SEL_R␉␉␉␉(1 << 12)␊
5724# define R500_C2_SEL_G␉␉␉␉(2 << 12)␊
5725# define R500_C2_SEL_B␉␉␉␉(3 << 12)␊
5726# define R500_C3_SEL_A␉␉␉␉(0 << 14)␊
5727# define R500_C3_SEL_R␉␉␉␉(1 << 14)␊
5728# define R500_C3_SEL_G␉␉␉␉(2 << 14)␊
5729# define R500_C3_SEL_B␉␉␉␉(3 << 14)␊
5730# define R500_OUT_SIGN(x)␉␉␉␉((x) << 16)␊
5731# define R500_ROUND_ADJ␉␉␉␉(1 << 20)␊
5732#define R500_US_PIXSIZE␉␉␉␉␉0x4604␊
5733# define R500_PIX_SIZE(x)␉␉␉␉(x)␊
5734#define R500_US_TEX_ADDR_0␉␉␉␉0x9800␊
5735# define R500_TEX_SRC_ADDR(x)␉␉␉␉((x) << 0)␊
5736# define R500_TEX_SRC_ADDR_REL␉␉␉(1 << 7)␊
5737# define R500_TEX_SRC_S_SWIZ_R␉␉␉(0 << 8)␊
5738# define R500_TEX_SRC_S_SWIZ_G␉␉␉(1 << 8)␊
5739# define R500_TEX_SRC_S_SWIZ_B␉␉␉(2 << 8)␊
5740# define R500_TEX_SRC_S_SWIZ_A␉␉␉(3 << 8)␊
5741# define R500_TEX_SRC_T_SWIZ_R␉␉␉(0 << 10)␊
5742# define R500_TEX_SRC_T_SWIZ_G␉␉␉(1 << 10)␊
5743# define R500_TEX_SRC_T_SWIZ_B␉␉␉(2 << 10)␊
5744# define R500_TEX_SRC_T_SWIZ_A␉␉␉(3 << 10)␊
5745# define R500_TEX_SRC_R_SWIZ_R␉␉␉(0 << 12)␊
5746# define R500_TEX_SRC_R_SWIZ_G␉␉␉(1 << 12)␊
5747# define R500_TEX_SRC_R_SWIZ_B␉␉␉(2 << 12)␊
5748# define R500_TEX_SRC_R_SWIZ_A␉␉␉(3 << 12)␊
5749# define R500_TEX_SRC_Q_SWIZ_R␉␉␉(0 << 14)␊
5750# define R500_TEX_SRC_Q_SWIZ_G␉␉␉(1 << 14)␊
5751# define R500_TEX_SRC_Q_SWIZ_B␉␉␉(2 << 14)␊
5752# define R500_TEX_SRC_Q_SWIZ_A␉␉␉(3 << 14)␊
5753# define R500_TEX_DST_ADDR(x)␉␉␉␉((x) << 16)␊
5754# define R500_TEX_DST_ADDR_REL␉␉␉(1 << 23)␊
5755# define R500_TEX_DST_R_SWIZ_R␉␉␉(0 << 24)␊
5756# define R500_TEX_DST_R_SWIZ_G␉␉␉(1 << 24)␊
5757# define R500_TEX_DST_R_SWIZ_B␉␉␉(2 << 24)␊
5758# define R500_TEX_DST_R_SWIZ_A␉␉␉(3 << 24)␊
5759# define R500_TEX_DST_G_SWIZ_R␉␉␉(0 << 26)␊
5760# define R500_TEX_DST_G_SWIZ_G␉␉␉(1 << 26)␊
5761# define R500_TEX_DST_G_SWIZ_B␉␉␉(2 << 26)␊
5762# define R500_TEX_DST_G_SWIZ_A␉␉␉(3 << 26)␊
5763# define R500_TEX_DST_B_SWIZ_R␉␉␉(0 << 28)␊
5764# define R500_TEX_DST_B_SWIZ_G␉␉␉(1 << 28)␊
5765# define R500_TEX_DST_B_SWIZ_B␉␉␉(2 << 28)␊
5766# define R500_TEX_DST_B_SWIZ_A␉␉␉(3 << 28)␊
5767# define R500_TEX_DST_A_SWIZ_R␉␉␉(0 << 30)␊
5768# define R500_TEX_DST_A_SWIZ_G␉␉␉(1 << 30)␊
5769# define R500_TEX_DST_A_SWIZ_B␉␉␉(2 << 30)␊
5770# define R500_TEX_DST_A_SWIZ_A␉␉␉(3 << 30)␊
5771#define R500_US_TEX_ADDR_DXDY_0␉␉␉␉0xa000␊
5772# define R500_DX_ADDR(x)␉␉␉␉((x) << 0)␊
5773# define R500_DX_ADDR_REL␉␉␉␉(1 << 7)␊
5774# define R500_DX_S_SWIZ_R␉␉␉␉(0 << 8)␊
5775# define R500_DX_S_SWIZ_G␉␉␉␉(1 << 8)␊
5776# define R500_DX_S_SWIZ_B␉␉␉␉(2 << 8)␊
5777# define R500_DX_S_SWIZ_A␉␉␉␉(3 << 8)␊
5778# define R500_DX_T_SWIZ_R␉␉␉␉(0 << 10)␊
5779# define R500_DX_T_SWIZ_G␉␉␉␉(1 << 10)␊
5780# define R500_DX_T_SWIZ_B␉␉␉␉(2 << 10)␊
5781# define R500_DX_T_SWIZ_A␉␉␉␉(3 << 10)␊
5782# define R500_DX_R_SWIZ_R␉␉␉␉(0 << 12)␊
5783# define R500_DX_R_SWIZ_G␉␉␉␉(1 << 12)␊
5784# define R500_DX_R_SWIZ_B␉␉␉␉(2 << 12)␊
5785# define R500_DX_R_SWIZ_A␉␉␉␉(3 << 12)␊
5786# define R500_DX_Q_SWIZ_R␉␉␉␉(0 << 14)␊
5787# define R500_DX_Q_SWIZ_G␉␉␉␉(1 << 14)␊
5788# define R500_DX_Q_SWIZ_B␉␉␉␉(2 << 14)␊
5789# define R500_DX_Q_SWIZ_A␉␉␉␉(3 << 14)␊
5790# define R500_DY_ADDR(x)␉␉␉␉((x) << 16)␊
5791# define R500_DY_ADDR_REL␉␉␉␉(1 << 17)␊
5792# define R500_DY_S_SWIZ_R␉␉␉␉(0 << 24)␊
5793# define R500_DY_S_SWIZ_G␉␉␉␉(1 << 24)␊
5794# define R500_DY_S_SWIZ_B␉␉␉␉(2 << 24)␊
5795# define R500_DY_S_SWIZ_A␉␉␉␉(3 << 24)␊
5796# define R500_DY_T_SWIZ_R␉␉␉␉(0 << 26)␊
5797# define R500_DY_T_SWIZ_G␉␉␉␉(1 << 26)␊
5798# define R500_DY_T_SWIZ_B␉␉␉␉(2 << 26)␊
5799# define R500_DY_T_SWIZ_A␉␉␉␉(3 << 26)␊
5800# define R500_DY_R_SWIZ_R␉␉␉␉(0 << 28)␊
5801# define R500_DY_R_SWIZ_G␉␉␉␉(1 << 28)␊
5802# define R500_DY_R_SWIZ_B␉␉␉␉(2 << 28)␊
5803# define R500_DY_R_SWIZ_A␉␉␉␉(3 << 28)␊
5804# define R500_DY_Q_SWIZ_R␉␉␉␉(0 << 30)␊
5805# define R500_DY_Q_SWIZ_G␉␉␉␉(1 << 30)␊
5806# define R500_DY_Q_SWIZ_B␉␉␉␉(2 << 30)␊
5807# define R500_DY_Q_SWIZ_A␉␉␉␉(3 << 30)␊
5808#define R500_US_TEX_INST_0␉␉␉␉0x9000␊
5809# define R500_TEX_ID(x)␉␉␉␉((x) << 16)␊
5810# define R500_TEX_INST_NOP␉␉␉␉(0 << 22)␊
5811# define R500_TEX_INST_LD␉␉␉␉(1 << 22)␊
5812# define R500_TEX_INST_TEXKILL␉␉␉(2 << 22)␊
5813# define R500_TEX_INST_PROJ␉␉␉␉(3 << 22)␊
5814# define R500_TEX_INST_LODBIAS␉␉␉(4 << 22)␊
5815# define R500_TEX_INST_LOD␉␉␉␉(5 << 22)␊
5816# define R500_TEX_INST_DXDY␉␉␉␉(6 << 22)␊
5817# define R500_TEX_SEM_ACQUIRE␉␉␉␉(1 << 25)␊
5818# define R500_TEX_IGNORE_UNCOVERED␉␉␉(1 << 26)␊
5819# define R500_TEX_UNSCALED␉␉␉␉(1 << 27)␊
5820#define R500_US_W_FMT␉␉␉␉␉0x46b4␊
5821# define R500_W_FMT_W0␉␉␉␉(0 << 0)␊
5822# define R500_W_FMT_W24␉␉␉␉(1 << 0)␊
5823# define R500_W_FMT_W24FP␉␉␉␉(2 << 0)␊
5824# define R500_W_SRC_US␉␉␉␉(0 << 2)␊
5825# define R500_W_SRC_RAS␉␉␉␉(1 << 2)␊
5826␊
5827#define R500_RS_INST_0␉␉␉␉␉0x4320␊
5828#define R500_RS_INST_1␉␉␉␉␉0x4324␊
5829# define R500_RS_INST_TEX_ID_SHIFT␉␉␉0␊
5830# define R500_RS_INST_TEX_CN_WRITE␉␉␉(1 << 4)␊
5831# define R500_RS_INST_TEX_ADDR_SHIFT␉␉␉5␊
5832# define R500_RS_INST_COL_ID_SHIFT␉␉␉12␊
5833# define R500_RS_INST_COL_CN_NO_WRITE␉␉␉(0 << 16)␊
5834# define R500_RS_INST_COL_CN_WRITE␉␉␉(1 << 16)␊
5835# define R500_RS_INST_COL_CN_WRITE_FBUFFER␉␉(2 << 16)␊
5836# define R500_RS_INST_COL_CN_WRITE_BACKFACE␉␉(3 << 16)␊
5837# define R500_RS_INST_COL_COL_ADDR_SHIFT␉␉18␊
5838# define R500_RS_INST_TEX_ADJ␉␉␉␉(1 << 25)␊
5839# define R500_RS_INST_W_CN␉␉␉␉(1 << 26)␊
5840␊
5841#define R500_US_FC_CTRL␉␉␉␉␉0x4624␊
5842#define R500_US_CODE_ADDR␉␉␉␉0x4630␊
5843#define R500_US_CODE_RANGE ␉␉␉␉0x4634␊
5844#define R500_US_CODE_OFFSET ␉␉␉␉0x4638␊
5845␊
5846#define R500_RS_IP_0␉␉␉␉␉0x4074␊
5847#define R500_RS_IP_1␉␉␉␉␉0x4078␊
5848# define R500_RS_IP_PTR_K0␉␉␉␉62␊
5849# define R500_RS_IP_PTR_K1 ␉␉␉␉63␊
5850# define R500_RS_IP_TEX_PTR_S_SHIFT ␉␉␉0␊
5851# define R500_RS_IP_TEX_PTR_T_SHIFT ␉␉␉6␊
5852# define R500_RS_IP_TEX_PTR_R_SHIFT ␉␉␉12␊
5853# define R500_RS_IP_TEX_PTR_Q_SHIFT ␉␉␉18␊
5854# define R500_RS_IP_COL_PTR_SHIFT ␉␉␉24␊
5855# define R500_RS_IP_COL_FMT_SHIFT ␉␉␉27␊
5856# define R500_RS_IP_COL_FMT_RGBA␉␉␉(0 << 27)␊
5857# define R500_RS_IP_OFFSET_EN ␉␉␉(1 << 31)␊
5858␊
5859#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */␊
5860␊
5861/* r6xx/r7xx stuff */␊
5862#define R600_GRBM_STATUS ␉ 0x8010␊
5863# define R600_CMDFIFO_AVAIL_MASK 0x1f␊
5864# define R700_CMDFIFO_AVAIL_MASK 0xf␊
5865# define R600_GUI_ACTIVE (1 << 31)␊
5866␊
5867#define R600_GRBM_SOFT_RESET 0x8020␊
5868# define R600_SOFT_RESET_CP (1 << 0)␊
5869␊
5870#define R600_WAIT_UNTIL 0x8040␊
5871␊
5872#define R600_CP_ME_CNTL 0x86d8␊
5873# define R600_CP_ME_HALT (1 << 28)␊
5874␊
5875#define R600_CP_RB_BASE 0xc100␊
5876#define R600_CP_RB_CNTL 0xc104␊
5877# define R600_RB_NO_UPDATE (1 << 27)␊
5878# define R600_RB_RPTR_WR_ENA (1 << 31)␊
5879#define R600_CP_RB_RPTR_WR 0xc108␊
5880#define R600_CP_RB_RPTR_ADDR 0xc10c␊
5881#define R600_CP_RB_RPTR_ADDR_HI 0xc110␊
5882#define R600_CP_RB_WPTR 0xc114␊
5883#define R600_CP_RB_WPTR_ADDR 0xc118␊
5884#define R600_CP_RB_WPTR_ADDR_HI 0xc11c␊
5885␊
5886#define R600_CP_RB_RPTR 0x8700␊
5887#define R600_CP_RB_WPTR_DELAY 0x8704␊
5888␊
5889#endif␊
5890

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