Chameleon

Chameleon Svn Source Tree

Root/branches/ErmaC/MainTrunkPatch/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉␉value->word = 0;␊
37␉␉␉␉␉␉break;␊
38␉␉␉␉␉default:␊
39␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
40␉␉␉␉}␊
41␉␉␉}␊
42␉␉␉␉break;␊
43␊
44␉␉␉default:␊
45␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
46␉␉}␊
47␉}␊
48␉else␊
49␉{␊
50␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
51␉}␊
52␊
53␉return true;␊
54}␊
55␊
56bool getProcessorInformationMaximumClock(returnType *value)␊
57{␊
58␉value->word = Platform.CPU.CPUFrequency/1000000;␊
59␉return true;␊
60}␊
61␊
62bool getSMBOemProcessorBusSpeed(returnType *value)␊
63{␊
64␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
65␉{␉␉␊
66␉␉switch (Platform.CPU.Family) ␊
67␉␉{␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model)␊
71␉␉␉␉{␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
80␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_DALES:␊
82␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
83␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
84␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
86␉␉␉␉␉{␊
87␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
88␉␉␉␉␉␉int nhm_bus = 0x3F;␊
89␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
90␉␉␉␉␉␉unsigned long did, vid;␊
91␉␉␉␉␉␉int i;␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉// Nehalem supports Scrubbing␊
94␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
95␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
96␉␉␉␉␉␉{␊
97␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
98␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
99␉␉␉␉␉␉␉vid &= 0xFFFF;␊
100␉␉␉␉␉␉␉did &= 0xFF00;␊
101␉␉␉␉␉␉␉␊
102␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
103␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
104␉␉␉␉␉␉}␊
105␉␉␉␉␉␉␊
106␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
107␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
108␉␉␉␉␉␉qpimult &= 0x7F;␊
109␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
110␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
111␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
112␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
113␉␉␉␉␉␉{␊
114␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
115␉␉␉␉␉␉}␊
116␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
117␉␉␉␉␉␉value->word = qpibusspeed;␊
118␉␉␉␉␉␉return true;␊
119␉␉␉␉␉}␊
120␉␉␉␉}␊
121␉␉␉}␊
122␉␉}␊
123␉}␊
124␉return false;␊
125}␊
126␊
127uint16_t simpleGetSMBOemProcessorType(void)␊
128{␊
129␉if (Platform.CPU.NoCores >= 4) ␊
130␉{␊
131␉␉return 0x0501;␉// Quad-Core Xeon␊
132␉}␊
133␉else if (Platform.CPU.NoCores == 1) ␊
134␉{␊
135␉␉return 0x0201;␉// Core Solo␊
136␉};␊
137␉␊
138␉return 0x0301;␉␉// Core 2 Duo␊
139}␊
140␊
141bool getSMBOemProcessorType(returnType *value)␊
142{␊
143␉static bool done = false;␉␉␊
144␉␉␊
145␉value->word = simpleGetSMBOemProcessorType();␊
146␊
147␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
148␉{␊
149␉␉if (!done)␊
150␉␉{␊
151␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
152␉␉␉done = true;␊
153␉␉}␊
154␊
155␉␉switch (Platform.CPU.Family) ␊
156␉␉{␊
157␉␉␉case 0x06:␊
158␉␉␉{␊
159␉␉␉␉switch (Platform.CPU.Model)␊
160␉␉␉␉{␊
161␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
162␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
163␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
164␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
165␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
166␉␉␉␉␉␉return true;␊
167␊
168␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
169␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
170␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
171␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
172␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
173␉␉␉␉␉␉{␊
174␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
175␉␉␉␉␉␉}␊
176␉␉␉␉␉␉else␊
177␉␉␉␉␉␉{␊
178␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
179␉␉␉␉␉␉}␊
180␉␉␉␉␉␉return true;␊
181␊
182␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
183␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
184␉␉␉␉␉␉{␊
185␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
186␉␉␉␉␉␉}␊
187␉␉␉␉␉␉else␊
188␉␉␉␉␉␉{␊
189␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
190␉␉␉␉␉␉␉{␊
191␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
192␉␉␉␉␉␉␉}␊
193␉␉␉␉␉␉␉else␊
194␉␉␉␉␉␉␉{␊
195␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
196␉␉␉␉␉␉␉}␊
197␉␉␉␉␉␉}␊
198␉␉␉␉␉␉return true;␊
199␊
200␉␉␉␉␉case CPU_MODEL_DALES:␊
201␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
202␉␉␉␉␉␉{␊
203␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
204␉␉␉␉␉␉}␊
205␉␉␉␉␉␉else␊
206␉␉␉␉␉␉{␊
207␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
208␉␉␉␉␉␉}␊
209␉␉␉␉␉␉return true;␊
210␊
211␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
212␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
213␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
214␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
215␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
216␉␉␉␉␉␉else␊
217␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
218␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
219␉␉␉␉␉␉␉else␊
220␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
221␉␉␉␉␉␉return true;␊
222␉␉␉␉}␊
223␉␉␉}␊
224␉␉}␊
225␉}␊
226␉␊
227␉return false;␊
228}␊
229␊
230bool getSMBMemoryDeviceMemoryType(returnType *value)␊
231{␊
232␉static int idx = -1;␊
233␉int␉map;␊
234␊
235␉idx++;␊
236␉if (idx < MAX_RAM_SLOTS)␊
237␉{␊
238␉␉map = Platform.DMI.DIMM[idx];␊
239␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
240␉␉{␊
241␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
242␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
243␉␉␉return true;␊
244␉␉}␊
245␉}␊
246␉␊
247␉return false;␊
248//␉value->byte = SMB_MEM_TYPE_DDR2;␊
249//␉return true;␊
250}␊
251␊
252bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
253{␊
254 value->word = 0xFFFF;␊
255 return true;␊
256}␊
257␊
258bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
259{␊
260␉static int idx = -1;␊
261␉int␉map;␊
262␊
263␉idx++;␊
264␉if (idx < MAX_RAM_SLOTS)␊
265␉{␊
266␉␉map = Platform.DMI.DIMM[idx];␊
267␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
268␉␉{␊
269␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
270␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
271␉␉␉return true;␊
272␉␉}␊
273␉}␊
274␊
275␉return false;␊
276//␉value->dword = 800;␊
277//␉return true;␊
278}␊
279␊
280bool getSMBMemoryDeviceManufacturer(returnType *value)␊
281{␊
282␉static int idx = -1;␊
283␉int␉map;␊
284␊
285␉idx++;␊
286␉if (idx < MAX_RAM_SLOTS)␊
287␉{␊
288␉␉map = Platform.DMI.DIMM[idx];␊
289␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
290␉␉{␊
291␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
292␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
293␉␉␉return true;␊
294␉␉}␊
295␉}␊
296␊
297␉if (!bootInfo->memDetect)␊
298␉{␊
299␉␉return false;␊
300␉}␊
301␉value->string = NOT_AVAILABLE;␊
302␉return true;␊
303}␊
304␉␊
305bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
306{␊
307␉static int idx = -1;␊
308␉int␉map;␊
309␊
310␉idx++;␊
311␊
312 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
313␊
314␉if (idx < MAX_RAM_SLOTS)␊
315␉{␊
316␉␉map = Platform.DMI.DIMM[idx];␊
317␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
318␉␉{␊
319␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
320␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
321␉␉␉return true;␊
322␉␉}␊
323␉}␊
324␊
325␉if (!bootInfo->memDetect)␊
326␉{␊
327␉␉return false;␊
328␉}␊
329␉value->string = NOT_AVAILABLE;␊
330␉return true;␊
331}␊
332␊
333bool getSMBMemoryDevicePartNumber(returnType *value)␊
334{␊
335␉static int idx = -1;␊
336␉int␉map;␊
337␊
338␉idx++;␊
339␉if (idx < MAX_RAM_SLOTS)␊
340␉{␊
341␉␉map = Platform.DMI.DIMM[idx];␊
342␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
343␉␉{␊
344␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
345␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
346␉␉␉return true;␊
347␉␉}␊
348␉}␊
349␊
350␉if (!bootInfo->memDetect)␊
351␉{␊
352␉␉return false;␊
353␉}␊
354␉value->string = NOT_AVAILABLE;␊
355␉return true;␊
356}␊
357␊
358␊
359// getting smbios addr with fast compare ops, late checksum testing ...␊
360#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
361static const char * const SMTAG = "_SM_";␊
362static const char* const DMITAG = "_DMI_";␊
363␊
364SMBEntryPoint *getAddressOfSmbiosTable(void)␊
365{␊
366␉SMBEntryPoint␉*smbios;␊
367␉/* ␊
368␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
369␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
370␉ */␊
371␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
372␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
373␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
374␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
375␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
376␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
377␉ {␊
378␉␉␉return smbios;␊
379␉ }␊
380␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
381␉}␊
382␉printf("ERROR: Unable to find SMBIOS!\n");␊
383␉pause();␊
384␉return NULL;␊
385}␊
386␊
387

Archive Download this file

Revision: 2148