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Root/branches/blackosx/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "saio_internal.h"␊
14#include "bootstruct.h"␊
15#include "memvendors.h"␊
16␊
17#ifndef DEBUG_SPD␊
18#define DEBUG_SPD 0␊
19#endif␊
20␊
21#if DEBUG_SPD␊
22#define DBG(x...)␉printf(x)␊
23#else␊
24#define DBG(x...)␊
25#endif␊
26␊
27static const char *spd_memory_types[] =␊
28{␊
29␉"RAM", /* 00h Undefined */␊
30␉"FPM", /* 01h FPM */␊
31␉"EDO", /* 02h EDO */␊
32␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
33␉"SDRAM", /* 04h SDRAM */␊
34␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
35␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
36␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
37␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
38␉"",␉␉␉␉/* 09h Undefined */␊
39␉"",␉␉␉␉/* 0Ah Undefined */␊
40␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
41};␊
42␊
43#define UNKNOWN_MEM_TYPE 2␊
44static uint8_t spd_mem_to_smbios[] =␊
45{␊
46␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
47␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
48␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
49␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
50␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
51␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
52␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
53␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
54␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
55␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
56␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
57␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
58};␊
59#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
60␊
61#define rdtsc(low,high) \␊
62__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
63␊
64#define SMBHSTSTS 0␊
65#define SMBHSTCNT 2␊
66#define SMBHSTCMD 3␊
67#define SMBHSTADD 4␊
68#define SMBHSTDAT 5␊
69#define SBMBLKDAT 7␊
70␊
71/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
72unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
73{␊
74 int l1, h1, l2, h2;␊
75 unsigned long long t;␊
76␉␊
77 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
78 outb(base + SMBHSTDAT, 0xff);␊
79␉␊
80 while( inb(base + SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
81␉␊
82 outb(base + SMBHSTCMD, cmd);␊
83 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
84 outb(base + SMBHSTCNT, 0x48 );␊
85␉␊
86 rdtsc(l1, h1);␊
87␉␊
88 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
89␉{␉␊
90␉␉rdtsc(l2, h2);␊
91␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
92␉␉if (t > 5)␊
93␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
94 }␊
95 return inb(base + SMBHSTDAT);␊
96}␊
97␊
98/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
99#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
100␊
101int spd_indexes[] = {␊
102␉SPD_MEMORY_TYPE,␊
103␉SPD_DDR3_MEMORY_BANK,␊
104␉SPD_DDR3_MEMORY_CODE,␊
105␉SPD_NUM_ROWS,␊
106␉SPD_NUM_COLUMNS,␊
107␉SPD_NUM_DIMM_BANKS,␊
108␉SPD_NUM_BANKS_PER_SDRAM,␊
109␉4,7,8,9,12,64, /* TODO: give names to these values */␊
110␉95,96,97,98, 122,123,124,125 /* UIS */␊
111};␊
112#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
113␊
114/** Read from spd *used* values only*/␊
115static void init_spd(char * spd, uint32_t base, int slot)␊
116{␊
117␉int i;␊
118␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
119␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
120␉}␊
121}␊
122␊
123/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
124 have different formats, always return a valid ptr.*/␊
125const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
126{␊
127 uint8_t bank = 0;␊
128 uint8_t code = 0;␊
129 int i = 0;␊
130 char * spd = slot->spd;␊
131␊
132 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
133 bank = spd[SPD_DDR3_MEMORY_BANK];␊
134 code = spd[SPD_DDR3_MEMORY_CODE];␊
135 for (i=0; i < VEN_MAP_SIZE; i++)␊
136 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
137 return vendorMap[i].name;␊
138 }␊
139 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
140 if(spd[64]==0x7f) {␊
141 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
142␉␉␉ bank++;␊
143␉␉␉ READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
144␉␉␉}␊
145␉␉␉READ_SPD(spd, base, slot_num,i);␊
146 code = spd[i];␊
147 } else {␊
148 code = spd[64]; ␊
149 bank = 0;␊
150 }␊
151 for (i=0; i < VEN_MAP_SIZE; i++)␊
152 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
153 return vendorMap[i].name;␊
154 }␊
155 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
156 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
157 return "Unifosa";␊
158 return "NoName";␊
159}␊
160␊
161/** Get Default Memory Module Speed (no overclocking handled) */␊
162int getDDRspeedMhz(const char * spd)␊
163{␊
164 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
165 switch(spd[12]) {␊
166 case 0x0f:␊
167 return 1066;␊
168 case 0x0c:␊
169 return 1333;␊
170 case 0x0a:␊
171 return 1600;␊
172 case 0x14:␊
173 default:␊
174 return 800;␊
175 }␊
176 } ␊
177 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
178 switch(spd[9]) {␊
179 case 0x50:␊
180 return 400;␊
181 case 0x3d:␊
182 return 533;␊
183 case 0x30:␊
184 return 667;␊
185 case 0x25:␊
186 default:␊
187 return 800;␊
188 }␊
189 }␊
190 return 800; // default freq for unknown types␊
191}␊
192␊
193#define UIS(a) ((uint32_t)spd[a])␊
194␊
195/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
196const char *getDDRSerial(const char* spd)␊
197{␊
198 static char asciiSerial[16];␊
199 static uint8_t serialnum=0;␊
200 uint32_t ret=0;␊
201␊
202 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {// DDR3␊
203 ret = UIS(122) | (UIS(123)<<8) | (UIS(124)<<16) | ((UIS(125)&0x7f)<<24);␊
204 }␊
205 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) { // DDR2 or DDR␊
206 ret = UIS(95) | (UIS(96)<<8) | (UIS(97)<<16) | ((UIS(98)&0x7f)<<24);␊
207 }␊
208␊
209 if (!ret) sprintf(asciiSerial, "10000000%d", serialnum++); ␊
210 else sprintf(asciiSerial, "%X", ret); ␊
211␊
212␉return strdup(asciiSerial);␊
213}␊
214␊
215/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
216const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
217{␊
218␉static char asciiPartNo[32];␊
219␉int i, start=0, index = 0;␊
220␊
221 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
222␉␉start = 128;␊
223␉}␊
224 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
225␉␉start = 73;␊
226␉}␊
227␉␊
228 // Check that the spd part name is zero terminated and that it is ascii:␊
229␉bzero(asciiPartNo, 32);␊
230␉char c;␊
231␉for (i=start; i<start+32; i++) {␊
232␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
233␉␉c = spd[i];␊
234␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
235␉␉␉asciiPartNo[index++] = c;␊
236␉␉else if (!isascii(c))␊
237␉␉␉break;␊
238␉}␊
239␉␊
240␉return strdup(asciiPartNo);␊
241 return NULL;␊
242}␊
243␊
244int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
245␊
246␊
247/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
248static void read_smb_intel(pci_dt_t *smbus_dev)␊
249{ ␊
250 int i, speed;␊
251 uint8_t spd_size, spd_type;␊
252 uint32_t base;␊
253 bool dump = false;␊
254 RamSlotInfo_t* slot;␊
255␊
256 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
257 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
258␊
259 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
260 bool fullBanks = // needed at least for laptops␊
261 Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;␊
262 // Search MAX_RAM_SLOTS slots␊
263␉char spdbuf[256];␊
264␊
265 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
266 slot = &Platform.RAM.DIMM[i];␊
267 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
268 // Check spd is present␊
269 if (spd_size && (spd_size != 0xff) ) {␊
270␊
271␉␉␉slot->spd = spdbuf;␊
272 slot->InUse = true;␊
273␊
274 bzero(slot->spd, spd_size);␊
275 ␊
276 // Copy spd data into buffer␊
277 ␊
278␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
279 init_spd(slot->spd, base, i);␊
280␉␉␉␊
281 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
282 case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
283 ␊
284 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
285 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
286 break;␊
287 ␊
288 case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
289 ␊
290 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
291 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
292 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
293 ␊
294 break;␊
295 }␊
296 ␊
297 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
298 slot->Type = spd_mem_to_smbios[spd_type];␊
299 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
300 slot->Vendor = getVendorName(slot, base, i);␊
301 slot->SerialNo = getDDRSerial(slot->spd);␊
302␊
303 // determine spd speed␊
304 speed = getDDRspeedMhz(slot->spd);␊
305 if (slot->Frequency<speed) slot->Frequency = speed; // should test the mem controller to get potential overclocking info ? ␊
306␉␉␉printf("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
307 i, ␊
308 (int)slot->Type,␊
309 slot->ModuleSize, ␊
310 spd_memory_types[spd_type],␊
311 slot->Frequency,␊
312 slot->Vendor,␊
313 slot->PartNo,␊
314 slot->SerialNo); ␊
315␉␉␉if(DEBUG_SPD) {␊
316 dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
317 getc();␊
318 }␊
319 }␊
320␊
321 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
322 Platform.DMI.DIMM[i]= ␊
323 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ? ␊
324 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
325 ␊
326␉␉slot->spd = NULL;␊
327␊
328 } // for␊
329}␊
330␊
331static struct smbus_controllers_t smbus_controllers[] = {␊
332␊
333␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
334␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
335␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
336␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
337␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
338␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
339␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
340␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
341␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
342␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
343␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
344␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
345␊
346};␊
347␊
348// initial call : pci_dt = root_pci_dev;␊
349// find_and_read_smbus_controller(root_pci_dev);␊
350bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
351{␊
352 pci_dt_t␉*current = pci_dt;␊
353 int i;␊
354␊
355 while (current) {␊
356#if 0␊
357 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
358 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
359 current->class_id, current->vendor_id, current->device_id, ␊
360 get_pci_dev_path(current));␊
361#endif␊
362␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
363 {␊
364 if (current->vendor_id == smbus_controllers[i].vendor &&␊
365 current->device_id == smbus_controllers[i].device)␊
366 {␊
367 smbus_controllers[i].read_smb(current); // read smb␊
368 return true;␊
369 } ␊
370 }␊
371 find_and_read_smbus_controller(current->children);␊
372 current = current->next;␊
373 }␊
374 return false; // not found␊
375}␊
376␊
377void scan_spd(PlatformInfo_t *p)␊
378{␊
379␉printf("\n--> Start of mem detect:\n");␊
380 find_and_read_smbus_controller(root_pci_dev);␊
381␉printf("\n<-- End of mem detect.\n");␊
382}␊
383

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