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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␉␉␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE: ␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉␉value->word = 0;␊
37␉␉␉␉␉␉break;␊
38␉␉␉␉␉default:␊
39␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
40␉␉␉␉}␊
41␉␉␉}␊
42␉␉␉␉break;␊
43␉␉␉␉␊
44␉␉␉default:␊
45␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
46␉␉}␊
47␉}␊
48␉else␊
49␉{␊
50␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
51␉}␊
52␊
53␉return true;␊
54}␊
55␊
56bool getProcessorInformationMaximumClock(returnType *value)␊
57{␊
58␉value->word = Platform.CPU.CPUFrequency/1000000;␊
59␉return true;␊
60}␊
61␊
62bool getSMBOemProcessorBusSpeed(returnType *value)␊
63{␊
64␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
65␉{␉␉␊
66␉␉switch (Platform.CPU.Family) ␊
67␉␉{␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model)␊
71␉␉␉␉{␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
80␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_DALES:␊
82␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
83␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
84␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
86␉␉␉␉␉{␊
87␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
88␉␉␉␉␉␉int nhm_bus = 0x3F;␊
89␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
90␉␉␉␉␉␉unsigned long did, vid;␊
91␉␉␉␉␉␉int i;␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉// Nehalem supports Scrubbing␊
94␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
95␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
96␉␉␉␉␉␉{␊
97␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
98␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
99␉␉␉␉␉␉␉vid &= 0xFFFF;␊
100␉␉␉␉␉␉␉did &= 0xFF00;␊
101␉␉␉␉␉␉␉␊
102␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
103␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
104␉␉␉␉␉␉}␊
105␉␉␉␉␉␉␊
106␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
107␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
108␉␉␉␉␉␉qpimult &= 0x7F;␊
109␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
110␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
111␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
112␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
113␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
114␉␉␉␉␉␉value->word = qpibusspeed;␊
115␉␉␉␉␉␉return true;␊
116␉␉␉␉␉}␊
117␉␉␉␉}␊
118␉␉␉}␊
119␉␉}␊
120␉}␊
121␉return false;␊
122}␊
123␊
124uint16_t simpleGetSMBOemProcessorType(void)␊
125{␊
126␉if (Platform.CPU.NoCores >= 4) ␊
127␉{␊
128␉␉return 0x0501;␉// Quad-Core Xeon␊
129␉}␊
130␉else if (Platform.CPU.NoCores == 1) ␊
131␉{␊
132␉␉return 0x0201;␉// Core Solo␊
133␉};␊
134␉␊
135␉return 0x0301;␉␉// Core 2 Duo␊
136}␊
137␊
138bool getSMBOemProcessorType(returnType *value)␊
139{␊
140␉static bool done = false;␉␉␊
141␉␉␊
142␉value->word = simpleGetSMBOemProcessorType();␊
143␊
144␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
145␉{␊
146␉␉if (!done)␊
147␉␉{␊
148␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
149␉␉␉done = true;␊
150␉␉}␊
151␉␉␊
152␉␉switch (Platform.CPU.Family) ␊
153␉␉{␊
154␉␉␉case 0x06:␊
155␉␉␉{␊
156␉␉␉␉switch (Platform.CPU.Model)␊
157␉␉␉␉{␊
158␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
159␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
160␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
161␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
162␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
163␉␉␉␉␉␉return true;␊
164␊
165␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
166␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
167␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
168␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
169␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
170␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
171␉␉␉␉␉␉else␊
172␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
173␉␉␉␉␉␉return true;␊
174␊
175␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
176␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
177␉␉␉␉␉␉␉value->word = 0x0501;// Xeon␊
178␉␉␉␉␉␉else␊
179␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
180␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
181␉␉␉␉␉␉␉else␊
182␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
183␉␉␉␉␉␉return true;␊
184␊
185␉␉␉␉␉case CPU_MODEL_DALES:␊
186␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
187␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
188␉␉␉␉␉␉else␊
189␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
190␉␉␉␉␉␉return true;␊
191␊
192␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
193␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
194␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
195␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
196␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
197␉␉␉␉␉␉else␊
198␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
199␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
200 else␊
201 if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
202 value->word = 0x0601;␉␉// Core i5␊
203 else␊
204 value->word = 0x0701;␉␉// Core i7␊
205 return true;␉␉␉␉}␊
206␉␉␉}␊
207␉␉}␊
208␉}␊
209␉␊
210␉return false;␊
211}␊
212␊
213bool getSMBMemoryDeviceMemoryType(returnType *value)␊
214{␊
215␉static int idx = -1;␊
216␉int␉map;␊
217␊
218␉idx++;␊
219␉if (idx < MAX_RAM_SLOTS)␊
220␉{␊
221␉␉map = Platform.DMI.DIMM[idx];␊
222␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
223␉␉{␊
224␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
225␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
226␉␉␉return true;␊
227␉␉}␊
228␉}␊
229␉␊
230␉return false;␊
231//␉value->byte = SMB_MEM_TYPE_DDR2;␊
232//␉return true;␊
233}␊
234␊
235bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
236{␊
237␉static int idx = -1;␊
238␉int␉map;␊
239␊
240␉idx++;␊
241␉if (idx < MAX_RAM_SLOTS)␊
242␉{␊
243␉␉map = Platform.DMI.DIMM[idx];␊
244␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
245␉␉{␊
246␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
247␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
248␉␉␉return true;␊
249␉␉}␊
250␉}␊
251␊
252␉return false;␊
253//␉value->dword = 800;␊
254//␉return true;␊
255}␊
256␊
257bool getSMBMemoryDeviceManufacturer(returnType *value)␊
258{␊
259␉static int idx = -1;␊
260␉int␉map;␊
261␊
262␉idx++;␊
263␉if (idx < MAX_RAM_SLOTS)␊
264␉{␊
265␉␉map = Platform.DMI.DIMM[idx];␊
266␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
267␉␉{␊
268␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
269␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
270␉␉␉return true;␊
271␉␉}␊
272␉}␊
273␊
274␉if (!bootInfo->memDetect)␊
275␉␉return false;␊
276␉value->string = NOT_AVAILABLE;␊
277␉return true;␊
278}␊
279␉␊
280bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
281{␊
282␉static int idx = -1;␊
283␉int␉map;␊
284␊
285␉idx++;␊
286␊
287 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
288␊
289␉if (idx < MAX_RAM_SLOTS)␊
290␉{␊
291␉␉map = Platform.DMI.DIMM[idx];␊
292␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
293␉␉{␊
294␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
295␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
296␉␉␉return true;␊
297␉␉}␊
298␉}␊
299␊
300␉if (!bootInfo->memDetect)␊
301␉␉return false;␊
302␉value->string = NOT_AVAILABLE;␊
303␉return true;␊
304}␊
305␊
306bool getSMBMemoryDevicePartNumber(returnType *value)␊
307{␊
308␉static int idx = -1;␊
309␉int␉map;␊
310␊
311␉idx++;␊
312␉if (idx < MAX_RAM_SLOTS)␊
313␉{␊
314␉␉map = Platform.DMI.DIMM[idx];␊
315␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
316␉␉{␊
317␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
318␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
319␉␉␉return true;␊
320␉␉}␊
321␉}␊
322␊
323␉if (!bootInfo->memDetect)␊
324␉␉return false;␊
325␉value->string = NOT_AVAILABLE;␊
326␉return true;␊
327}␊
328␊
329␊
330// getting smbios addr with fast compare ops, late checksum testing ...␊
331#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
332static const char * const SMTAG = "_SM_";␊
333static const char* const DMITAG = "_DMI_";␊
334␊
335SMBEntryPoint *getAddressOfSmbiosTable(void)␊
336{␊
337␉SMBEntryPoint␉*smbios;␊
338␉/* ␊
339␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
340␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
341␉ */␊
342␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
343␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
344␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
345␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
346␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
347␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
348␉ {␊
349␉␉␉return smbios;␊
350␉ }␊
351␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
352␉}␊
353␉printf("ERROR: Unable to find SMBIOS!\n");␊
354␉pause();␊
355␉return NULL;␊
356}␊
357␊
358

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