Chameleon

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Root/trunk/i386/libsaio/dram_controllers.c

1/*␊
2 * dram controller access and scan from the pci host controller␊
3 * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊
4 * original source comes from:␊
5 *␊
6 * memtest86␊
7 *␊
8 * Released under version 2 of the Gnu Public License.␊
9 * By Chris Brady, cbrady@sgi.com␊
10 * ----------------------------------------------------␊
11 * MemTest86+ V4.00 Specific code (GPL V2.0)␊
12 * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
13 * http://www.canardpc.com - http://www.memtest.org␊
14 */␊
15␊
16#include "libsaio.h"␊
17#include "bootstruct.h"␊
18#include "pci.h"␊
19#include "platform.h"␊
20#include "dram_controllers.h"␊
21␊
22#ifndef DEBUG_DRAM␊
23#define DEBUG_DRAM 0␊
24#endif␊
25␊
26#if DEBUG_DRAM␊
27#define DBG(x...) printf(x)␊
28#else␊
29#define DBG(x...)␊
30#endif␊
31␊
32/*␊
33 * Initialise memory controller functions␊
34 */␊
35␊
36// Setup P35 Memory Controller␊
37static void setup_p35(pci_dt_t *dram_dev)␊
38{␊
39␉uint32_t dev0;␊
40␉␊
41␉// Activate MMR I/O␊
42␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
43␉if (!(dev0 & 0x1))␊
44␉{␊
45␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
46␉}␊
47}␊
48␊
49int nhm_bus = 0x3F;␊
50␊
51// Setup Nehalem Integrated Memory Controller␊
52static void setup_nhm(pci_dt_t *dram_dev)␊
53{␊
54␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
55␉unsigned long did, vid;␊
56␉int i;␊
57␊
58␉// Nehalem supports Scrubbing␊
59␉// First, locate the PCI bus where the MCH is located␊
60␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
61␉{␊
62␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
63␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
64␉␉vid &= 0xFFFF;␊
65␉␉did &= 0xFF00;␊
66␉␉␊
67␉␉if(vid == 0x8086 && did >= 0x2C00)␊
68␉␉{␊
69␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
70␉␉}␊
71␉}␊
72}␊
73␊
74/*␊
75 * Retrieve memory controller fsb functions␊
76 */␊
77␊
78␊
79// Get i965 Memory Speed␊
80static void get_fsb_i965(pci_dt_t *dram_dev)␊
81{␊
82␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
83␊
84␉long *ptr;␊
85␉␊
86␉// Find Ratio␊
87␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
88␉dev0 &= 0xFFFFC000;␊
89␉ptr = (long*)(dev0 + 0xC00);␊
90␉mch_cfg = *ptr & 0xFFFF;␊
91␉␊
92␉mch_ratio = 100000;␊
93␉␊
94␉switch (mch_cfg & 7)␊
95␉{␊
96␉␉case 0: mch_fsb = 1066; break;␊
97␉␉case 1: mch_fsb = 533; break;␊
98␉␉default: ␊
99␉␉case 2: mch_fsb = 800; break;␊
100␉␉case 3: mch_fsb = 667; break;␉␉␊
101␉␉case 4: mch_fsb = 1333; break;␊
102␉␉case 6: mch_fsb = 1600; break;␉␉␉␉␉␊
103␉}␊
104␉␊
105␉DBG("mch_fsb %d\n", mch_fsb);␊
106␉␊
107␉switch (mch_fsb)␊
108␉{␊
109␉␉case 533:␊
110␉␉switch ((mch_cfg >> 4) & 7)␊
111␉␉{␊
112␉␉␉case 1:␉mch_ratio = 200000; break;␊
113␉␉␉case 2:␉mch_ratio = 250000; break;␊
114␉␉␉case 3:␉mch_ratio = 300000; break;␊
115␉␉}␊
116␉␉break;␊
117␉␉␉␊
118␉␉default:␊
119␉␉case 800:␊
120␉␉switch ((mch_cfg >> 4) & 7)␊
121␉␉{␊
122␉␉␉case 0:␉mch_ratio = 100000; break;␊
123␉␉␉case 1:␉mch_ratio = 125000; break;␊
124␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
125␉␉␉case 3:␉mch_ratio = 200000; break;␊
126␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
127␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
128␉␉}␊
129␉␉break;␊
130␉␉␉␊
131␉␉case 1066:␊
132␉␉switch ((mch_cfg >> 4) & 7)␊
133␉␉{␊
134␉␉␉case 1:␉mch_ratio = 100000; break;␊
135␉␉␉case 2:␉mch_ratio = 125000; break;␊
136␉␉␉case 3:␉mch_ratio = 150000; break;␊
137␉␉␉case 4:␉mch_ratio = 200000; break;␊
138␉␉␉case 5:␉mch_ratio = 250000; break;␊
139␉␉}␊
140␉␉break;␊
141␉␉␉␊
142␉␉case 1333:␊
143␉␉switch ((mch_cfg >> 4) & 7)␊
144␉␉{␊
145␉␉␉case 2:␉mch_ratio = 100000; break;␊
146␉␉␉case 3:␉mch_ratio = 120000; break;␊
147␉␉␉case 4:␉mch_ratio = 160000; break;␊
148␉␉␉case 5:␉mch_ratio = 200000; break;␊
149␉␉}␊
150␉␉break;␊
151␉␉␉␊
152␉␉case 1600:␊
153␉␉switch ((mch_cfg >> 4) & 7)␊
154␉␉{␊
155␉␉␉case 3:␉mch_ratio = 100000; break;␊
156␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
157␉␉␉case 5:␉mch_ratio = 150000; break;␊
158␉␉␉case 6:␉mch_ratio = 200000; break;␊
159␉␉}␊
160␉␉break;␊
161␉}␊
162␉␊
163␉DBG("mch_ratio %d\n", mch_ratio);␊
164␊
165␉// Compute RAM Frequency␊
166␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
167␉␊
168␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
169␊
170}␊
171␊
172// Get i965m Memory Speed␊
173static void get_fsb_im965(pci_dt_t *dram_dev)␊
174{␊
175␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
176␊
177␉long *ptr;␊
178␉␊
179␉// Find Ratio␊
180␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
181␉dev0 &= 0xFFFFC000;␊
182␉ptr = (long*)(dev0 + 0xC00);␊
183␉mch_cfg = *ptr & 0xFFFF;␊
184␉␊
185␉mch_ratio = 100000;␊
186␉␊
187␉switch (mch_cfg & 7)␊
188␉{␊
189␉␉case 1: mch_fsb = 533; break;␊
190␉␉default: ␊
191␉␉case 2:␉mch_fsb = 800; break;␊
192␉␉case 3:␉mch_fsb = 667; break;␉␉␉␉␊
193␉␉case 6:␉mch_fsb = 1066; break;␉␉␉␊
194␉}␊
195␉␊
196␉switch (mch_fsb)␊
197␉{␊
198␉␉case 533:␊
199␉␉␉switch ((mch_cfg >> 4) & 7)␊
200␉␉␉{␊
201␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
202␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
203␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
204␉␉␉}␊
205␉␉␉break;␊
206␉␉␉␊
207␉␉case 667:␊
208␉␉␉switch ((mch_cfg >> 4)& 7)␊
209␉␉␉{␊
210␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
211␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
212␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
213␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
214␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
215␉␉␉}␊
216␉␉␉break;␊
217␉␉␉␊
218␉␉default:␊
219␉␉case 800:␊
220␉␉␉switch ((mch_cfg >> 4) & 7)␊
221␉␉␉{␊
222␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊
223␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
224␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
225␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
226␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
227␉␉␉}␊
228␉␉␉break;␊
229␉␉case 1066:␊
230␉␉␉switch ((mch_cfg >> 4)&7)␊
231␉␉␉{␊
232␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
233␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
234␉␉␉}␊
235␉␉␉␊
236␉}␊
237␉␊
238␉// Compute RAM Frequency␊
239␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
240}␊
241␊
242␊
243// Get iCore7 Memory Speed␊
244static void get_fsb_nhm(pci_dt_t *dram_dev)␊
245{␊
246␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
247␉␊
248␉// Get the clock ratio␊
249␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
250␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
251␉␊
252␉// Compute RAM Frequency␊
253␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
254}␊
255␊
256/*␊
257 * Retrieve memory controller info functions␊
258 */␊
259␊
260// Get i965 Memory Timings␊
261static void get_timings_i965(pci_dt_t *dram_dev)␊
262{ ␊
263␉// Thanks for CDH optis␊
264␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
265␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
266␊
267␉long *ptr;␊
268␉␊
269␉// Read MMR Base Address␊
270␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
271␉dev0 &= 0xFFFFC000;␊
272␉␊
273␉ptr = (long*)(dev0 + 0x260);␊
274␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
275␉␊
276␉ptr = (long*)(dev0 + 0x660);␊
277␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
278␉␊
279␉// If DIMM 0 not populated, check DIMM 1␊
280␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
281␉␊
282␉ptr = (long*)(dev0 + offset + 0x29C);␊
283␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
284␉␊
285␉ptr = (long*)(dev0 + offset + 0x250);␉␊
286␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
287␉␊
288␉ptr = (long*)(dev0 + offset + 0x252);␊
289␉ACT_Register = *ptr & 0xFFFFFFFF;␊
290␉␊
291␉ptr = (long*)(dev0 + offset + 0x258);␊
292␉Read_Register = *ptr & 0xFFFFFFFF;␊
293␉␊
294␉ptr = (long*)(dev0 + offset + 0x244);␊
295␉Misc_Register = *ptr & 0xFFFFFFFF;␊
296␉␊
297␉// 965 Series only support DDR2␊
298␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
299␉␊
300␉// CAS Latency (tCAS)␊
301␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊
302␉␊
303␉// RAS-To-CAS (tRCD)␊
304␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊
305␉␊
306␉// RAS Precharge (tRP)␊
307␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
308␉␊
309␉// RAS Active to precharge (tRAS)␊
310␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊
311␉␊
312␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF))␊
313␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
314␉else␊
315␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
316}␊
317␊
318// Get im965 Memory Timings␊
319static void get_timings_im965(pci_dt_t *dram_dev)␊
320{␊
321␉// Thanks for CDH optis␊
322␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
323␉long *ptr;␊
324␉␊
325␉// Read MMR Base Address␊
326␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
327␉dev0 &= 0xFFFFC000;␊
328␉␊
329␉ptr = (long*)(dev0 + 0x1200);␊
330␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
331␉␊
332␉ptr = (long*)(dev0 + 0x1300);␊
333␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
334␉␊
335␉// If DIMM 0 not populated, check DIMM 1␊
336␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
337␉␊
338␉ptr = (long*)(dev0 + offset + 0x121C);␊
339␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
340␉␊
341␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
342␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
343␉␊
344␉// Series only support DDR2␊
345␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
346␉␊
347␉// CAS Latency (tCAS)␊
348␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊
349␉␊
350␉// RAS-To-CAS (tRCD)␊
351␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊
352␉␊
353␉// RAS Precharge (tRP)␊
354␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊
355␉␊
356␉// RAS Active to precharge (tRAS)␊
357␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊
358␉␊
359␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) ␊
360␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
361␉else␊
362␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
363}␊
364␊
365// Get P35 Memory Timings␊
366static void get_timings_p35(pci_dt_t *dram_dev)␊
367{ ␊
368␉// Thanks for CDH optis␊
369␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
370␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
371␉long *ptr;␊
372␉␊
373␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
374␉//Device_ID &= 0xFFFF;␊
375␉␊
376␉// Now, read MMR Base Address␊
377␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
378␉dev0 &= 0xFFFFC000;␊
379␉␊
380␉ptr = (long*)(dev0 + 0x260);␊
381␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
382␉␊
383␉ptr = (long*)(dev0 + 0x660);␊
384␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
385␉␊
386␉// If DIMM 0 not populated, check DIMM 1␊
387␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
388␉␊
389␉ptr = (long*)(dev0 + offset + 0x265);␊
390␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
391␉␊
392␉ptr = (long*)(dev0 + offset + 0x25D);␉␊
393␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
394␉␊
395␉ptr = (long*)(dev0 + offset + 0x252);␊
396␉ACT_Register = *ptr & 0xFFFFFFFF;␊
397␉␊
398␉ptr = (long*)(dev0 + offset + 0x258);␊
399␉Read_Register = *ptr & 0xFFFFFFFF;␊
400␉␊
401␉ptr = (long*)(dev0 + offset + 0x244);␊
402␉Misc_Register = *ptr & 0xFFFFFFFF;␊
403␉␊
404␉ptr = (long*)(dev0 + offset + 0x1E8);␊
405␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
406␉␊
407␉// On P45, check 1A8␊
408␉if(dram_dev->device_id > 0x2E00) {␊
409␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
410␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
411␉␉Memory_Check >>= 2;␊
412␉␉Memory_Check &= 1;␊
413␉␉Memory_Check = !Memory_Check;␊
414␉} else {␊
415␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
416␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␉␊
417␉}␊
418␉␊
419␉// Determine DDR-II or DDR-III␊
420␉if (Memory_Check & 1)␊
421␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
422␉else␊
423␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
424␊
425␉// CAS Latency (tCAS)␊
426␉if(dram_dev->device_id > 0x2E00)␊
427␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
428␉else␊
429␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
430␊
431␉// RAS-To-CAS (tRCD)␊
432␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊
433␉␊
434␉// RAS Precharge (tRP)␊
435␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
436␉␊
437␉// RAS Active to precharge (tRAS)␊
438␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊
439␉␊
440␉// Channel configuration␊
441␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) ␊
442␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
443␉else␊
444␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
445}␊
446␊
447// Get Nehalem Memory Timings␊
448static void get_timings_nhm(pci_dt_t *dram_dev)␊
449{␊
450␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
451␉int fvc_bn = 4;␊
452␉␊
453␉// Find which channels are populated␊
454␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
455␉mc_control = (mc_control >> 8) & 0x7;␊
456␉␊
457␉// DDR-III␊
458␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
459␉␊
460␉// Get the first valid channel␊
461␉if(mc_control & 1)␊
462␉␉fvc_bn = 4; ␊
463␉else if(mc_control & 2)␊
464␉␉fvc_bn = 5; ␊
465␉else if(mc_control & 7) ␊
466␉␉fvc_bn = 6; ␊
467␊
468␉// Now, detect timings␊
469␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
470␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
471␉␊
472␉// CAS Latency (tCAS)␊
473␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊
474␉␊
475␉// RAS-To-CAS (tRCD)␊
476␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
477␉␊
478␉// RAS Active to precharge (tRAS)␊
479␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
480␉␊
481␉// RAS Precharge (tRP)␊
482␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
483␉␊
484␉// Single , Dual or Triple Channels␊
485␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
486␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
487␉else if (mc_control == 7)␊
488␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊
489␉else␊
490␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
491}␊
492␊
493static struct mem_controller_t dram_controllers[] = {␊
494␊
495␉// Default unknown chipset␊
496␉{ 0, 0, "",␉NULL, NULL, NULL },␊
497␊
498␉// Intel␊
499␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
500␊
501␉{ 0x8086, 0x1A30, "i845",␉NULL, NULL, NULL },␊
502␉␊
503␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
504␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
505␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
506␊
507␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
508␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
509␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
510␊
511␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
512␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
513␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
514␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
515␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
516␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
517␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
518␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
519␊
520␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
521␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
522␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
523␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
524␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
525␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
526␉{ 0x8086, 0x3404, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
527␉{ 0x8086, 0x3405, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
528␉{ 0x8086, 0x3406, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
529␉{ 0x8086, 0x3407, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
530};␊
531␊
532static const char *memory_channel_types[] =␊
533{␊
534␉"Unknown", "Single", "Dual", "Triple"␊
535};␉␉␉␊
536␊
537void scan_dram_controller(pci_dt_t *dram_dev)␊
538{␊
539␉int i;␊
540␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
541␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) ␊
542␉␉␉␉&& (dram_controllers[i].device == dram_dev->device_id))␊
543␉␉{␊
544␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
545␉␉␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel " : "" ,␊
546␉␉␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
547␉␉␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
548␉␉␉␊
549␉␉␉if (dram_controllers[i].initialise != NULL)␊
550␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
551␊
552␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
553␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
554␊
555␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
556␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
557␊
558␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊
559␉␉␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊
560␉␉␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊
561␉␉␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊
562␉␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
563␉␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
564␉␉␉␉␉);␊
565//␉␉␉getchar();␉␉␊
566␉␉}␊
567}␊
568

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