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Root/trunk/i386/libsaio/cpu.c

1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30␉int␉␉attempts = 0;␊
31␉uint64_t latchTime;␊
32␉uint64_t␉saveTime,intermediate;␊
33␉unsigned int timerValue, lastValue;␊
34␉//boolean_t␉int_enabled;␊
35␉/*␊
36␉ * Table of correction factors to account for␊
37␉ *␉ - timer counter quantization errors, and␊
38␉ *␉ - undercounts 0..5␊
39␉ */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45␉uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52␉};␊
53␊
54␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊
55␊
56restart:␊
57␉if (attempts >= 9) // increase to up to 9 attempts.␊
58␉{␊
59␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
60␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61␉}␊
62␉attempts++;␊
63␉enable_PIT2();␉␉// turn on PIT2␊
64␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
65␉latchTime = rdtsc64();␉// get the time stamp to time ␊
66␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69␉get_PIT2(&lastValue);␊
70␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71␉do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74␉␉{␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81␉} while (timerValue > 5);␊
82␉printf("timerValue␉ %d\n",timerValue);␊
83␉printf("intermediate 0x%016llx\n",intermediate);␊
84␉printf("saveTime␉ 0x%016llx\n",saveTime);␊
85 ␊
86␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
88␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89␉intermediate += latchTime;␉␉// add on our save fudge␊
90 ␊
91␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92␉disable_PIT2();␉␉␉// turn off PIT 2␊
93␉␊
94␉//ml_set_interrupts_enabled(int_enabled);␊
95␉return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␉␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1)␊
128␉␉{␊
129␉␉␉continue;␊
130␉␉}␊
131␉␉/* The TSC must increment at LEAST once every millisecond.␊
132␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
133␉␉ * be >= 30. Anything less and the processor is way too slow.␊
134␉␉ */␊
135␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
136␉␉{␊
137␉␉␉continue;␊
138␉␉}␊
139␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
140␉␉if ( (tscEnd - tscStart) < tscDelta )␊
141␉␉{␊
142␉␉␉tscDelta = tscEnd - tscStart;␊
143␉␉}␊
144␉}␊
145␉/* tscDelta is now the least number of TSC ticks the processor made in␊
146␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
147␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
148␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
149␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
150␉ * dividing by the milliseconds, we simply multiply by 1000.␊
151␉ */␊
152␊
153␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
154␉ * that we're going to multiply by 1000 first so we do need at least some␊
155␉ * arithmetic headroom. For now, 32-bit should be enough.␊
156␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
157␉ */␊
158␉if (tscDelta > (1ULL<<32))␊
159␉{␊
160␉␉retval = 0;␊
161␉}␊
162␉else␊
163␉{␊
164␉␉retval = tscDelta * 1000 / 30;␊
165␉}␊
166␉disable_PIT2();␊
167␉return retval;␊
168}␊
169␊
170/*␊
171 * Original comment/code:␊
172 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
173 *␊
174 * Measures the Actual Performance Frequency in Hz (64-bit)␊
175 * (just a naming change, mperf --> aperf )␊
176 */␊
177static uint64_t measure_aperf_frequency(void)␊
178{␊
179␉uint64_t aperfStart;␊
180␉uint64_t aperfEnd;␊
181␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
182␉unsigned long pollCount;␊
183␉uint64_t retval = 0;␊
184␉int i;␊
185␉␊
186␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
187␉ * counter 2. We run this loop 3 times to make sure the cache␊
188␉ * is hot and we take the minimum delta from all of the runs.␊
189␉ * That is to say that we're biased towards measuring the minimum␊
190␉ * number of APERF ticks that occur while waiting for the timer to␊
191␉ * expire.␊
192␉ */␊
193␉for(i = 0; i < 10; ++i)␊
194␉{␊
195␉␉enable_PIT2();␊
196␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
197␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
198␉␉pollCount = poll_PIT2_gate();␊
199␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
200␉␉/* The poll loop must have run at least a few times for accuracy */␊
201␉␉if (pollCount <= 1)␊
202␉␉{␊
203␉␉␉continue;␊
204␉␉}␊
205␉␉/* The TSC must increment at LEAST once every millisecond.␊
206␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
207␉␉ * be >= 30. Anything less and the processor is way too slow.␊
208␉␉ */␊
209␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
210␉␉{␊
211␉␉␉continue;␊
212␉␉}␊
213␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
214␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
215␉␉{␊
216␉␉␉aperfDelta = aperfEnd - aperfStart;␊
217␉␉}␊
218␉}␊
219␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
220␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
221␉ */␊
222␉␊
223␉if (aperfDelta > (1ULL<<32))␊
224␉{␊
225␉␉retval = 0;␊
226␉}␊
227␉else␊
228␉{␊
229␉␉retval = aperfDelta * 1000 / 30;␊
230␉}␊
231␉disable_PIT2();␊
232␉return retval;␊
233}␊
234␊
235/*␊
236 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
237 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
238 *␉ a max multi. (used to calculate the FSB freq.),␊
239 *␉ and a current multi. (used to calculate the CPU freq.)␊
240 * - fsbFrequency = tscFrequency / multi␊
241 * - cpuFrequency = fsbFrequency * multi␊
242 */␊
243void scan_cpu(PlatformInfo_t *p)␊
244{␊
245␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
246␉uint64_t␉msr, flex_ratio;␊
247␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
248␉const char␉*newratio;␊
249␉int␉␉␉len, myfsb;␊
250␉uint8_t␉␉bus_ratio_min;␊
251␉uint32_t␉max_ratio, min_ratio;␊
252␊
253␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
254␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
255␊
256␉/* get cpuid values */␊
257␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
258␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
259␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
260␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
261␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
262␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
263␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊
264␉{␊
265␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
266␉}␊
267␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊
268␉{␊
269␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
270␉}␊
271␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
272␉{␊
273␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
274␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
275␉}␊
276␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
277␉{␊
278␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
279␉}␊
280␊
281#if DEBUG_CPU␊
282␉{␊
283␉␉int␉␉i;␊
284␉␉printf("CPUID Raw Values:\n");␊
285␉␉for (i=0; i<CPUID_MAX; i++)␊
286␉␉{␊
287␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
288␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
289␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
290␉␉}␊
291␉}␊
292#endif␊
293␊
294/*␊
295 EAX (Intel):␊
296 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
297 +--------+----------------+--------+----+----+--------+--------+--------+␊
298 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
299 +--------+----------------+--------+----+----+--------+--------+--------+␊
300␊
301 EAX (AMD):␊
302 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
303 +--------+----------------+--------+----+----+--------+--------+--------+␊
304 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
305 +--------+----------------+--------+----+----+--------+--------+--------+␊
306*/␊
307␊
308␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
309␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
310␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
311␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
312␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
313␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
314␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
315␊
316␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
317␊
318␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
319␉␉p->CPU.Family == 0x06 &&␊
320␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊
321␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
322␉␉)␊
323␉{␊
324␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
325␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊
326␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊
327␉}␊
328␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
329␉{␊
330␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
331␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
332␉}␊
333␉else␊
334␉{␊
335␉␉// Use previous method for Cores and Threads␊
336␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
337␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
338␉}␊
339␊
340␉/* get brand string (if supported) */␊
341␉/* Copyright: from Apple's XNU cpuid.c */␊
342␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
343␉{␊
344␉␉uint32_t␉reg[4];␊
345␉␉char␉␉str[128], *s;␊
346␉␉/*␊
347␉␉ * The brand string 48 bytes (max), guaranteed to␊
348␉␉ * be NULL terminated.␊
349␉␉ */␊
350␉␉do_cpuid(0x80000002, reg);␊
351␉␉bcopy((char *)reg, &str[0], 16);␊
352␉␉do_cpuid(0x80000003, reg);␊
353␉␉bcopy((char *)reg, &str[16], 16);␊
354␉␉do_cpuid(0x80000004, reg);␊
355␉␉bcopy((char *)reg, &str[32], 16);␊
356␉␉for (s = str; *s != '\0'; s++)␊
357␉␉{␊
358␉␉␉if (*s != ' ')␊
359␉␉␉{␊
360␉␉␉␉break;␊
361␉␉␉}␊
362␉␉}␊
363␉␉␊
364␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
365␉␉␊
366␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))␊
367␉␉{␊
368␉␉␉/*␊
369␉␉␉ * This string means we have a firmware-programmable brand string,␊
370␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
371␉␉␉ */␊
372␉␉␉p->CPU.BrandString[0] = '\0';␊
373␉␉}␊
374␉}␊
375␉␊
376␉/* setup features */␊
377␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
378␉{␊
379␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
380␉}␊
381␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
382␉{␊
383␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
384␉}␊
385␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
386␉{␊
387␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
388␉}␊
389␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
390␉{␊
391␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
392␉}␊
393␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
394␉{␊
395␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
396␉}␊
397␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
398␉{␊
399␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
400␉}␊
401␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
402␉{␊
403␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
404␉}␊
405␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
406␉{␊
407␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
408␉}␊
409␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
410␉if (p->CPU.NoThreads > p->CPU.NoCores)␊
411␉{␊
412␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
413␉}␊
414␊
415␉tscFrequency = measure_tsc_frequency();␊
416␉/* if usual method failed */␊
417␉if ( tscFrequency < 1000 )//TEST␊
418␉{␊
419␉␉tscFrequency = timeRDTSC() * 20;␊
420␉}␊
421␉fsbFrequency = 0;␊
422␉cpuFrequency = 0;␊
423␊
424␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
425␉{␊
426␉␉int intelCPU = p->CPU.Model;␊
427␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
428␉␉{␊
429␉␉␉/* Nehalem CPU model */␊
430␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
431␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊
432␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊
433␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
434␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
435␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
436␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
437␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
438␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊
439␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊
440␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
441␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊
442␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊
443␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊
444␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
445␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CRYSTALWELL ))␊
446␉␉␉{␊
447␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
448␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
449␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
450␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
451␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
452␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
453␉␉␉␉if (bitfield(msr, 16, 16))␊
454␉␉␉␉{␊
455␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
456␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
457␉␉␉␉␉ where the cpu multipler can't be changed to␊
458␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
459␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
460␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
461␉␉␉␉␉ causing the system to crash since tscGranularity␊
462␉␉␉␉␉ is inadvertently set to 0.␊
463␉␉␉␉␉ */␊
464␉␉␉␉␉if (flex_ratio == 0)␊
465␉␉␉␉␉{␊
466␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
467␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
468␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
469␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
470␉␉␉␉␉}␊
471␉␉␉␉␉else␊
472␉␉␉␉␉{␊
473␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
474␉␉␉␉␉␉{␊
475␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
476␉␉␉␉␉␉}␊
477␉␉␉␉␉}␊
478␉␉␉␉}␊
479␊
480␉␉␉␉if (bus_ratio_max)␊
481␉␉␉␉{␊
482␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
483␉␉␉␉}␊
484␉␉␉␉//valv: Turbo Ratio Limit␊
485␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
486␉␉␉␉{␊
487␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
488␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
489␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
490␉␉␉␉}␊
491␉␉␉␉else␊
492␉␉␉␉{␊
493␉␉␉␉␉cpuFrequency = tscFrequency;␊
494␉␉␉␉}␊
495␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
496␉␉␉␉{␊
497␉␉␉␉␉max_ratio = atoi(newratio);␊
498␉␉␉␉␉max_ratio = (max_ratio * 10);␊
499␉␉␉␉␉if (len >= 3)␊
500␉␉␉␉␉{␊
501␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
502␉␉␉␉␉}␊
503␊
504␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
505␊
506␉␉␉␉␉// extreme overclockers may love 320 ;)␊
507␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
508␉␉␉␉␉{␊
509␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
510␉␉␉␉␉␉if (len >= 3)␊
511␉␉␉␉␉␉{␊
512␉␉␉␉␉␉␉maxdiv = 1;␊
513␉␉␉␉␉␉}␊
514␉␉␉␉␉␉else␊
515␉␉␉␉␉␉{␊
516␉␉␉␉␉␉␉maxdiv = 0;␊
517␉␉␉␉␉␉}␊
518␉␉␉␉␉}␊
519␉␉␉␉␉else␊
520␉␉␉␉␉{␊
521␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
522␉␉␉␉␉}␊
523␉␉␉␉}␊
524␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
525␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
526␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
527␉␉␉␉p->CPU.MinRatio = min_ratio;␊
528␊
529␉␉␉␉myfsb = fsbFrequency / 1000000;␊
530␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10);␊
531␉␉␉␉currcoef = bus_ratio_max;␊
532␉␉␉}␊
533␉␉␉else␊
534␉␉␉{␊
535␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
536␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
537␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
538␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
539␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
540␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
541␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
542␊
543␉␉␉␉// This will always be model >= 3␊
544␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
545␉␉␉␉{␊
546␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
547␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
548␉␉␉␉}␊
549␉␉␉␉else␊
550␉␉␉␉{␊
551␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
552␉␉␉␉␉/* XXX */␊
553␉␉␉␉␉maxcoef = currcoef;␊
554␉␉␉␉}␊
555␊
556␉␉␉␉if (maxcoef)␊
557␉␉␉␉{␊
558␉␉␉␉␉if (maxdiv)␊
559␉␉␉␉␉{␊
560␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
561␉␉␉␉␉}␊
562␉␉␉␉␉else␊
563␉␉␉␉␉{␊
564␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
565␉␉␉␉␉}␊
566␉␉␉␉␉if (currdiv)␊
567␉␉␉␉␉{␊
568␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
569␉␉␉␉␉}␊
570␉␉␉␉␉else␊
571␉␉␉␉␉{␊
572␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
573␉␉␉␉␉}␊
574␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
575␉␉␉␉}␊
576␉␉␉}␊
577␉␉}␊
578␉␉/* Mobile CPU */␊
579␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
580␉␉{␊
581␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
582␉␉}␊
583␉}␊
584␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
585␉{␊
586␉␉switch(p->CPU.ExtFamily)␊
587␉␉{␊
588␉␉␉case 0x00: /* K8 */␊
589␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
590␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
591␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
592␉␉␉␉break;␊
593␊
594␉␉␉case 0x01: /* K10 */␊
595␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
596␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
597␉␉␉␉// EffFreq: effective frequency interface␊
598␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
599␉␉␉␉{␊
600␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
601␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
602␉␉␉␉␉cpuFrequency = aperf;␊
603␉␉␉␉}␊
604␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
605␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
606␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
607␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
608␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
609␊
610␉␉␉␉break;␊
611␊
612␉␉␉case 0x05: /* K14 */␊
613␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
614␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
615␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
616␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
617␊
618␉␉␉␉break;␊
619␊
620␉␉␉case 0x02: /* K11 */␊
621␉␉␉␉// not implimented␊
622␉␉␉␉break;␊
623␉␉}␊
624␊
625␉␉if (maxcoef)␊
626␉␉{␊
627␉␉␉if (currdiv)␊
628␉␉␉{␊
629␉␉␉␉if (!currcoef)␊
630␉␉␉␉{␊
631␉␉␉␉␉currcoef = maxcoef;␊
632␉␉␉␉}␊
633␊
634␉␉␉␉if (!cpuFrequency)␊
635␉␉␉␉{␊
636␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
637␉␉␉␉}␊
638␉␉␉␉else␊
639␉␉␉␉{␊
640␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
641␉␉␉␉}␊
642␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
643␉␉␉}␊
644␉␉␉else␊
645␉␉␉{␊
646␉␉␉␉if (!cpuFrequency)␊
647␉␉␉␉{␊
648␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
649␉␉␉␉}␊
650␉␉␉␉else ␊
651␉␉␉␉{␊
652␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
653␉␉␉␉}␊
654␉␉␉␉DBG("%d\n", currcoef);␊
655␉␉␉}␊
656␉␉}␊
657␉␉else if (currcoef)␊
658␉␉{␊
659␉␉␉if (currdiv)␊
660␉␉␉{␊
661␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
662␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
663␉␉␉}␊
664␉␉␉else␊
665␉␉␉{␊
666␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
667␉␉␉␉DBG("%d\n", currcoef);␊
668␉␉␉}␊
669␉␉}␊
670␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
671␉}␊
672␉␊
673#if 0␊
674␉if (!fsbFrequency)␊
675␉{␊
676␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
677␉␉cpuFrequency = tscFrequency;␊
678␉␉DBG("0 ! using the default value for FSB !\n");␊
679␉}␊
680#endif␊
681␊
682␉p->CPU.MaxCoef = maxcoef;␊
683␉p->CPU.MaxDiv = maxdiv;␊
684␉p->CPU.CurrCoef = currcoef;␊
685␉p->CPU.CurrDiv = currdiv;␊
686␉p->CPU.TSCFrequency = tscFrequency;␊
687␉p->CPU.FSBFrequency = fsbFrequency;␊
688␉p->CPU.CPUFrequency = cpuFrequency;␊
689␊
690␉// keep formatted with spaces instead of tabs␊
691␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
692 DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
693 DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
694 DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
695 DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
696 DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
697 DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
698 DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
699 DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
700 DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
701#if DEBUG_CPU␊
702␉pause();␊
703#endif␊
704}␊
705

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