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1/*␊
2 * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊
3 */␊
4␊
5#include "libsaio.h"␊
6#include "pci.h"␊
7#include "hpet.h"␊
8␊
9#ifndef DEBUG_HPET␊
10#define DEBUG_HPET 0␊
11#endif␊
12␊
13#if DEBUG_HPET␊
14#define DBG(x...) printf(x)␊
15#else␊
16#define DBG(x...)␊
17#endif␊
18␊
19void force_enable_hpet_intel(pci_dt_t *lpc_dev);␊
20void force_enable_hpet_nvidia(pci_dt_t *lpc_dev);␊
21void force_enable_hpet_via(pci_dt_t *lpc_dev);␊
22␊
23/*␊
24 * Force HPET enabled␊
25 *␊
26 * VIA fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html␊
27 */␊
28␊
29static struct lpc_controller_t lpc_controllers_intel[] = {␊
30␊
31␉// Default unknown chipset␊
32␉{ 0, 0, "" },␊
33␊
34␉// Intel␊
35␉{ 0x8086, 0x24dc, "ICH5" },␊
36␉{ 0x8086, 0x2640, "ICH6" },␊
37␉{ 0x8086, 0x2641, "ICH6M" },␊
38␉{ 0x8086, 0x2670, "631xESB" },␊
39␊
40␉{ 0x8086, 0x27b0, "ICH7 DH" },␊
41␉{ 0x8086, 0x27b8, "ICH7" },␊
42␉{ 0x8086, 0x27b9, "ICH7M" },␊
43␉{ 0x8086, 0x27bd, "ICH7M DH" },␊
44␊
45␉{ 0x8086, 0x27bc, "NM10" },␊
46␊
47␉{ 0x8086, 0x2810, "ICH8R" },␊
48␉{ 0x8086, 0x2811, "ICH8M-E" },␊
49␉{ 0x8086, 0x2812, "ICH8DH" },␊
50␉{ 0x8086, 0x2814, "ICH8DO" },␊
51␉{ 0x8086, 0x2815, "ICH8M" },␊
52␊
53␉{ 0x8086, 0x2912, "ICH9DH" },␊
54␉{ 0x8086, 0x2914, "ICH9DO" },␊
55␉{ 0x8086, 0x2916, "ICH9R" },␊
56␉{ 0x8086, 0x2917, "ICH9M-E" },␊
57␉{ 0x8086, 0x2918, "ICH9" },␊
58␉{ 0x8086, 0x2919, "ICH9M" },␊
59␊
60␉{ 0x8086, 0x3a14, "ICH10DO" },␊
61␉{ 0x8086, 0x3a16, "ICH10R" },␊
62␉{ 0x8086, 0x3a18, "ICH10" },␊
63␉{ 0x8086, 0x3a1a, "ICH10D" },␊
64␉{ 0x8086, 0x3b00, "5 Series" },␊
65 ␉{ 0x8086, 0x3b01, "Mobile 5 Series" },␊
66␉{ 0x8086, 0x3b02, "5 Series" },␊
67␉{ 0x8086, 0x3b09, "Mobile 5 Series" },␊
68␊
69␉{ 0x8086, 0x1c41, "Mobile SFF 6 Series" },␊
70␉{ 0x8086, 0x1c42, "6 Series" },␊
71␉{ 0x8086, 0x1c43, "Mobile 6 Series" },␊
72␉{ 0x8086, 0x1c44, "Z68" },␊
73␉{ 0x8086, 0x1c46, "UM67" },␊
74␉{ 0x8086, 0x1c47, "UM67" },␊
75␉{ 0x8086, 0x1c49, "HM65" },␊
76␉{ 0x8086, 0x1c4a, "H67" },␊
77␉{ 0x8086, 0x1c4b, "HM67" },␊
78␉{ 0x8086, 0x1c4c, "Q65" },␊
79␉{ 0x8086, 0x1c4d, "QS67" },␊
80␉{ 0x8086, 0x1c4e, "Q67" },␊
81␉{ 0x8086, 0x1c4f, "QM67" },␊
82␉{ 0x8086, 0x1c50, "B65" },␊
83␉{ 0x8086, 0x1c52, "C202" },␊
84␉{ 0x8086, 0x1c54, "C204" },␊
85␉{ 0x8086, 0x1c56, "C206" },␊
86␉{ 0x8086, 0x1c5c, "H61" },␊
87␊
88␉{ 0x8086, 0x1c58, "B65" },␊
89␉{ 0x8086, 0x1c59, "HM67" },␊
90␉{ 0x8086, 0x1c5a, "Q67" },␊
91␊
92//␉{ 0x8086, 0x1dc1, "PATSBURG" },␊
93␊
94␉{ 0x8086, 0x1e41, "Mobile C216/7 Series" },␊
95␉{ 0x8086, 0x1e42, "Mobile 7 Series" },␊
96␉{ 0x8086, 0x1e43, "Mobile 7 Series" },␊
97␉{ 0x8086, 0x1e44, "Z77" },␊
98␉{ 0x8086, 0x1e45, "H71" },␊
99␉{ 0x8086, 0x1e46, "Z75" },␊
100␉{ 0x8086, 0x1e47, "Q77" },␊
101␉{ 0x8086, 0x1e48, "Q75" },␊
102␉{ 0x8086, 0x1e49, "B75" },␊
103␉{ 0x8086, 0x1e4a, "H77" },␊
104␉{ 0x8086, 0x1e4b, "B75" },␊
105␊
106␉{ 0x8086, 0x8119, "SCH 8119" },␊
107␊
108};␊
109␊
110static struct lpc_controller_t lpc_controllers_nvidia[] = {␊
111␊
112␉// Default unknown chipset␊
113␉{ 0, 0, "" },␊
114␊
115␉// nVidia␊
116␉{ 0x10de, 0x0aac, "MCP79" },␊
117␉{ 0x10de, 0x0aae, "MCP79" },␊
118␉{ 0x10de, 0x0aaf, "MCP79" },␊
119␉{ 0x10de, 0x0d80, "MCP89" },␊
120␉{ 0x10de, 0x0d81, "MCP89" },␊
121␉{ 0x10de, 0x0d82, "MCP89" },␊
122␉{ 0x10de, 0x0d83, "MCP89" },␊
123␊
124};␊
125␊
126static struct lpc_controller_t lpc_controllers_via[] = {␊
127␉// Default unknown chipset␊
128␉{ 0, 0, "" },␊
129␊
130␉{ 0x1106, 0x3372, "VT8237S" },␊
131};␊
132␊
133␊
134void force_enable_hpet(pci_dt_t *lpc_dev)␊
135{␊
136␉switch(lpc_dev->vendor_id)␊
137␉{␊
138␉␉case 0x8086:␊
139␉␉␉force_enable_hpet_intel(lpc_dev);␊
140␉␉␉break;␊
141␊
142␉␉case 0x10de:␊
143␉␉␉force_enable_hpet_nvidia(lpc_dev);␊
144␉␉␉break;␊
145␊
146␉␉case 0x1106:␊
147␉␉␉force_enable_hpet_via(lpc_dev);␊
148␉␉␉break;␊
149␉}␊
150␊
151#if DEBUG_HPET␊
152␉printf("Press [Enter] to continue...\n");␊
153␉getchar();␊
154#endif␊
155␊
156}␊
157␊
158/* ErmaC add lpc for nVidia */␊
159void force_enable_hpet_nvidia(pci_dt_t *lpc_dev)␊
160{␊
161␉uint32_t␉val, hpet_address = 0xFED00000;␊
162␉int i;␊
163␉void␉␉*rcba;␊
164␊
165␉for(i = 1; i < sizeof(lpc_controllers_nvidia) / sizeof(lpc_controllers_nvidia[0]); i++)␊
166␉{␊
167␉␉if ((lpc_controllers_nvidia[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_nvidia[i].device == lpc_dev->device_id))␊
168␉␉{␊
169␊
170␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊
171␊
172␉␉␉DBG("nVidia(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊
173␉␉␉␉lpc_controllers_nvidia[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊
174␊
175␉␉␉if (rcba == 0)␊
176␉␉␉{␊
177␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊
178␉␉␉}␊
179␉␉␉else␊
180␉␉␉{␊
181␉␉␉␉val = REG32(rcba, 0x3404);␊
182␉␉␉␉if (val & 0x80)␊
183␉␉␉␉{␊
184␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊
185␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊
186␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
187␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊
188␉␉␉␉}␊
189␉␉␉␉else␊
190␉␉␉␉{␊
191␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊
192␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊
193␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊
194␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
195␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊
196␉␉␉␉}␊
197␊
198␉␉␉␉// verify if the job is done␊
199␉␉␉␉val = REG32(rcba, 0x3404);␊
200␉␉␉␉if (!(val & 0x80))␊
201␉␉␉␉{␊
202␉␉␉␉␉printf(" Failed to force enable HPET\n");␊
203␉␉␉␉}␊
204␉␉␉}␊
205␉␉␉break;␊
206␉␉}␊
207␉}␊
208}␊
209␊
210void force_enable_hpet_via(pci_dt_t *lpc_dev)␊
211{␊
212␉uint32_t␉val, hpet_address = 0xFED00000;␊
213␉int i;␊
214␊
215␉for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++)␊
216␉{␊
217␉␉if ((lpc_controllers_via[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_via[i].device == lpc_dev->device_id))␊
218␉␉{␊
219␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
220␊
221␉␉␉DBG("VIA %s LPC Interface [%04x:%04x], MMIO\n", ␊
222␉␉␉␉lpc_controllers_via[i].name, lpc_dev->vendor_id, lpc_dev->device_id);␊
223␊
224␉␉␉if (val & 0x80)␊
225␉␉␉{␊
226␉␉␉␉hpet_address = (val & ~0x3ff);␊
227␉␉␉␉DBG("HPET at 0x%lx\n", hpet_address);␊
228␉␉␉}␊
229␉␉␉else␊
230␉␉␉{␊
231␉␉␉␉val = 0xfed00000 | 0x80;␊
232␉␉␉␉pci_config_write32(lpc_dev->dev.addr, 0x68, val);␊
233␉␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
234␉␉␉␉if (val & 0x80)␊
235␉␉␉␉{␊
236␉␉␉␉␉hpet_address = (val & ~0x3ff);␊
237␉␉␉␉␉DBG("Force enabled HPET at 0x%lx\n", hpet_address);␊
238␉␉␉␉}␊
239␉␉␉␉else␊
240␉␉␉␉{␊
241␉␉␉␉␉DBG("Unable to enable HPET");␊
242␉␉␉␉}␊
243␉␉␉}␊
244␉␉}␊
245␉}␊
246}␊
247␊
248void force_enable_hpet_intel(pci_dt_t *lpc_dev)␊
249{␊
250␉uint32_t␉val, hpet_address = 0xFED00000;␊
251␉int i;␊
252␉void␉␉*rcba;␊
253␊
254␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊
255␉for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++)␊
256␉{␊
257␉␉if ((lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_intel[i].device == lpc_dev->device_id))␊
258␉␉{␊
259␊
260␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊
261␊
262␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊
263␉␉␉␉lpc_controllers_intel[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊
264␊
265␉␉␉if (rcba == 0)␊
266␉␉␉{␊
267␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊
268␉␉␉}␊
269␉␉␉else␊
270␉␉␉{␊
271␉␉␉␉val = REG32(rcba, 0x3404);␊
272␉␉␉␉if (val & 0x80)␊
273␉␉␉␉{␊
274␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊
275␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊
276␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
277␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊
278␉␉␉␉}␊
279␉␉␉␉else␊
280␉␉␉␉{␊
281␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊
282␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊
283␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊
284␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
285␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊
286␉␉␉␉}␊
287␊
288␉␉␉␉// verify if the job is done␊
289␉␉␉␉val = REG32(rcba, 0x3404);␊
290␉␉␉␉if (!(val & 0x80))␊
291␉␉␉␉{␊
292␉␉␉␉␉printf(" Failed to force enable HPET\n");␊
293␉␉␉␉}␊
294␉␉␉}␊
295␉␉␉break;␊
296␉␉}␊
297␉}␊
298}␊
299␊
300

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