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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
36␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL:␊
38␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
39␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
40␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
41␊
42␉␉␉␉␉␉value->word = 0;␊
43␉␉␉␉␉␉break;␊
44␉␉␉␉␉default:␊
45␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
46␉␉␉␉}␊
47␉␉␉}␊
48␉␉␉␉break;␊
49␊
50␉␉␉default:␊
51␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
52␉␉}␊
53␉}␊
54␉else␊
55␉{␊
56␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
57␉}␊
58␊
59␉return true;␊
60}␊
61␊
62bool getProcessorInformationMaximumClock(returnType *value)␊
63{␊
64␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);␊
65␉return true;␊
66}␊
67␊
68bool getSMBOemProcessorBusSpeed(returnType *value)␊
69{␊
70␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
71␉␉switch (Platform.CPU.Family) {␊
72␉␉␉case 0x06:␊
73␉␉␉{␊
74␉␉␉␉switch (Platform.CPU.Model)␊
75␉␉␉␉{␊
76␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
77␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
78␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
79␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
80␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
81␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
82␉␉␉␉␉␉return false;␊
83␊
84␉␉␉␉␉case 0x19:␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
86␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
87␉␉␉␉␉case CPU_MODEL_DALES:␊
88␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
89␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
90␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
91␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
92␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
93␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
94␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
95␉␉␉␉␉case CPU_MODEL_HASWELL:␊
96␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
97␉␉␉␉␉{␊
98␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
99␉␉␉␉␉␉int nhm_bus = 0x3F;␊
100␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
101␉␉␉␉␉␉unsigned long did, vid;␊
102␉␉␉␉␉␉unsigned int i;␊
103␉␉␉␉␉␉␊
104␉␉␉␉␉␉// Nehalem supports Scrubbing␊
105␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
106␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
107␉␉␉␉␉␉{␊
108␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
109␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
110␉␉␉␉␉␉␉vid &= 0xFFFF;␊
111␉␉␉␉␉␉␉did &= 0xFF00;␊
112␉␉␉␉␉␉␉␊
113␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
114␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
115␉␉␉␉␉␉}␊
116␊
117␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
118␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
119␉␉␉␉␉␉qpimult &= 0x7F;␊
120␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
121␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
122␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
123␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
124␉␉␉␉␉␉{␊
125␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
126␉␉␉␉␉␉}␊
127␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
128␉␉␉␉␉␉value->word = qpibusspeed;␊
129␉␉␉␉␉␉return true;␊
130␉␉␉␉␉}␊
131␉␉␉␉␉default:␊
132␉␉␉␉␉␉break; //Unsupported CPU type␊
133␉␉␉␉}␊
134␉␉␉}␊
135␉␉␉default:␊
136␉␉␉␉break;␊
137␉␉}␊
138␉}␊
139␉return false;␊
140}␊
141␊
142uint16_t simpleGetSMBOemProcessorType(void)␊
143{␊
144␉if (Platform.CPU.NoCores >= 4) {␊
145␉␉return 0x0501;␉// Quad-Core Xeon␊
146␉}␊
147␉else if (Platform.CPU.NoCores == 1) {␊
148␉␉return 0x0201;␉// Core Solo␊
149␉};␊
150␉␊
151␉return 0x0301;␉␉// Core 2 Duo␊
152}␊
153␊
154bool getSMBOemProcessorType(returnType *value)␊
155{␊
156␉static bool done = false;␊
157␊
158␉value->word = simpleGetSMBOemProcessorType();␊
159␊
160␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
161␉{␊
162␉␉if (!done)␊
163␉␉{␊
164␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
165␉␉␉done = true;␊
166␉␉}␊
167␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
168␉␉switch (Platform.CPU.Family) {␊
169␉␉␉case 0x06:␊
170␉␉␉{␊
171␉␉␉␉switch (Platform.CPU.Model)␊
172␉␉␉␉{␊
173␊
174␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
175␉␉␉␉␉␉value->word = 0x101;␊
176␉␉␉␉␉␉return true;␊
177␊
178␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
179␉␉␉␉␉case CPU_MODEL_CELERON:␊
180␉␉␉␉␉␉value->word = 0x201;␊
181␉␉␉␉␉␉return true;␊
182␊
183␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
184␉␉␉␉␉␉value->word = 0x401;␊
185␉␉␉␉␉␉return true;␊
186␊
187␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
188␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
189␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
190␉␉␉␉␉␉{␊
191␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// Xeon␊
192␉␉␉␉␉␉}␊
193␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
194␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
195␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
196␉␉␉␉␉␉return true;␊
197␊
198␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
199␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
200␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
201␉␉␉␉␉␉{␊
202␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Xeon␊
203␉␉␉␉␉␉}␊
204␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
205␉␉␉␉␉␉{␊
206␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
207␉␉␉␉␉␉}␊
208␉␉␉␉␉␉return true;␊
209␊
210␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
211␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
212␉␉␉␉␉␉{␊
213␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Lynnfiled Quad-Core Xeon␊
214␉␉␉␉␉␉}␊
215␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
216␉␉␉␉␉␉{␊
217␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
218␉␉␉␉␉␉}␊
219␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
220␉␉␉␉␉␉{␊
221␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
222␉␉␉␉␉␉}␊
223␉␉␉␉␉␉return true;␊
224␊
225␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
226␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
227␉␉␉␉␉␉{␊
228␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
229␉␉␉␉␉␉}␊
230␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
231␉␉␉␉␉␉{␊
232␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
235␉␉␉␉␉␉{␊
236␉␉␉␉␉␉␉value->word = 0x702;␉␉␉// Core i7␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
239␉␉␉␉␉␉{␊
240␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉return true;␊
243␊
244␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
245␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
246␉␉␉␉␉␉{␊
247␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
248␉␉␉␉␉␉}␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
250␉␉␉␉␉␉{␊
251␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Core(TM) i5 CPU M 540"))␊
254␉␉␉␉␉␉{␊
255␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
258␉␉␉␉␉␉{␊
259␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
260␉␉␉␉␉␉}␊
261␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
262␉␉␉␉␉␉{␊
263␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
264␉␉␉␉␉␉}␊
265␉␉␉␉␉␉return true;␊
266␊
267␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
268␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
269␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
270␉␉␉␉␉␉{␊
271␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
272␉␉␉␉␉␉}␊
273␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
274␉␉␉␉␉␉{␊
275␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
276␉␉␉␉␉␉}␊
277␉␉␉␉␉␉return true;␊
278␊
279␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
280␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
281␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
282␉␉␉␉␉␉{␊
283␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
284␉␉␉␉␉␉}␊
285␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
286␉␉␉␉␉␉{␊
287␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3␊
288␉␉␉␉␉␉}␊
289␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
290␉␉␉␉␉␉{␊
291␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
292␉␉␉␉␉␉}␊
293␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
294␉␉␉␉␉␉{␊
295␉␉␉␉␉␉␉value->word = 0x703;␉␉// Core i7␊
296␉␉␉␉␉␉}␊
297␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
298␉␉␉␉␉␉{␊
299␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
300␉␉␉␉␉␉}␊
301␉␉␉␉␉␉return true;␊
302␊
303␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
304␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
305␉␉␉␉␉␉{␊
306␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
309␉␉␉␉␉␉{␊
310␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
311␉␉␉␉␉␉}␊
312␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
313␉␉␉␉␉␉{␊
314␉␉␉␉␉␉␉value->word = 0x704;␉␉// Core i7␊
315␉␉␉␉␉␉}␊
316␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
317␉␉␉␉␉␉{␊
318␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
319␉␉␉␉␉␉}␊
320␉␉␉␉␉␉return true;␊
321␊
322␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E -␊
323␉␉␉␉␉␉value->word = 0xA01;␊
324␉␉␉␉␉␉return true;␊
325␊
326␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
327␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
328␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
329␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
330␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
331␉␉␉␉␉␉{␊
332␉␉␉␉␉␉␉value->word = 0x905;␉␉// Core i3 - Apple doesn't use it␊
333␉␉␉␉␉␉}␊
334␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
335␉␉␉␉␉␉{␊
336␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
337␉␉␉␉␉␉}␊
338␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
339␉␉␉␉␉␉{␊
340␉␉␉␉␉␉␉value->word = 0x705;␉␉// Core i7␊
341␉␉␉␉␉␉}␊
342␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
343␉␉␉␉␉␉{␊
344␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
345␉␉␉␉␉␉}␊
346␉␉␉␉␉␉return true;␊
347␊
348␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
349␉␉␉␉␉␉value->word = 0x301;␉␉␉//␊
350␉␉␉␉␉␉return true;␊
351␊
352␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
353␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
354␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
355␉␉␉␉␉␉return true;␊
356␉␉␉␉␉default:␊
357␉␉␉␉␉␉break; //Unsupported CPU type␊
358␉␉␉␉}␊
359␉␉␉}␊
360␉␉␉default:␊
361␉␉␉␉break;␊
362␉␉}␊
363␉}␊
364␉␊
365␉return false;␊
366}␊
367␊
368bool getSMBMemoryDeviceMemoryType(returnType *value)␊
369{␊
370␉static int idx = -1;␊
371␉int␉map;␊
372␊
373␉idx++;␊
374␉if (idx < MAX_RAM_SLOTS)␊
375␉{␊
376␉␉map = Platform.DMI.DIMM[idx];␊
377␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
378␉␉{␊
379␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
380␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
381␉␉␉return true;␊
382␉␉}␊
383␉}␊
384␉␊
385␉return false;␊
386//␉value->byte = SMB_MEM_TYPE_DDR2;␊
387//␉return true;␊
388}␊
389␊
390bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
391{␊
392␉value->word = 0xFFFF;␊
393␉return true;␊
394}␊
395␊
396bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
397{␊
398␉static int idx = -1;␊
399␉int␉map;␊
400␊
401␉idx++;␊
402␉if (idx < MAX_RAM_SLOTS)␊
403␉{␊
404␉␉map = Platform.DMI.DIMM[idx];␊
405␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
406␉␉{␊
407␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
408␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
409␉␉␉return true;␊
410␉␉}␊
411␉}␊
412␊
413␉return false;␊
414//␉value->dword = 800;␊
415//␉return true;␊
416}␊
417␊
418bool getSMBMemoryDeviceManufacturer(returnType *value)␊
419{␊
420␉static int idx = -1;␊
421␉int␉map;␊
422␊
423␉idx++;␊
424␉if (idx < MAX_RAM_SLOTS)␊
425␉{␊
426␉␉map = Platform.DMI.DIMM[idx];␊
427␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
428␉␉{␊
429␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
430␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
431␉␉␉return true;␊
432␉␉}␊
433␉}␊
434␊
435␉if (!bootInfo->memDetect)␊
436␉{␊
437␉␉return false;␊
438␉}␊
439␉value->string = NOT_AVAILABLE;␊
440␉return true;␊
441}␊
442␊
443bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
444{␊
445␉static int idx = -1;␊
446␉int␉map;␊
447␊
448␉idx++;␊
449␊
450␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
451␊
452␉if (idx < MAX_RAM_SLOTS)␊
453␉{␊
454␉␉map = Platform.DMI.DIMM[idx];␊
455␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
456␉␉{␊
457␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
458␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
459␉␉␉return true;␊
460␉␉}␊
461␉}␊
462␊
463␉if (!bootInfo->memDetect)␊
464␉{␊
465␉␉return false;␊
466␉}␊
467␉value->string = NOT_AVAILABLE;␊
468␉return true;␊
469}␊
470␊
471bool getSMBMemoryDevicePartNumber(returnType *value)␊
472{␊
473␉static int idx = -1;␊
474␉int␉map;␊
475␊
476␉idx++;␊
477␉if (idx < MAX_RAM_SLOTS)␊
478␉{␊
479␉␉map = Platform.DMI.DIMM[idx];␊
480␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
481␉␉{␊
482␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
483␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
484␉␉␉return true;␊
485␉␉}␊
486␉}␊
487␊
488␉if (!bootInfo->memDetect)␊
489␉{␊
490␉␉return false;␊
491␉}␊
492␉value->string = NOT_AVAILABLE;␊
493␉return true;␊
494}␊
495␊
496␊
497// getting smbios addr with fast compare ops, late checksum testing ...␊
498#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
499static const char * const SMTAG = "_SM_";␊
500static const char* const DMITAG = "_DMI_";␊
501␊
502SMBEntryPoint *getAddressOfSmbiosTable(void)␊
503{␊
504␉SMBEntryPoint␉*smbios;␊
505␉/*␊
506␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
507␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
508␉ */␊
509␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
510␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
511␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
512␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
513␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
514␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
515␉␉␉return smbios;␊
516␉ }␊
517␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
518␉}␊
519␉printf("ERROR: Unable to find SMBIOS!\n");␊
520␉pause();␊
521␉return NULL;␊
522}␊
523␊
524

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