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1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72int spd_indexes[] = {␊
73␉SPD_MEMORY_TYPE,␊
74␉SPD_DDR3_MEMORY_BANK,␊
75␉SPD_DDR3_MEMORY_CODE,␊
76␉SPD_NUM_ROWS,␊
77␉SPD_NUM_COLUMNS,␊
78␉SPD_NUM_DIMM_BANKS,␊
79␉SPD_NUM_BANKS_PER_SDRAM,␊
80␉4,7,8,9,12,64, /* TODO: give names to these values */␊
81␉95,96,97,98, 122,123,124,125 /* UIS */␊
82};␊
83#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
84␊
85/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
86␊
87unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
88{␊
89␉int l1, h1, l2, h2;␊
90␉unsigned long long t;␊
91␊
92␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
93␉outb(base + SMBHSTDAT, 0xff);␊
94␊
95␉rdtsc(l1, h1);␊
96␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
97␉{␊
98␉␉rdtsc(l2, h2);␊
99␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
100␉␉if (t > 5)␊
101␉␉{␊
102␉␉␉return 0xFF;␉// break␊
103␉␉}␊
104␉}␊
105␊
106␉outb(base + SMBHSTCMD, cmd);␊
107␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
108␉outb(base + SMBHSTCNT, 0x48 );␊
109␊
110␉rdtsc(l1, h1);␊
111␊
112␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
113␉{␊
114␉␉rdtsc(l2, h2);␊
115␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
116␉␉if (t > 5)␊
117␉␉{␊
118␉␉␉break;␉// break after 5ms␊
119␉␉}␊
120␉}␊
121␉return inb(base + SMBHSTDAT);␊
122}␊
123␊
124/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
125#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
126␊
127␊
128/** Read from spd *used* values only*/␊
129static void init_spd(char * spd, uint32_t base, int slot)␊
130{␊
131␉int i;␊
132␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
133␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
134␉}␊
135}␊
136␊
137/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
138 have different formats, always return a valid ptr.*/␊
139const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
140{␊
141␉uint8_t bank = 0;␊
142␉uint8_t code = 0;␊
143␉int i = 0;␊
144␉uint8_t * spd = (uint8_t *) slot->spd;␊
145␊
146␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
147␉{ // DDR3␊
148␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
149␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
150␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
151␉␉{␊
152␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
153␉␉␉{␊
154␉␉␉␉return vendorMap[i].name;␊
155␉␉␉}␊
156␉␉}␊
157␉}␊
158␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
159␉{␊
160␉␉if(spd[64]==0x7f)␊
161␉␉{␊
162␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++)␊
163␉␉␉{␊
164␉␉␉␉bank++;␊
165␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
166␉␉␉}␊
167␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
168␉␉␉code = spd[i];␊
169␉␉}␊
170␉␉else␊
171␉␉{␊
172␉␉␉code = spd[64]; ␊
173␉␉␉bank = 0;␊
174␉␉}␊
175␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
176␉␉{␊
177␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
178␉␉␉{␊
179␉␉␉␉return vendorMap[i].name;␊
180␉␉␉}␊
181␉␉}␊
182␉}␊
183␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
184␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
185␉{␊
186␉␉return "Unifosa";␊
187␉}␊
188␉return "NoName";␊
189}␊
190␊
191/* Get Default Memory Module Speed (no overclocking handled) */␊
192int getDDRspeedMhz(const char * spd)␊
193{␊
194␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
195␉{ ␊
196␉␉switch(spd[12])␊
197␉␉{␊
198␉␉␉case 0x0f:␊
199␉␉␉␉return 1066;␊
200␉␉␉case 0x0c:␊
201␉␉␉␉return 1333;␊
202␉␉␉case 0x0a:␊
203␉␉␉␉return 1600;␊
204␉␉␉case 0x14:␊
205␉␉␉default:␊
206␉␉␉␉return 800;␊
207␉␉}␊
208␉} ␊
209␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
210␉{␊
211␉␉switch(spd[9])␊
212␉␉{␊
213␉␉␉case 0x50:␊
214␉␉␉␉return 400;␊
215␉␉␉case 0x3d:␊
216␉␉␉␉return 533;␊
217␉␉␉case 0x30:␊
218␉␉␉␉return 667;␊
219␉␉␉case 0x25:␊
220␉␉␉default:␊
221␉␉␉␉return 800;␊
222␉␉␉case 0x1E:␊
223␉␉␉␉return 1066;␊
224␉␉}␊
225␉}␊
226␉return 800; // default freq for unknown types␊
227}␊
228␊
229#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
230#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
231␊
232/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
233const char *getDDRSerial(const char* spd)␊
234{␊
235␉static char asciiSerial[16];␊
236 ␊
237␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
238␉{␊
239␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
240␉}␊
241␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
242␉{␊
243␉␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
244␉} else {␊
245␉␉sprintf(asciiSerial, "0000000000000000");␊
246␉}␊
247␊
248␉return strdup(asciiSerial);␊
249}␊
250␊
251/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
252const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
253{␊
254␉static char asciiPartNo[32];␊
255␉int i, start=0, index = 0;␊
256␊
257␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
258␉{␊
259␉␉start = 128;␊
260␉}␊
261␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
262␉{␊
263␉␉start = 73;␊
264␉}␊
265␉␊
266␉// Check that the spd part name is zero terminated and that it is ascii:␊
267␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
268␉char c;␊
269␉for (i=start; i < start + sizeof(asciiPartNo); i++)␊
270␉{␊
271␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
272␉␉c = spd[i];␊
273␉␉if (isalpha(c) || isdigit(c) || ispunct(c))␊
274␉␉{␊
275␉␉␉// It seems that System Profiler likes only letters and digits...␊
276␉␉␉asciiPartNo[index++] = c;␊
277␉␉}␊
278␉␉else if (!isascii(c))␊
279␉␉{␊
280␉␉␉break;␊
281␉␉}␊
282␉}␊
283␉␊
284␉return strdup(asciiPartNo);␊
285}␊
286␊
287int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
288␊
289␊
290/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
291static void read_smb_intel(pci_dt_t *smbus_dev)␊
292{ ␊
293␉uint16_t speed;␊
294␉uint8_t i, spd_size, spd_type;␊
295␉uint32_t base, mmio, hostc;␊
296//␉bool dump = false;␊
297␉RamSlotInfo_t* slot;␊
298␊
299␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
300␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
301␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
302␊
303␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
304␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
305␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
306␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
307␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
308␊
309␉//Azi: no use for this!␊
310␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
311␉// needed at least for laptops␊
312␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
313␊
314␉char spdbuf[MAX_SPD_SIZE];␊
315␉// Search MAX_RAM_SLOTS slots␊
316␉for (i = 0; i < MAX_RAM_SLOTS; i++)␊
317␉{␊
318 // ----␊
319␉␉slot = &Platform.RAM.DIMM[i];␊
320␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
321␉␉DBG("SPD[0] (size): 0x%02x @0x%x\n", spd_size, 0x50 + i);␊
322␉␉// Check spd is present␊
323␉␉if (spd_size && (spd_size != 0xff))␊
324␉␉{␊
325␊
326␉␉␉slot->spd = spdbuf;␊
327 // -----␊
328␉␉␉slot->InUse = true;␊
329␊
330␉␉␉bzero(slot->spd, spd_size);␊
331␊
332␉␉␉// Copy spd data into buffer␊
333␊
334␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
335␉␉␉init_spd(slot->spd, base, i);␊
336␊
337␉␉␉switch (slot->spd[SPD_MEMORY_TYPE])␊
338␉␉␉{␊
339␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
340 ␊
341␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
342 + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
343 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
344 slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
345␉␉␉␉break;␊
346␊
347␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
348␊
349␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) * ␊
350␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
351␉␉␉␉break;␊
352␊
353␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
354␊
355␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
356␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
357␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
358␊
359␉␉␉␉break;␊
360␉␉␉}␊
361␊
362␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
363␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
364␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE)␊
365␉␉␉{␊
366␉␉␉␉continue;␊
367␉␉␉}␊
368␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
369␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
370␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
371␊
372␉␉␉// determine spd speed␊
373␉␉␉speed = getDDRspeedMhz(slot->spd);␊
374␉␉␉if (slot->Frequency<speed)␊
375␉␉␉{␊
376␉␉␉␉slot->Frequency = speed;␊
377␉␉␉}␊
378␉␉␉␊
379␉␉␉// pci memory controller if available, is more reliable␊
380␉␉␉if (Platform.RAM.Frequency > 0)␊
381␉␉␉{␊
382␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
383␉␉␉␉// now round off special cases␊
384␉␉␉␉uint32_t fmod100 = freq %100;␊
385␉␉␉␉switch(fmod100)␊
386␉␉␉␉{␊
387␉␉␉␉␉case 1:␉freq--;␉break;␊
388␉␉␉␉␉case 32:␉freq++;␉break;␊
389␉␉␉␉␉case 65:␉freq++; break;␊
390␉␉␉␉␉case 98:␉freq+=2;break;␊
391␉␉␉␉␉case 99:␉freq++; break;␊
392␉␉␉␉}␊
393␉␉␉␉slot->Frequency = freq;␊
394␉␉␉}␊
395␊
396␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
397 i, ␊
398 (int)slot->Type,␊
399 slot->ModuleSize, ␊
400 spd_memory_types[spd_type],␊
401 slot->Frequency,␊
402 slot->Vendor,␊
403 slot->PartNo,␊
404 slot->SerialNo);␊
405 slot->InUse = true;␊
406␉␉}␊
407␊
408␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
409␉␉Platform.DMI.DIMM[i]= ␊
410 ␉(uint32_t)((i>0 && Platform.RAM.DIMM[1].InUse==false && !fullBanks && Platform.DMI.CntMemorySlots == 2) ?␊
411 ␉mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
412␉␉slot->spd = NULL;␊
413␊
414␉} // for␊
415}␊
416␊
417static struct smbus_controllers_t smbus_controllers[] = {␊
418// Info from here: http://cateee.net/lkddb/web-lkddb/I2C_I801.html␊
419␊
420␉{0x8086, 0x1C22, "6 Series", read_smb_intel },␊
421␉{0x8086, 0x1D22, "C600/X79 Series", read_smb_intel },␊
422␉{0x8086, 0x1D70, "C600/X79 Series", read_smb_intel },␊
423␉{0x8086, 0x1D71, "C608/C606/X79 Series", read_smb_intel },␊
424␉{0x8086, 0x1D72, "C608", read_smb_intel },␊
425␉{0x8086, 0x1E22, "7 Series/C210 Series", read_smb_intel },␊
426␉{0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
427␉{0x8086, 0x2413, "82801AA", read_smb_intel },␊
428␉{0x8086, 0x2423, "82801BA/BAM", read_smb_intel },␊
429␉{0x8086, 0x2443, "82801BA/BAM", read_smb_intel },␊
430␉{0x8086, 0x2483, "82801CA/CAM", read_smb_intel },␊
431␉{0x8086, 0x24C3, "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)", read_smb_intel },␊
432␉{0x8086, 0x24D3, "82801EB/ER (ICH5/ICH5R)", read_smb_intel },␊
433␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
434␉{0x8086, 0x266A, "82801FB/FBM/FR/FW/FRW (ICH6 Family)", read_smb_intel },␊
435␉{0x8086, 0x269B, "631xESB/632xESB/3100", read_smb_intel },␊
436␉{0x8086, 0x27DA, "N10/ICH 7 Family", read_smb_intel },␊
437␉{0x8086, 0x283E, "82801H (ICH8 Family) ", read_smb_intel },␊
438␉{0x8086, 0x2930, "82801I (ICH9 Family)", read_smb_intel },␊
439␉{0x8086, 0x3A30, "82801JI (ICH10 Family)", read_smb_intel },␊
440␉{0x8086, 0x3A60, "82801JD/DO (ICH10 Family)", read_smb_intel },␊
441␉{0x8086, 0x3B30, "5 Series/3400 Series", read_smb_intel },␊
442␉{0x8086, 0x5032, "EP80579", read_smb_intel },␊
443␉{0x8086, 0x8C22, "8 Series/C220", read_smb_intel },␊
444␉{0x8086, 0x9C22, "Lynx Point-LP", read_smb_intel }␊
445␊
446};␊
447␊
448// initial call : pci_dt = root_pci_dev;␊
449// find_and_read_smbus_controller(root_pci_dev);␊
450bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
451{␊
452␉pci_dt_t␉*current = pci_dt;␊
453␉int i;␊
454␊
455␉while (current)␊
456␉{␊
457#if 0␊
458␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
459␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
460␉␉current->class_id, current->vendor_id, current->device_id, ␊
461␉␉get_pci_dev_path(current));␊
462#endif␊
463␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
464␉␉{␊
465␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device)␊
466␉␉␉{␊
467␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
468␉␉␉␉return true;␊
469␉␉␉}␊
470␉␉}␊
471␉␉find_and_read_smbus_controller(current->children);␊
472␉␉current = current->next;␊
473␉}␊
474␉return false; // not found␊
475}␊
476␊
477void scan_spd(PlatformInfo_t *p)␊
478{␊
479␉find_and_read_smbus_controller(root_pci_dev);␊
480}␊
481␊
482

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