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1/*␊
2 * platform.h␊
3 * AsereBLN: reworked and extended␊
4 *␊
5 */␊
6␊
7#ifndef __LIBSAIO_PLATFORM_H␊
8#define __LIBSAIO_PLATFORM_H␊
9␊
10//#include "libsaio.h"␊
11␊
12extern bool platformCPUFeature(uint32_t);␊
13extern void scan_platform(void);␊
14extern void dumpPhysAddr(const char * title, void * a, int len);␊
15␊
16/* CPUID Vendor */␊
17#define CPUID_VENDOR_INTEL 0x756E6547␊
18#define CPUID_VENDOR_AMD 0x68747541␊
19␊
20/* CPUID index into cpuid_raw */␊
21#define CPUID_0␉␉␉␉0␊
22#define CPUID_1␉␉␉␉1␊
23#define CPUID_2␉␉␉␉2␊
24#define CPUID_3␉␉␉␉3␊
25#define CPUID_4␉␉␉␉4␊
26#define CPUID_5␉␉␉␉5␊
27#define CPUID_6␉␉␉␉6␊
28#define CPUID_80␉␉␉7␊
29#define CPUID_81␉␉␉8␊
30#define CPUID_88␉␉␉9␊
31#define CPUID_MAX␉␉␉10␊
32␊
33#define CPU_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊
34#define CPU_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona, Irwindale (90nm)␊
35#define CPU_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊
36#define CPU_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias␊
37#define CPU_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan␊
38#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
39#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
40#define CPU_MODEL_CONROE␉␉0x0F␉␉␉// ␊
41#define CPU_MODEL_CELERON␉␉0x16␉␉␉// ␊
42#define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
43#define CPU_MODEL_WOLFDALE␉␉0x17␉␉␉// ␊
44#define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
45#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Pineview␊
46#define CPU_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊
47#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
48#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
49#define CPU_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
50#define CPU_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
51#define CPU_MODEL_LINCROFT␉␉0x27␉␉␉// ␊
52#define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
53#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
54#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
55#define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
56#define CPU_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
57#define CPU_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview␊
58#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
59#define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
60#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
61#define CPU_MODEL_HASWELL_MB␉␉0x3F␉␉␉// Haswell MB␊
62//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
63#define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊
64#define CPU_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Haswell ULX␊
65␊
66/* CPU Features */␊
67#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
68#define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊
69#define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊
70#define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊
71#define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊
72#define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊
73#define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊
74#define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊
75#define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊
76#define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊
77␊
78/* SMBIOS Memory Types */ ␊
79#define SMB_MEM_TYPE_UNDEFINED␉0␊
80#define SMB_MEM_TYPE_OTHER␉␉1␊
81#define SMB_MEM_TYPE_UNKNOWN␉2␊
82#define SMB_MEM_TYPE_DRAM␉␉3␊
83#define SMB_MEM_TYPE_EDRAM␉␉4␊
84#define SMB_MEM_TYPE_VRAM␉␉5␊
85#define SMB_MEM_TYPE_SRAM␉␉6␊
86#define SMB_MEM_TYPE_RAM␉␉7␊
87#define SMB_MEM_TYPE_ROM␉␉8␊
88#define SMB_MEM_TYPE_FLASH␉␉9␊
89#define SMB_MEM_TYPE_EEPROM␉␉10␊
90#define SMB_MEM_TYPE_FEPROM␉␉11␊
91#define SMB_MEM_TYPE_EPROM␉␉12␊
92#define SMB_MEM_TYPE_CDRAM␉␉13␊
93#define SMB_MEM_TYPE_3DRAM␉␉14␊
94#define SMB_MEM_TYPE_SDRAM␉␉15␊
95#define SMB_MEM_TYPE_SGRAM␉␉16␊
96#define SMB_MEM_TYPE_RDRAM␉␉17␊
97#define SMB_MEM_TYPE_DDR␉␉18␊
98#define SMB_MEM_TYPE_DDR2␉␉19␊
99#define SMB_MEM_TYPE_FBDIMM␉␉20␊
100#define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊
101␊
102/* Memory Configuration Types */ ␊
103#define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊
104#define SMB_MEM_CHANNEL_SINGLE␉␉1␊
105#define SMB_MEM_CHANNEL_DUAL␉␉2␊
106#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
107␊
108/* Maximum number of ram slots */␊
109#define MAX_RAM_SLOTS␉␉␉8␊
110#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
111␊
112/* Maximum number of SPD bytes */␊
113#define MAX_SPD_SIZE␉␉␉256␊
114␊
115/* Size of SMBIOS UUID in bytes */␊
116#define UUID_LEN␉␉␉16␊
117␊
118typedef struct _RamSlotInfo_t␊
119{␊
120␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
121␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
122␉const char*␉␉Vendor;␊
123␉const char*␉␉PartNo;␊
124␉const char*␉␉SerialNo;␊
125␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
126␉bool␉␉␉InUse;␊
127␉uint8_t␉␉␉Type;␊
128␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
129␉uint8_t␉␉␉BankConnCnt;␊
130} RamSlotInfo_t;␊
131␊
132//==============================================================================␊
133␊
134typedef struct _PlatformInfo_t {␊
135␉struct CPU {␊
136␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
137␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
138␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
139␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
140␉␉uint32_t␉␉Type;␉␉␉␉␉// Type␊
141␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
142␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
143␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
144␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊
145␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
146␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
147␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
148␉␉uint8_t␉␉␉MaxDiv;␊
149␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
150␉␉uint8_t␉␉␉CurrDiv;␊
151␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
152␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
153␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
154␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
155␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
156␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
157␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
158␉} CPU;␊
159␊
160␉struct RAM {␊
161␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
162␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
163␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
164␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
165␉␉uint8_t␉␉␉TRP;␊
166␉␉uint8_t␉␉␉RAS;␊
167␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
168␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
169␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
170␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
171␉} RAM;␊
172␊
173␉struct DMI {␊
174␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots populated by SMBIOS␊
175␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊
176␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊
177␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊
178␉} DMI;␊
179␊
180␉uint8_t␉␉␉␉Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
181␉uint8_t␉␉␉␉*UUID;␊
182} PlatformInfo_t;␊
183␊
184extern PlatformInfo_t Platform;␊
185␊
186#endif /* !__LIBSAIO_PLATFORM_H */␊
187

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