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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_HASWELL:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
38␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
39␊
40␉␉␉␉␉␉value->word = 0;␊
41␉␉␉␉␉␉break;␊
42␉␉␉␉␉default:␊
43␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
44␉␉␉␉}␊
45␉␉␉}␊
46␉␉␉␉break;␊
47␊
48␉␉␉default:␊
49␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
50␉␉}␊
51␉} else {␊
52␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
53␉}␊
54␊
55␉return true;␊
56}␊
57␊
58bool getProcessorInformationMaximumClock(returnType *value)␊
59{␊
60␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);␊
61␉return true;␊
62}␊
63␊
64bool getSMBOemProcessorBusSpeed(returnType *value)␊
65{␊
66␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
67␉␉switch (Platform.CPU.Family) {␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model)␊
71␉␉␉␉{␊
72␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
73␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
74␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
75␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
76␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
77␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
78␉␉␉␉␉␉return false;␊
79␊
80␉␉␉␉␉case 0x19:␊
81␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
83␉␉␉␉␉case CPU_MODEL_DALES:␊
84␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
86␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
87␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
88␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
89␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
90␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
91␉␉␉␉␉case CPU_MODEL_HASWELL:␊
92␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
93␉␉␉␉␉{␊
94␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
95␉␉␉␉␉␉int nhm_bus = 0x3F;␊
96␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
97␉␉␉␉␉␉unsigned long did, vid;␊
98␉␉␉␉␉␉unsigned int i;␊
99␉␉␉␉␉␉␊
100␉␉␉␉␉␉// Nehalem supports Scrubbing␊
101␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
102␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
103␉␉␉␉␉␉{␊
104␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
105␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
106␉␉␉␉␉␉␉vid &= 0xFFFF;␊
107␉␉␉␉␉␉␉did &= 0xFF00;␊
108␉␉␉␉␉␉␉␊
109␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
110␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
111␉␉␉␉␉␉}␊
112␊
113␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
114␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
115␉␉␉␉␉␉qpimult &= 0x7F;␊
116␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
117␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
118␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
119␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
120␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
121␉␉␉␉␉␉}␊
122␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
123␉␉␉␉␉␉value->word = qpibusspeed;␊
124␉␉␉␉␉␉return true;␊
125␉␉␉␉␉}␊
126␉␉␉␉␉default:␊
127␉␉␉␉␉␉break; //Unsupported CPU type␊
128␉␉␉␉}␊
129␉␉␉}␊
130␉␉␉default:␊
131␉␉␉␉break;␊
132␉␉}␊
133␉}␊
134␉return false;␊
135}␊
136␊
137uint16_t simpleGetSMBOemProcessorType(void)␊
138{␊
139␉if (Platform.CPU.NoCores >= 4) {␊
140␉␉return 0x0501;␉// Quad-Core Xeon␊
141␉}␊
142␉else if (Platform.CPU.NoCores == 1) {␊
143␉␉return 0x0201;␉// Core Solo␊
144␉};␊
145␉␊
146␉return 0x0301;␉␉// Core 2 Duo␊
147}␊
148␊
149bool getSMBOemProcessorType(returnType *value)␊
150{␊
151␉static bool done = false;␊
152␊
153␉value->word = simpleGetSMBOemProcessorType();␊
154␊
155␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
156␉{␊
157␉␉if (!done)␊
158␉␉{␊
159␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
160␉␉␉done = true;␊
161␉␉}␊
162␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
163␉␉switch (Platform.CPU.Family) {␊
164␉␉␉case 0x06:␊
165␉␉␉{␊
166␉␉␉␉switch (Platform.CPU.Model)␊
167␉␉␉␉{␊
168␊
169␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
170␉␉␉␉␉␉value->word = 0x101;␊
171␉␉␉␉␉␉return true;␊
172␊
173␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
174␉␉␉␉␉case CPU_MODEL_CELERON:␊
175␉␉␉␉␉␉value->word = 0x201;␊
176␉␉␉␉␉␉return true;␊
177␊
178␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
179␉␉␉␉␉␉value->word = 0x401;␊
180␉␉␉␉␉␉return true;␊
181␊
182␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
183␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
184␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
185␉␉␉␉␉␉{␊
186␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// Xeon␊
187␉␉␉␉␉␉}␊
188␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
189␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
190␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
191␉␉␉␉␉␉return true;␊
192␊
193␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
194␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
195␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
196␉␉␉␉␉␉{␊
197␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Xeon␊
198␉␉␉␉␉␉}␊
199␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
200␉␉␉␉␉␉{␊
201␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
202␉␉␉␉␉␉}␊
203␉␉␉␉␉␉return true;␊
204␊
205␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
206␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
207␉␉␉␉␉␉{␊
208␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Lynnfiled Quad-Core Xeon␊
209␉␉␉␉␉␉}␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
211␉␉␉␉␉␉{␊
212␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
215␉␉␉␉␉␉{␊
216␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
217␉␉␉␉␉␉}␊
218␉␉␉␉␉␉return true;␊
219␊
220␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
221␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
222␉␉␉␉␉␉{␊
223␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
224␉␉␉␉␉␉}␊
225␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
226␉␉␉␉␉␉{␊
227␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
228␉␉␉␉␉␉}␊
229␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
230␉␉␉␉␉␉{␊
231␉␉␉␉␉␉␉value->word = 0x702;␉␉␉// Core i7␊
232␉␉␉␉␉␉}␊
233␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
234␉␉␉␉␉␉{␊
235␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
236␉␉␉␉␉␉}␊
237␉␉␉␉␉␉return true;␊
238␊
239␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
240␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
241␉␉␉␉␉␉{␊
242␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
243␉␉␉␉␉␉}␊
244␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
245␉␉␉␉␉␉{␊
246␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
247␉␉␉␉␉␉}␊
248␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Core(TM) i5 CPU M 540"))␊
249␉␉␉␉␉␉{␊
250␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
251␉␉␉␉␉␉}␊
252␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
253␉␉␉␉␉␉{␊
254␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
255␉␉␉␉␉␉}␊
256␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
257␉␉␉␉␉␉{␊
258␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
259␉␉␉␉␉␉}␊
260␉␉␉␉␉␉return true;␊
261␊
262␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
263␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
264␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
265␉␉␉␉␉␉{␊
266␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
267␉␉␉␉␉␉}␊
268␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
269␉␉␉␉␉␉{␊
270␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
271␉␉␉␉␉␉}␊
272␉␉␉␉␉␉return true;␊
273␊
274␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
275␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
276␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
277␉␉␉␉␉␉{␊
278␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
279␉␉␉␉␉␉}␊
280␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
281␉␉␉␉␉␉{␊
282␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3␊
283␉␉␉␉␉␉}␊
284␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
285␉␉␉␉␉␉{␊
286␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
287␉␉␉␉␉␉}␊
288␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
289␉␉␉␉␉␉{␊
290␉␉␉␉␉␉␉value->word = 0x703;␉␉// Core i7␊
291␉␉␉␉␉␉}␊
292␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
293␉␉␉␉␉␉{␊
294␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
295␉␉␉␉␉␉}␊
296␉␉␉␉␉␉return true;␊
297␊
298␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
299␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
300␉␉␉␉␉␉{␊
301␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it␊
302␉␉␉␉␉␉}␊
303␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
304␉␉␉␉␉␉{␊
305␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
306␉␉␉␉␉␉}␊
307␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
308␉␉␉␉␉␉{␊
309␉␉␉␉␉␉␉value->word = 0x704;␉␉// Core i7␊
310␉␉␉␉␉␉}␊
311␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
312␉␉␉␉␉␉{␊
313␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
314␉␉␉␉␉␉}␊
315␉␉␉␉␉␉return true;␊
316␊
317␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E -␊
318␉␉␉␉␉␉value->word = 0xA01;␊
319␉␉␉␉␉␉return true;␊
320␊
321␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
322␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
323␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
324␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
325␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
326␉␉␉␉␉␉{␊
327␉␉␉␉␉␉␉value->word = 0x905;␉␉// Core i3 - Apple doesn't use it␊
328␉␉␉␉␉␉}␊
329␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
330␉␉␉␉␉␉{␊
331␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
332␉␉␉␉␉␉}␊
333␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
334␉␉␉␉␉␉{␊
335␉␉␉␉␉␉␉value->word = 0x705;␉␉// Core i7␊
336␉␉␉␉␉␉}␊
337␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
338␉␉␉␉␉␉{␊
339␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
340␉␉␉␉␉␉}␊
341␉␉␉␉␉␉return true;␊
342␊
343␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
344␉␉␉␉␉␉value->word = 0x301;␉␉␉//␊
345␉␉␉␉␉␉return true;␊
346␊
347␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
348␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
349␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
350␉␉␉␉␉␉return true;␊
351␉␉␉␉␉default:␊
352␉␉␉␉␉␉break; //Unsupported CPU type␊
353␉␉␉␉}␊
354␉␉␉}␊
355␉␉␉default:␊
356␉␉␉␉break;␊
357␉␉}␊
358␉}␊
359␉␊
360␉return false;␊
361}␊
362␊
363bool getSMBMemoryDeviceMemoryType(returnType *value)␊
364{␊
365␉static int idx = -1;␊
366␉int␉map;␊
367␊
368␉idx++;␊
369␉if (idx < MAX_RAM_SLOTS) {␊
370␉␉map = Platform.DMI.DIMM[idx];␊
371␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
372␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
373␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
374␉␉␉return true;␊
375␉␉}␊
376␉}␊
377␊
378␉return false;␊
379//␉value->byte = SMB_MEM_TYPE_DDR2;␊
380//␉return true;␊
381}␊
382␊
383bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
384{␊
385␉value->word = 0xFFFF;␊
386␉return true;␊
387}␊
388␊
389bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
390{␊
391␉static int idx = -1;␊
392␉int␉map;␊
393␊
394␉idx++;␊
395␉if (idx < MAX_RAM_SLOTS) {␊
396␉␉map = Platform.DMI.DIMM[idx];␊
397␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
398␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
399␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
400␉␉␉return true;␊
401␉␉}␊
402␉}␊
403␊
404␉return false;␊
405//␉value->dword = 800;␊
406//␉return true;␊
407}␊
408␊
409bool getSMBMemoryDeviceManufacturer(returnType *value)␊
410{␊
411␉static int idx = -1;␊
412␉int␉map;␊
413␊
414␉idx++;␊
415␉if (idx < MAX_RAM_SLOTS)␊
416␉{␊
417␉␉map = Platform.DMI.DIMM[idx];␊
418␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
419␉␉{␊
420␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
421␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
422␉␉␉return true;␊
423␉␉}␊
424␉}␊
425␊
426␉if (!bootInfo->memDetect) {␊
427␉␉return false;␊
428␉}␊
429␉value->string = NOT_AVAILABLE;␊
430␉return true;␊
431}␊
432␊
433bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
434{␊
435␉static int idx = -1;␊
436␉int␉map;␊
437␊
438␉idx++;␊
439␊
440␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
441␊
442␉if (idx < MAX_RAM_SLOTS) {␊
443␉␉map = Platform.DMI.DIMM[idx];␊
444␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
445␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
446␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
447␉␉␉return true;␊
448␉␉}␊
449␉}␊
450␊
451␉if (!bootInfo->memDetect) {␊
452␉␉return false;␊
453␉}␊
454␉value->string = NOT_AVAILABLE;␊
455␉return true;␊
456}␊
457␊
458bool getSMBMemoryDevicePartNumber(returnType *value)␊
459{␊
460␉static int idx = -1;␊
461␉int␉map;␊
462␊
463␉idx++;␊
464␉if (idx < MAX_RAM_SLOTS) {␊
465␉␉map = Platform.DMI.DIMM[idx];␊
466␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
467␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
468␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
469␉␉␉return true;␊
470␉␉}␊
471␉}␊
472␊
473␉if (!bootInfo->memDetect) {␊
474␉␉return false;␊
475␉}␊
476␉value->string = NOT_AVAILABLE;␊
477␉return true;␊
478}␊
479␊
480␊
481// getting smbios addr with fast compare ops, late checksum testing ...␊
482#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
483static const char * const SMTAG = "_SM_";␊
484static const char* const DMITAG = "_DMI_";␊
485␊
486SMBEntryPoint *getAddressOfSmbiosTable(void)␊
487{␊
488␉SMBEntryPoint␉*smbios;␊
489␉/*␊
490␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
491␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
492␉ */␊
493␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
494␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
495␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
496␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
497␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
498␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
499␉␉␉return smbios;␊
500␉ }␊
501␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
502␉}␊
503␉printf("ERROR: Unable to find SMBIOS!\n");␊
504␉pause();␊
505␉return NULL;␊
506}␊
507␊
508

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