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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_HASWELL:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
38␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
39␊
40␉␉␉␉␉␉value->word = 0;␊
41␉␉␉␉␉␉break;␊
42␉␉␉␉␉default:␊
43␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
44␉␉␉␉}␊
45␉␉␉}␊
46␉␉␉␉break;␊
47␊
48␉␉␉default:␊
49␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉}␊
51␉} else {␊
52␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
53␉}␊
54␊
55␉return true;␊
56}␊
57␊
58bool getProcessorInformationMaximumClock(returnType *value)␊
59{␊
60␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
61␉return true;␊
62}␊
63␊
64bool getSMBOemProcessorBusSpeed(returnType *value)␊
65{␊
66␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
67␉␉switch (Platform.CPU.Family) {␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model) {␊
71␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case 0x19:␊
80␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_DALES:␊
83␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
84␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
86␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
87␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
88␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
89␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
90␉␉␉␉␉case CPU_MODEL_HASWELL:␊
91␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
92␉␉␉␉␉{␊
93␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
94␉␉␉␉␉␉int nhm_bus = 0x3F;␊
95␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
96␉␉␉␉␉␉unsigned long did, vid;␊
97␉␉␉␉␉␉unsigned int i;␊
98␉␉␉␉␉␉␊
99␉␉␉␉␉␉// Nehalem supports Scrubbing␊
100␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
101␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
102␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
103␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
104␉␉␉␉␉␉␉vid &= 0xFFFF;␊
105␉␉␉␉␉␉␉did &= 0xFF00;␊
106␉␉␉␉␉␉␉␊
107␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
108␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
109␉␉␉␉␉␉␉}␊
110␉␉␉␉␉␉}␊
111␊
112␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
113␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
114␉␉␉␉␉␉qpimult &= 0x7F;␊
115␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
116␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
117␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
118␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
119␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
120␉␉␉␉␉␉}␊
121␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
122␉␉␉␉␉␉value->word = qpibusspeed;␊
123␉␉␉␉␉␉return true;␊
124␉␉␉␉␉}␊
125␉␉␉␉␉default:␊
126␉␉␉␉␉␉break; //Unsupported CPU type␊
127␉␉␉␉}␊
128␉␉␉}␊
129␉␉␉default:␊
130␉␉␉␉break;␊
131␉␉}␊
132␉}␊
133␉return false;␊
134}␊
135␊
136uint16_t simpleGetSMBOemProcessorType(void)␊
137{␊
138␉if (Platform.CPU.NoCores >= 4) {␊
139␉␉return 0x0501;␉// Quad-Core Xeon␊
140␉} else if (Platform.CPU.NoCores == 1) {␊
141␉␉return 0x0201;␉// Core Solo␊
142␉};␊
143␉␊
144␉return 0x0301;␉␉// Core 2 Duo␊
145}␊
146␊
147bool getSMBOemProcessorType(returnType *value)␊
148{␊
149␉static bool done = false;␊
150␊
151␉value->word = simpleGetSMBOemProcessorType();␊
152␊
153␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
154␉␉if (!done) {␊
155␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
156␉␉␉done = true;␊
157␉␉}␊
158␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
159␉␉switch (Platform.CPU.Family) {␊
160␉␉␉case 0x06:␊
161␉␉␉{␊
162␉␉␉␉switch (Platform.CPU.Model) {␊
163␊
164␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
165␉␉␉␉␉␉value->word = 0x101;␊
166␉␉␉␉␉␉return true;␊
167␊
168␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
169␉␉␉␉␉case CPU_MODEL_CELERON:␊
170␉␉␉␉␉␉value->word = 0x201;␊
171␉␉␉␉␉␉return true;␊
172␊
173␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
174␉␉␉␉␉␉value->word = 0x401;␊
175␉␉␉␉␉␉return true;␊
176␊
177␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
178␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
179␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
180␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// Xeon␊
181␉␉␉␉␉␉}␊
182␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
183␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
184␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
185␉␉␉␉␉␉return true;␊
186␊
187␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
188␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
189␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
190␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Xeon␊
191␉␉␉␉␉␉}␊
192␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
193␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
194␉␉␉␉␉␉}␊
195␉␉␉␉␉␉return true;␊
196␊
197␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
198␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
199␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Lynnfiled Quad-Core Xeon␊
200␉␉␉␉␉␉}␊
201␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
202␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
203␉␉␉␉␉␉}␊
204␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
205␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
206␉␉␉␉␉␉}␊
207␉␉␉␉␉␉return true;␊
208␊
209␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
211␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
212␉␉␉␉␉␉}␊
213␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
214␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
215␉␉␉␉␉␉}␊
216␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
217␉␉␉␉␉␉␉value->word = 0x702;␉␉␉// Core i7␊
218␉␉␉␉␉␉}␊
219␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
220␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
221␉␉␉␉␉␉}␊
222␉␉␉␉␉␉return true;␊
223␊
224␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
225␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
226␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
227␉␉␉␉␉␉}␊
228␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
229␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
230␉␉␉␉␉␉}␊
231␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Core(TM) i5 CPU M 540")) {␊
232␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
235␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
236␉␉␉␉␉␉}␊
237␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
238␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
239␉␉␉␉␉␉}␊
240␉␉␉␉␉␉return true;␊
241␊
242␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
243␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
244␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
245␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
246␉␉␉␉␉␉}␊
247␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
248␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
249␉␉␉␉␉␉}␊
250␉␉␉␉␉␉return true;␊
251␊
252␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
253␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
254␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
255␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
258␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3␊
259␉␉␉␉␉␉}␊
260␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
261␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
262␉␉␉␉␉␉}␊
263␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
264␉␉␉␉␉␉␉value->word = 0x703;␉␉// Core i7␊
265␉␉␉␉␉␉}␊
266␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
267␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
268␉␉␉␉␉␉}␊
269␉␉␉␉␉␉return true;␊
270␊
271␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
272␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
273␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it␊
274␉␉␉␉␉␉}␊
275␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
276␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
277␉␉␉␉␉␉}␊
278␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
279␉␉␉␉␉␉␉value->word = 0x704;␉␉// Core i7␊
280␉␉␉␉␉␉}␊
281␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
282␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
283␉␉␉␉␉␉}␊
284␉␉␉␉␉␉return true;␊
285␊
286␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉␉// 0x3E - Mac Pro 6,1 - shouldn't be Sandy Bridge EP refering to intel spec.?␊
287␉␉␉␉␉␉value->word = 0xA01;␊
288␉␉␉␉␉␉return true;␊
289␊
290␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
291␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
292␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
293␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
294␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
295␉␉␉␉␉␉␉value->word = 0x905;␉␉// Core i3 - Apple doesn't use it␊
296␉␉␉␉␉␉}␊
297␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
298␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
299␉␉␉␉␉␉}␊
300␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
301␉␉␉␉␉␉␉value->word = 0x705;␉␉// Core i7␊
302␉␉␉␉␉␉}␊
303␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
304␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
305␉␉␉␉␉␉}␊
306␉␉␉␉␉␉return true;␊
307␊
308␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
309␉␉␉␉␉␉value->word = 0x301;␉␉␉//␊
310␉␉␉␉␉␉return true;␊
311␊
312␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
313␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
314␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
315␉␉␉␉␉␉return true;␊
316␉␉␉␉␉default:␊
317␉␉␉␉␉␉break; //Unsupported CPU type␊
318␉␉␉␉}␊
319␉␉␉}␊
320␉␉␉default:␊
321␉␉␉␉break;␊
322␉␉}␊
323␉}␊
324␉␊
325␉return false;␊
326}␊
327␊
328bool getSMBMemoryDeviceMemoryType(returnType *value)␊
329{␊
330␉static int idx = -1;␊
331␉int␉map;␊
332␊
333␉idx++;␊
334␉if (idx < MAX_RAM_SLOTS) {␊
335␉␉map = Platform.DMI.DIMM[idx];␊
336␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
337␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
338␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
339␉␉␉return true;␊
340␉␉}␊
341␉}␊
342␊
343␉return false;␊
344//␉value->byte = SMB_MEM_TYPE_DDR2;␊
345//␉return true;␊
346}␊
347␊
348bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
349{␊
350␉value->word = 0xFFFF;␊
351␉return true;␊
352}␊
353␊
354bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
355{␊
356␉static int idx = -1;␊
357␉int␉map;␊
358␊
359␉idx++;␊
360␉if (idx < MAX_RAM_SLOTS) {␊
361␉␉map = Platform.DMI.DIMM[idx];␊
362␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
363␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
364␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
365␉␉␉return true;␊
366␉␉}␊
367␉}␊
368␊
369␉return false;␊
370//␉value->dword = 800;␊
371//␉return true;␊
372}␊
373␊
374bool getSMBMemoryDeviceManufacturer(returnType *value)␊
375{␊
376␉static int idx = -1;␊
377␉int␉map;␊
378␊
379␉idx++;␊
380␉if (idx < MAX_RAM_SLOTS) {␊
381␉␉map = Platform.DMI.DIMM[idx];␊
382␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
383␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
384␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
385␉␉␉return true;␊
386␉␉}␊
387␉}␊
388␊
389␉if (!bootInfo->memDetect) {␊
390␉␉return false;␊
391␉}␊
392␉value->string = NOT_AVAILABLE;␊
393␉return true;␊
394}␊
395␊
396bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
397{␊
398␉static int idx = -1;␊
399␉int␉map;␊
400␊
401␉idx++;␊
402␊
403␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
404␊
405␉if (idx < MAX_RAM_SLOTS) {␊
406␉␉map = Platform.DMI.DIMM[idx];␊
407␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
408␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
409␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
410␉␉␉return true;␊
411␉␉}␊
412␉}␊
413␊
414␉if (!bootInfo->memDetect) {␊
415␉␉return false;␊
416␉}␊
417␉value->string = NOT_AVAILABLE;␊
418␉return true;␊
419}␊
420␊
421bool getSMBMemoryDevicePartNumber(returnType *value)␊
422{␊
423␉static int idx = -1;␊
424␉int␉map;␊
425␊
426␉idx++;␊
427␉if (idx < MAX_RAM_SLOTS) {␊
428␉␉map = Platform.DMI.DIMM[idx];␊
429␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
430␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
431␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
432␉␉␉return true;␊
433␉␉}␊
434␉}␊
435␊
436␉if (!bootInfo->memDetect) {␊
437␉␉return false;␊
438␉}␊
439␉value->string = NOT_AVAILABLE;␊
440␉return true;␊
441}␊
442␊
443␊
444// getting smbios addr with fast compare ops, late checksum testing ...␊
445#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
446static const char * const SMTAG = "_SM_";␊
447static const char* const DMITAG = "_DMI_";␊
448␊
449SMBEntryPoint *getAddressOfSmbiosTable(void)␊
450{␊
451␉SMBEntryPoint␉*smbios;␊
452␉/*␊
453␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
454␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
455␉ */␊
456␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
457␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
458␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
459␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
460␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
461␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
462␉␉␉return smbios;␊
463␉ }␊
464␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
465␉}␊
466␉printf("ERROR: Unable to find SMBIOS!\n");␊
467␉pause();␊
468␉return NULL;␊
469}␊
470␊
471

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