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1/*
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>
3 * AsereBLN: 2009: cleanup and bugfix
4 */
5
6#ifndef __LIBSAIO_CPU_H
7#define __LIBSAIO_CPU_H
8
9#include "platform.h"
10
11extern void scan_cpu(PlatformInfo_t *);
12
13#define bit(n)(1ULL << (n))
14#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
15#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
16
17#define CPU_STRING_UNKNOWN"Unknown CPU Type"
18
19#defineMSR_IA32_PERF_STATUS0x00000198
20#define MSR_IA32_PERF_CONTROL0x199
21#define MSR_IA32_EXT_CONFIG0x00EE
22#define MSR_FLEX_RATIO0x194
23#define MSR_TURBO_RATIO_LIMIT0x1AD
24#defineMSR_PLATFORM_INFO0xCE
25#define MSR_CORE_THREAD_COUNT0x35// Undocumented
26#define MSR_IA32_PLATFORM_ID0x17
27
28#define K8_FIDVID_STATUS0xC0010042
29#define K10_COFVID_STATUS0xC0010071
30
31#define MSR_AMD_MPERF 0x000000E7
32#define MSR_AMD_APERF 0x000000E8
33
34#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
35
36// DFE: This constant comes from older xnu:
37#define CLKNUM1193182/* formerly 1193167 */
38
39// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM
40#define CALIBRATE_TIME_MSEC30/* 30 msecs */
41#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
42
43static inline uint64_t rdtsc64(void)
44{
45uint64_t ret;
46__asm__ volatile("rdtsc" : "=A" (ret));
47return ret;
48}
49
50static inline uint64_t rdmsr64(uint32_t msr)
51{
52 uint64_t ret;
53 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
54 return ret;
55}
56
57static inline void wrmsr64(uint32_t msr, uint64_t val)
58{
59__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));
60}
61
62static inline void intel_waitforsts(void) {
63uint32_t inline_timeout = 100000;
64while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }
65}
66
67static inline void do_cpuid(uint32_t selector, uint32_t *data)
68{
69asm volatile ("cpuid"
70 : "=a" (data[0]),
71 "=b" (data[1]),
72 "=c" (data[2]),
73 "=d" (data[3])
74 : "a" (selector));
75}
76
77static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)
78{
79asm volatile ("cpuid"
80 : "=a" (data[0]),
81 "=b" (data[1]),
82 "=c" (data[2]),
83 "=d" (data[3])
84 : "a" (selector), "c" (selector2));
85}
86
87// DFE: enable_PIT2 and disable_PIT2 come from older xnu
88
89/*
90 * Enable or disable timer 2.
91 * Port 0x61 controls timer 2:
92 * bit 0 gates the clock,
93 * bit 1 gates output to speaker.
94 */
95static inline void enable_PIT2(void)
96{
97 /* Enable gate, disable speaker */
98 __asm__ volatile(
99 " inb $0x61,%%al \n\t"
100 " and $0xFC,%%al \n\t" /* & ~0x03 */
101 " or $1,%%al \n\t"
102 " outb %%al,$0x61 \n\t"
103 : : : "%al" );
104}
105
106static inline void disable_PIT2(void)
107{
108 /* Disable gate and output to speaker */
109 __asm__ volatile(
110 " inb $0x61,%%al \n\t"
111 " and $0xFC,%%al \n\t"/* & ~0x03 */
112 " outb %%al,$0x61 \n\t"
113 : : : "%al" );
114}
115
116// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are
117// roughly based on Linux code
118
119/* Set the 8254 channel 2 to mode 0 with the specified value.
120 In mode 0, the counter will initially set its gate low when the
121 timer expires. For this to be useful, you ought to set it high
122 before calling this function. The enable_PIT2 function does this.
123 */
124static inline void set_PIT2_mode0(uint16_t value)
125{
126 __asm__ volatile(
127 " movb $0xB0,%%al \n\t"
128 " outb%%al,$0x43\n\t"
129 " movb%%dl,%%al\n\t"
130 " outb%%al,$0x42\n\t"
131 " movb%%dh,%%al\n\t"
132 " outb%%al,$0x42"
133 : : "d"(value) /*: no clobber */ );
134}
135
136/* Returns the number of times the loop ran before the PIT2 signaled */
137static inline unsigned long poll_PIT2_gate(void)
138{
139 unsigned long count = 0;
140 unsigned char nmi_sc_val;
141 do {
142 ++count;
143 __asm__ volatile(
144 "inb$0x61,%0"
145 : "=a"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);
146 } while( (nmi_sc_val & 0x20) == 0);
147 return count;
148}
149
150inline static void
151set_PIT2(int value)
152{
153/*
154 * First, tell the clock we are going to write 16 bits to the counter
155 * and enable one-shot mode (command 0xB8 to port 0x43)
156 * Then write the two bytes into the PIT2 clock register (port 0x42).
157 * Loop until the value is "realized" in the clock,
158 * this happens on the next tick.
159 */
160 asm volatile(
161 " movb $0xB8,%%al \n\t"
162 " outb %%al,$0x43 \n\t"
163 " movb %%dl,%%al \n\t"
164 " outb %%al,$0x42 \n\t"
165 " movb %%dh,%%al \n\t"
166 " outb %%al,$0x42 \n"
167"1: inb $0x42,%%al \n\t"
168 " inb $0x42,%%al \n\t"
169 " cmp %%al,%%dh \n\t"
170 " jne 1b"
171 : : "d"(value) : "%al");
172}
173
174
175inline static uint64_t
176get_PIT2(unsigned int *value)
177{
178 register uint64_t result;
179/*
180 * This routine first latches the time (command 0x80 to port 0x43),
181 * then gets the time stamp so we know how long the read will take later.
182 * Read (from port 0x42) and return the current value of the timer.
183 */
184#ifdef __i386__
185 asm volatile(
186 " xorl %%ecx,%%ecx \n\t"
187 " movb $0x80,%%al \n\t"
188 " outb %%al,$0x43 \n\t"
189 " rdtsc \n\t"
190 " pushl %%eax \n\t"
191 " inb $0x42,%%al \n\t"
192 " movb %%al,%%cl \n\t"
193 " inb $0x42,%%al \n\t"
194 " movb %%al,%%ch \n\t"
195 " popl %%eax "
196 : "=A"(result), "=c"(*value));
197#else /* __x86_64__ */
198 asm volatile(
199" xorq %%rcx,%%rcx \n\t"
200" movb $0x80,%%al \n\t"
201" outb %%al,$0x43 \n\t"
202" rdtsc \n\t"
203" pushq %%rax \n\t"
204" inb $0x42,%%al \n\t"
205" movb %%al,%%cl \n\t"
206" inb $0x42,%%al \n\t"
207" movb %%al,%%ch \n\t"
208" popq %%rax "
209: "=A"(result), "=c"(*value));
210#endif
211
212 return result;
213}
214
215#endif /* !__LIBSAIO_CPU_H */
216

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