1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #ifndef __LIBSAIO_CPU_H␊ |
7 | #define __LIBSAIO_CPU_H␊ |
8 | ␊ |
9 | #include "platform.h"␊ |
10 | ␊ |
11 | extern void scan_cpu(PlatformInfo_t *);␊ |
12 | ␊ |
13 | #define bit(n)␉␉␉(1ULL << (n))␊ |
14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
16 | ␊ |
17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
18 | ␊ |
19 | #define␉MSR_IA32_PERF_STATUS␉0x00000198␊ |
20 | #define MSR_IA32_PERF_CONTROL␉0x199␊ |
21 | #define MSR_IA32_EXT_CONFIG␉0x00EE␊ |
22 | #define MSR_FLEX_RATIO␉␉0x194␊ |
23 | #define MSR_TURBO_RATIO_LIMIT␉0x1AD␊ |
24 | #define␉MSR_PLATFORM_INFO␉0xCE␊ |
25 | #define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊ |
26 | #define MSR_IA32_PLATFORM_ID␉0x17␊ |
27 | ␊ |
28 | /*␊ |
29 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
30 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
31 | */␊ |
32 | #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
33 | #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
34 | #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
35 | #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
36 | #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
37 | #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
38 | #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
39 | #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
40 | #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
41 | #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
42 | #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
43 | #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
44 | #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
45 | #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
46 | #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
47 | #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
48 | #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
49 | #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
50 | #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
51 | #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
52 | #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
53 | #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
54 | #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
55 | #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
56 | #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
57 | #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
58 | #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
59 | #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
60 | #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
61 | ␊ |
62 | #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
63 | #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
64 | #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
65 | #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
66 | #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
67 | #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
68 | #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
69 | #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
70 | #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
71 | #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
72 | #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
73 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
74 | #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊ |
75 | #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
76 | #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
77 | #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
78 | ␊ |
79 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
80 | #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
81 | #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
82 | #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
83 | #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊ |
84 | #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
85 | #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
86 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
87 | #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
88 | #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
89 | #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
90 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
91 | #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
92 | #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
93 | #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
94 | ␊ |
95 | /*␊ |
96 | * Leaf 7, subleaf 0 additional features.␊ |
97 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
98 | */␊ |
99 | #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
100 | #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊ |
101 | #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
102 | #define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊ |
103 | #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊ |
104 | #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
105 | #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
106 | #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
107 | #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊ |
108 | #define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊ |
109 | ␊ |
110 | /*␊ |
111 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
112 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
113 | */␊ |
114 | #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
115 | #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
116 | ␊ |
117 | #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
118 | #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
119 | #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
120 | ␊ |
121 | #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
122 | ␊ |
123 | /*␊ |
124 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
125 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
126 | */␊ |
127 | #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
128 | ␊ |
129 | #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
130 | ␊ |
131 | #define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊ |
132 | #define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊ |
133 | ␊ |
134 | //-- processor type -> p_type:␊ |
135 | #define PT_OEM␉0x00␉// Intel Original OEM Processor;␊ |
136 | #define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊ |
137 | #define PT_DUAL␉0x02␉// Intel Dual Processor;␊ |
138 | #define PT_RES␉0x03␉// Intel Reserved;␊ |
139 | ␊ |
140 | /* Known MSR registers */␊ |
141 | #define MSR_IA32_PLATFORM_ID 0x0017␊ |
142 | #define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊ |
143 | #define IA32_TSC_ADJUST 0x003B␊ |
144 | #define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊ |
145 | #define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊ |
146 | #define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
147 | /* turbo for penryn */␊ |
148 | #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊ |
149 | #define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊ |
150 | #define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊ |
151 | #define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊ |
152 | #define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊ |
153 | #define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊ |
154 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
155 | #define␉MSR_IA32_PERF_STATUS 0x0198␊ |
156 | #define MSR_IA32_PERF_CONTROL 0x0199␊ |
157 | #define MSR_IA32_CLOCK_MODULATION 0x019A␊ |
158 | #define MSR_THERMAL_STATUS 0x019C␊ |
159 | #define MSR_IA32_MISC_ENABLE 0x01A0␊ |
160 | #define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊ |
161 | #define MSR_MISC_PWR_MGMT 0x01AA␊ |
162 | #define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊ |
163 | ␊ |
164 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
165 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
166 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
167 | #define MSR_POWER_CTL␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊ |
168 | ␊ |
169 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
170 | #define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊ |
171 | //MSR 00000606 0000-0000-000A-1003␊ |
172 | #define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */␊ |
173 | // bit 15 = 1 -- the value valid for C-state PM␊ |
174 | #define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */␊ |
175 | //MSR 0000060B 0000-0000-0000-8854␊ |
176 | //Valid + 010=1024ns + 0x54=84mks␊ |
177 | #define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */␊ |
178 | //MSR 0000060C 0000-0000-0000-8854␊ |
179 | #define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */␊ |
180 | ␊ |
181 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊ |
182 | #define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊ |
183 | #define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊ |
184 | ␊ |
185 | //AMD␊ |
186 | #define K8_FIDVID_STATUS 0xC0010042␊ |
187 | #define K10_COFVID_LIMIT 0xC0010061␊ |
188 | #define K10_PSTATE_STATUS 0xC0010064␊ |
189 | #define K10_COFVID_STATUS 0xC0010071␊ |
190 | ␊ |
191 | #define MSR_AMD_MPERF 0x000000E7␊ |
192 | #define MSR_AMD_APERF 0x000000E8␊ |
193 | ␊ |
194 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
195 | ␊ |
196 | // DFE: This constant comes from older xnu:␊ |
197 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
198 | ␊ |
199 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
200 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
201 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
202 | ␊ |
203 | static inline uint64_t rdtsc64(void)␊ |
204 | {␊ |
205 | ␉uint64_t ret;␊ |
206 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
207 | ␉return ret;␊ |
208 | }␊ |
209 | ␊ |
210 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
211 | {␊ |
212 | uint64_t ret;␊ |
213 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
214 | return ret;␊ |
215 | }␊ |
216 | ␊ |
217 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
218 | {␊ |
219 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
220 | }␊ |
221 | ␊ |
222 | static inline void intel_waitforsts(void) {␊ |
223 | ␉uint32_t inline_timeout = 100000;␊ |
224 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
225 | }␊ |
226 | ␊ |
227 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
228 | {␊ |
229 | ␉asm volatile ("cpuid"␊ |
230 | ␉␉␉␉ : "=a" (data[0]),␊ |
231 | ␉␉␉␉ "=b" (data[1]),␊ |
232 | ␉␉␉␉ "=c" (data[2]),␊ |
233 | ␉␉␉␉ "=d" (data[3])␊ |
234 | ␉␉␉␉ : "a" (selector));␊ |
235 | }␊ |
236 | ␊ |
237 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
238 | {␊ |
239 | ␉asm volatile ("cpuid"␊ |
240 | ␉␉␉␉ : "=a" (data[0]),␊ |
241 | ␉␉␉␉ "=b" (data[1]),␊ |
242 | ␉␉␉␉ "=c" (data[2]),␊ |
243 | ␉␉␉␉ "=d" (data[3])␊ |
244 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
245 | }␊ |
246 | ␊ |
247 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
248 | ␊ |
249 | /*␊ |
250 | * Enable or disable timer 2.␊ |
251 | * Port 0x61 controls timer 2:␊ |
252 | * bit 0 gates the clock,␊ |
253 | * bit 1 gates output to speaker.␊ |
254 | */␊ |
255 | static inline void enable_PIT2(void)␊ |
256 | {␊ |
257 | /* Enable gate, disable speaker */␊ |
258 | __asm__ volatile(␊ |
259 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
260 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
261 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
262 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
263 | ␉␉␉␉␉ : : : "%al" );␊ |
264 | }␊ |
265 | ␊ |
266 | static inline void disable_PIT2(void)␊ |
267 | {␊ |
268 | /* Disable gate and output to speaker */␊ |
269 | __asm__ volatile(␊ |
270 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
271 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
272 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
273 | ␉␉␉␉␉ : : : "%al" );␊ |
274 | }␊ |
275 | ␊ |
276 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
277 | // roughly based on Linux code␊ |
278 | ␊ |
279 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
280 | In mode 0, the counter will initially set its gate low when the␊ |
281 | timer expires. For this to be useful, you ought to set it high␊ |
282 | before calling this function. The enable_PIT2 function does this.␊ |
283 | */␊ |
284 | static inline void set_PIT2_mode0(uint16_t value)␊ |
285 | {␊ |
286 | __asm__ volatile(␊ |
287 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
288 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
289 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
290 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
291 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
292 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
293 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
294 | }␊ |
295 | ␊ |
296 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
297 | static inline unsigned long poll_PIT2_gate(void)␊ |
298 | {␊ |
299 | unsigned long count = 0;␊ |
300 | unsigned char nmi_sc_val;␊ |
301 | do {␊ |
302 | ++count;␊ |
303 | __asm__ volatile(␊ |
304 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
305 | ␉␉␉␉␉␉ : "=a"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
306 | } while( (nmi_sc_val & 0x20) == 0);␊ |
307 | return count;␊ |
308 | }␊ |
309 | ␊ |
310 | inline static void␊ |
311 | set_PIT2(int value)␊ |
312 | {␊ |
313 | /*␊ |
314 | * First, tell the clock we are going to write 16 bits to the counter␊ |
315 | * and enable one-shot mode (command 0xB8 to port 0x43)␊ |
316 | * Then write the two bytes into the PIT2 clock register (port 0x42).␊ |
317 | * Loop until the value is "realized" in the clock,␊ |
318 | * this happens on the next tick.␊ |
319 | */␊ |
320 | asm volatile(␊ |
321 | " movb $0xB8,%%al \n\t"␊ |
322 | " outb %%al,$0x43 \n\t"␊ |
323 | " movb %%dl,%%al \n\t"␊ |
324 | " outb %%al,$0x42 \n\t"␊ |
325 | " movb %%dh,%%al \n\t"␊ |
326 | " outb %%al,$0x42 \n"␊ |
327 | "1: inb $0x42,%%al \n\t" ␊ |
328 | " inb $0x42,%%al \n\t"␊ |
329 | " cmp %%al,%%dh \n\t"␊ |
330 | " jne 1b"␊ |
331 | : : "d"(value) : "%al");␊ |
332 | }␊ |
333 | ␊ |
334 | ␊ |
335 | inline static uint64_t␊ |
336 | get_PIT2(unsigned int *value)␊ |
337 | {␊ |
338 | register uint64_t result;␊ |
339 | /*␊ |
340 | * This routine first latches the time (command 0x80 to port 0x43),␊ |
341 | * then gets the time stamp so we know how long the read will take later.␊ |
342 | * Read (from port 0x42) and return the current value of the timer.␊ |
343 | */␊ |
344 | #ifdef __i386__␊ |
345 | asm volatile(␊ |
346 | " xorl %%ecx,%%ecx \n\t"␊ |
347 | " movb $0x80,%%al \n\t"␊ |
348 | " outb %%al,$0x43 \n\t"␊ |
349 | " rdtsc \n\t"␊ |
350 | " pushl %%eax \n\t"␊ |
351 | " inb $0x42,%%al \n\t"␊ |
352 | " movb %%al,%%cl \n\t"␊ |
353 | " inb $0x42,%%al \n\t"␊ |
354 | " movb %%al,%%ch \n\t"␊ |
355 | " popl %%eax "␊ |
356 | : "=A"(result), "=c"(*value));␊ |
357 | #else /* __x86_64__ */␊ |
358 | asm volatile(␊ |
359 | ␉␉" xorq %%rcx,%%rcx \n\t"␊ |
360 | ␉␉" movb $0x80,%%al \n\t"␊ |
361 | ␉␉" outb %%al,$0x43 \n\t"␊ |
362 | ␉␉" rdtsc \n\t"␊ |
363 | ␉␉" pushq %%rax \n\t"␊ |
364 | ␉␉" inb $0x42,%%al \n\t"␊ |
365 | ␉␉" movb %%al,%%cl \n\t"␊ |
366 | ␉␉" inb $0x42,%%al \n\t"␊ |
367 | ␉␉" movb %%al,%%ch \n\t"␊ |
368 | ␉␉" popq %%rax "␊ |
369 | ␉␉: "=A"(result), "=c"(*value));␊ |
370 | #endif␊ |
371 | ␊ |
372 | return result;␊ |
373 | }␊ |
374 | ␊ |
375 | #endif /* !__LIBSAIO_CPU_H */␊ |
376 | |