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Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_HASWELL:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
38␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
39␊
40␉␉␉␉␉␉value->word = 0;␊
41␉␉␉␉␉␉break;␊
42␉␉␉␉␉default:␊
43␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
44␉␉␉␉}␊
45␉␉␉}␊
46␉␉␉␉break;␊
47␊
48␉␉␉default:␊
49␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉}␊
51␉} else {␊
52␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
53␉}␊
54␊
55␉return true;␊
56}␊
57␊
58bool getProcessorInformationMaximumClock(returnType *value)␊
59{␊
60␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
61␉return true;␊
62}␊
63␊
64bool getSMBOemProcessorBusSpeed(returnType *value)␊
65{␊
66␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
67␉␉switch (Platform.CPU.Family) {␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model) {␊
71␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case 0x19:␊
80␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_DALES:␊
83␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
84␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
86␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
87␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
88␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
89␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
90␉␉␉␉␉case CPU_MODEL_HASWELL:␊
91␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
92␉␉␉␉␉{␊
93␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
94␉␉␉␉␉␉int nhm_bus = 0x3F;␊
95␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
96␉␉␉␉␉␉unsigned long did, vid;␊
97␉␉␉␉␉␉unsigned int i;␊
98␉␉␉␉␉␉␊
99␉␉␉␉␉␉// Nehalem supports Scrubbing␊
100␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
101␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
102␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
103␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
104␉␉␉␉␉␉␉vid &= 0xFFFF;␊
105␉␉␉␉␉␉␉did &= 0xFF00;␊
106␉␉␉␉␉␉␉␊
107␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
108␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
109␉␉␉␉␉␉␉}␊
110␉␉␉␉␉␉}␊
111␊
112␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
113␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
114␉␉␉␉␉␉qpimult &= 0x7F;␊
115␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
116␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
117␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
118␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
119␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
120␉␉␉␉␉␉}␊
121␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
122␉␉␉␉␉␉value->word = qpibusspeed;␊
123␉␉␉␉␉␉return true;␊
124␉␉␉␉␉}␊
125␉␉␉␉␉default:␊
126␉␉␉␉␉␉break; //Unsupported CPU type␊
127␉␉␉␉}␊
128␉␉␉}␊
129␉␉␉default:␊
130␉␉␉␉break;␊
131␉␉}␊
132␉}␊
133␉return false;␊
134}␊
135␊
136uint16_t simpleGetSMBOemProcessorType(void)␊
137{␊
138␉if (Platform.CPU.NoCores >= 4) {␊
139␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊
140␉} else if (Platform.CPU.NoCores == 1) {␊
141␉␉return 0x201;␉// 513 - Core Solo␊
142␉};␊
143␉␊
144␉return 0x301;␉␉// 769 - Core 2 Duo␊
145}␊
146␊
147bool getSMBOemProcessorType(returnType *value)␊
148{␊
149␉static bool done = false;␊
150␊
151␉value->word = simpleGetSMBOemProcessorType();␊
152␊
153␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
154␉␉if (!done) {␊
155␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
156␉␉␉done = true;␊
157␉␉}␊
158␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
159␉␉switch (Platform.CPU.Family) {␊
160␉␉␉case 0x06:␊
161␉␉␉{␊
162␉␉␉␉switch (Platform.CPU.Model) {␊
163␊
164␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
165␉␉␉␉␉␉value->word = 0x101;␉␉␉// 257␊
166␉␉␉␉␉␉return true;␊
167␊
168␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
169␉␉␉␉␉case CPU_MODEL_CELERON:␊
170␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
171␉␉␉␉␉␉return true;␊
172␊
173␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
174␉␉␉␉␉␉value->word = 0x401;␉␉␉// 1025␊
175␉␉␉␉␉␉return true;␊
176␊
177␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
178␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
179␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
180␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊
181␉␉␉␉␉␉}␊
182␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
183␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
184␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
185␉␉␉␉␉␉return true;␊
186␊
187␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
188␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
189␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
190␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
191␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
192␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
193␉␉␉␉␉␉␉return true;␊
194␉␉␉␉␉␉}␊
195␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
196␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
197␉␉␉␉␉␉␉return true;␊
198␉␉␉␉␉␉}␊
199␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
200␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
201␉␉␉␉␉␉␉return true;␊
202␉␉␉␉␉␉}␊
203␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
204␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
205␉␉␉␉␉␉␉return true;␊
206␉␉␉␉␉␉}␊
207␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
208␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
209␉␉␉␉␉␉}␊
210␉␉␉␉␉␉return true;␊
211␊
212␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
213␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
214␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
215␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
216␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
217␉␉␉␉␉␉␉return true;␊
218␉␉␉␉␉␉}␊
219␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
220␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
221␉␉␉␉␉␉␉return true;␊
222␉␉␉␉␉␉}␊
223␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
224␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
225␉␉␉␉␉␉␉return true;␊
226␉␉␉␉␉␉}␊
227␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
228␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
229␉␉␉␉␉␉␉return true;␊
230␉␉␉␉␉␉}␊
231␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
232␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉return true;␊
235␊
236␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
237␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
238␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
239␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
240␉␉␉␉␉␉␉return true;␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
243␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
244␉␉␉␉␉␉␉return true;␊
245␉␉␉␉␉␉}␊
246␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
247␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
248␉␉␉␉␉␉␉return true;␊
249␉␉␉␉␉␉}␊
250␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
251␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
252␉␉␉␉␉␉␉return true;␊
253␉␉␉␉␉␉}␊
254␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
255␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉return true;␊
258␊
259␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
260␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
261␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
262␉␉␉␉␉␉␉return true;␊
263␉␉␉␉␉␉}␊
264␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
265␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
266␉␉␉␉␉␉␉return true;␊
267␉␉␉␉␉␉}␊
268␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
269␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
270␉␉␉␉␉␉␉return true;␊
271␉␉␉␉␉␉}␊
272␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
273␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
274␉␉␉␉␉␉␉return true;␊
275␉␉␉␉␉␉}␊
276␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
277␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
278␉␉␉␉␉␉}␊
279␉␉␉␉␉␉return true;␊
280␊
281␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
282␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561␊
283␉␉␉␉␉␉return true;␊
284␊
285␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
286␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
287␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
288␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
289␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
290␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
291␉␉␉␉␉␉␉return true;␊
292␉␉␉␉␉␉}␊
293␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
294␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
295␉␉␉␉␉␉␉return true;␊
296␉␉␉␉␉␉}␊
297␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
298␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
299␉␉␉␉␉␉␉return true;␊
300␉␉␉␉␉␉}␊
301␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
302␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
303␉␉␉␉␉␉␉return true;␊
304␉␉␉␉␉␉}␊
305␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
306␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉␉return true;␊
309␊
310␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
311␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
312␉␉␉␉␉␉return true;␊
313␊
314␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
315␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
316␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
317␉␉␉␉␉␉return true;␊
318␉␉␉␉␉default:␊
319␉␉␉␉␉␉break; //Unsupported CPU type␊
320␉␉␉␉}␊
321␉␉␉}␊
322␉␉␉default:␊
323␉␉␉␉break;␊
324␉␉}␊
325␉}␊
326␉␊
327␉return false;␊
328}␊
329␊
330bool getSMBMemoryDeviceMemoryType(returnType *value)␊
331{␊
332␉static int idx = -1;␊
333␉int␉map;␊
334␊
335␉idx++;␊
336␉if (idx < MAX_RAM_SLOTS) {␊
337␉␉map = Platform.DMI.DIMM[idx];␊
338␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
339␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
340␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
341␉␉␉return true;␊
342␉␉}␊
343␉}␊
344␊
345␉return false;␊
346//␉value->byte = SMB_MEM_TYPE_DDR2;␊
347//␉return true;␊
348}␊
349␊
350bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
351{␊
352␉value->word = 0xFFFF;␊
353␉return true;␊
354}␊
355␊
356bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
357{␊
358␉static int idx = -1;␊
359␉int␉map;␊
360␊
361␉idx++;␊
362␉if (idx < MAX_RAM_SLOTS) {␊
363␉␉map = Platform.DMI.DIMM[idx];␊
364␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
365␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
366␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
367␉␉␉return true;␊
368␉␉}␊
369␉}␊
370␊
371␉return false;␊
372//␉value->dword = 800;␊
373//␉return true;␊
374}␊
375␊
376bool getSMBMemoryDeviceManufacturer(returnType *value)␊
377{␊
378␉static int idx = -1;␊
379␉int␉map;␊
380␊
381␉idx++;␊
382␉if (idx < MAX_RAM_SLOTS) {␊
383␉␉map = Platform.DMI.DIMM[idx];␊
384␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
385␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
386␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
387␉␉␉return true;␊
388␉␉}␊
389␉}␊
390␊
391␉if (!bootInfo->memDetect) {␊
392␉␉return false;␊
393␉}␊
394␉value->string = NOT_AVAILABLE;␊
395␉return true;␊
396}␊
397␊
398bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
399{␊
400␉static int idx = -1;␊
401␉int␉map;␊
402␊
403␉idx++;␊
404␊
405␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
406␊
407␉if (idx < MAX_RAM_SLOTS) {␊
408␉␉map = Platform.DMI.DIMM[idx];␊
409␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
410␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
411␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
412␉␉␉return true;␊
413␉␉}␊
414␉}␊
415␊
416␉if (!bootInfo->memDetect) {␊
417␉␉return false;␊
418␉}␊
419␉value->string = NOT_AVAILABLE;␊
420␉return true;␊
421}␊
422␊
423bool getSMBMemoryDevicePartNumber(returnType *value)␊
424{␊
425␉static int idx = -1;␊
426␉int␉map;␊
427␊
428␉idx++;␊
429␉if (idx < MAX_RAM_SLOTS) {␊
430␉␉map = Platform.DMI.DIMM[idx];␊
431␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
432␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
433␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
434␉␉␉return true;␊
435␉␉}␊
436␉}␊
437␊
438␉if (!bootInfo->memDetect) {␊
439␉␉return false;␊
440␉}␊
441␉value->string = NOT_AVAILABLE;␊
442␉return true;␊
443}␊
444␊
445␊
446// getting smbios addr with fast compare ops, late checksum testing ...␊
447#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
448static const char * const SMTAG = "_SM_";␊
449static const char* const DMITAG = "_DMI_";␊
450␊
451SMBEntryPoint *getAddressOfSmbiosTable(void)␊
452{␊
453␉SMBEntryPoint␉*smbios;␊
454␉/*␊
455␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
456␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
457␉ */␊
458␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
459␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
460␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
461␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
462␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
463␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
464␉␉␉return smbios;␊
465␉ }␊
466␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
467␉}␊
468␉printf("ERROR: Unable to find SMBIOS!\n");␊
469␉pause();␊
470␉return NULL;␊
471}␊
472␊
473

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