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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_HASWELL:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
38␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
39␊
40␉␉␉␉␉␉value->word = 0;␊
41␉␉␉␉␉␉break;␊
42␉␉␉␉␉default:␊
43␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
44␉␉␉␉}␊
45␉␉␉}␊
46␉␉␉␉break;␊
47␊
48␉␉␉default:␊
49␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉}␊
51␉} else {␊
52␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
53␉}␊
54␊
55␉return true;␊
56}␊
57␊
58bool getProcessorInformationMaximumClock(returnType *value)␊
59{␊
60␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
61␉return true;␊
62}␊
63␊
64bool getSMBOemProcessorBusSpeed(returnType *value)␊
65{␊
66␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
67␉␉switch (Platform.CPU.Family) {␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model) {␊
71␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case 0x19:␊
80␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_DALES:␊
83␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
84␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
86␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
87␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
88␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
89␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
90␉␉␉␉␉case CPU_MODEL_HASWELL:␊
91␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
92␉␉␉␉␉{␊
93␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
94␉␉␉␉␉␉int nhm_bus = 0x3F;␊
95␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
96␉␉␉␉␉␉unsigned long did, vid;␊
97␉␉␉␉␉␉unsigned int i;␊
98␉␉␉␉␉␉␊
99␉␉␉␉␉␉// Nehalem supports Scrubbing␊
100␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
101␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
102␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
103␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
104␉␉␉␉␉␉␉vid &= 0xFFFF;␊
105␉␉␉␉␉␉␉did &= 0xFF00;␊
106␉␉␉␉␉␉␉␊
107␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
108␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
109␉␉␉␉␉␉␉}␊
110␉␉␉␉␉␉}␊
111␊
112␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
113␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
114␉␉␉␉␉␉qpimult &= 0x7F;␊
115␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
116␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
117␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
118␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
119␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
120␉␉␉␉␉␉}␊
121␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
122␉␉␉␉␉␉value->word = qpibusspeed;␊
123␉␉␉␉␉␉return true;␊
124␉␉␉␉␉}␊
125␉␉␉␉␉default:␊
126␉␉␉␉␉␉break; //Unsupported CPU type␊
127␉␉␉␉}␊
128␉␉␉}␊
129␉␉␉default:␊
130␉␉␉␉break;␊
131␉␉}␊
132␉}␊
133␉return false;␊
134}␊
135␊
136uint16_t simpleGetSMBOemProcessorType(void)␊
137{␊
138␉if (Platform.CPU.NoCores >= 4) {␊
139␉␉return 0x0501;␉// 1281 - Quad-Core Xeon␊
140␉} else if (Platform.CPU.NoCores == 1) {␊
141␉␉return 0x0201;␉// // 513 - Core Duo␊
142␉};␊
143␉␊
144␉return 0x0301;␉␉// 769 - Core 2 Duo␊
145}␊
146␊
147bool getSMBOemProcessorType(returnType *value)␊
148{␊
149␉static bool done = false;␊
150␊
151␉value->word = simpleGetSMBOemProcessorType();␊
152␊
153␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
154␉␉if (!done) {␊
155␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
156␉␉␉done = true;␊
157␉␉}␊
158␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
159␉␉switch (Platform.CPU.Family) {␊
160 case 0x0F:␊
161␉␉␉case 0x06:␊
162␉␉␉{␊
163␉␉␉␉switch (Platform.CPU.Model) {␊
164 case CPU_MODEL_PENTIUM_M:␊
165␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
166 case CPU_MODEL_PRESCOTT:␊
167 case CPU_MODEL_NOCONA:␊
168 return true;␊
169 ␊
170␉␉␉␉␉case CPU_MODEL_PRESLER:␊
171 case CPU_MODEL_CELERON:␊
172 case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
173␉␉␉␉␉␉value->word = 0x201; // 513␊
174␉␉␉␉␉␉return true;␊
175 ␊
176␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
177 case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
178␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
179␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
180␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊
181 return true;␊
182␉␉␉␉␉␉}␊
183 if (Platform.CPU.NoCores <= 2) {␊
184␉␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769 - Core 2 Duo␊
185␉␉␉␉␉␉} else {␊
186 value->word = 0x402;␉␉␉// 1026 - Core 2 Quad as Xeon␊
187 }␊
188␉␉␉␉␉␉return true;␊
189 ␊
190␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
191␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
192␉␉␉␉␉␉return true;␊
193␊
194␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
195␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
196␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
197␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
198 if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
199␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// // 1281 - Lynnfiled Quad-Core Xeon␊
200 return true;␊
201␉␉␉␉␉␉}␊
202␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
203␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
204 return true;␊
205␉␉␉␉␉␉}␊
206␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
207␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
208 return true;␊
209␉␉␉␉␉␉}␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
211␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
212 return true;␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
215␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// 1537 - Core i3␊
216␉␉␉␉␉␉}␊
217␉␉␉␉␉␉return true;␊
218␊
219␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
220 case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
221 case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
222 if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
223␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
224 return true;␊
225␉␉␉␉␉␉}␊
226␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
227␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
228 return true;␊
229␉␉␉␉␉␉}␊
230␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
231␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
232 return true;␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
235␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 - Core i7␊
236 return true;␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
239␉␉␉␉␉␉␉value->word = 0x901;␉␉// 1538 - Core i3␊
240␉␉␉␉␉␉}␊
241␉␉␉␉␉␉return true;␊
242␊
243␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
244␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
245␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
246␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
247 return true;␊
248␉␉␉␉␉␉}␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
250␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 - Core i3␊
251 return true;␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
254␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
255 return true;␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
258␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
259 return true;␊
260␉␉␉␉␉␉}␊
261␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
262␉␉␉␉␉␉␉value->word = 0x902;␉␉// 1539 - Core i3␊
263␉␉␉␉␉␉}␊
264␉␉␉␉␉␉return true;␊
265␊
266␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
267 if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
268␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
269 return true;␊
270␉␉␉␉␉␉}␊
271␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
272␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it - but we yes:-)␊
273 return true;␊
274␉␉␉␉␉␉}␊
275␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
276␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
277 return true;␊
278␉␉␉␉␉␉}␊
279␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
280␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
281 return true;␊
282␉␉␉␉␉␉}␊
283␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
284␉␉␉␉␉␉␉value->word = 0x903;␉␉// 1540 - Core i3␊
285␉␉␉␉␉␉}␊
286␉␉␉␉␉␉return true;␊
287␊
288␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
289␉␉␉␉␉␉value->word = 0xA01; // 2561 - Xeon␊
290␉␉␉␉␉␉return true;␊
291␊
292␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
293␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
294␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
295␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
296 if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
297␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
298 return true;␊
299␉␉␉␉␉␉}␊
300␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
301␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
302 return true;␊
303␉␉␉␉␉␉}␊
304␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
305␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
306 return true;␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
309␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
310 return true;␊
311␉␉␉␉␉␉}␊
312␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
313␉␉␉␉␉␉␉value->word = 0x904;␉␉// 1541 - Core i3␊
314␉␉␉␉␉␉}␊
315␉␉␉␉␉␉return true;␊
316␊
317␉␉␉␉␉case 0x15: // EP80579 integrated processor␊
318␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
319␉␉␉␉␉␉return true;␊
320␊
321␉␉␉␉␉case 0x13: // Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
322␉␉␉␉␉case 0x19: // Intel Core i5 650 @3.20 Ghz␊
323␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
324␉␉␉␉␉␉return true;␊
325␉␉␉␉␉default:␊
326␉␉␉␉␉␉break; // Unsupported CPU type␊
327␉␉␉␉}␊
328␉␉␉}␊
329␉␉␉default:␊
330␉␉␉␉break;␊
331␉␉}␊
332␉}␊
333␉␊
334␉return false;␊
335}␊
336␊
337bool getSMBMemoryDeviceMemoryType(returnType *value)␊
338{␊
339␉static int idx = -1;␊
340␉int␉map;␊
341␊
342 if (!bootInfo->memDetect) {␊
343␉␉return false;␊
344␉}␊
345 ␊
346␉idx++;␊
347␉if (idx < MAX_RAM_SLOTS) {␊
348␉␉map = Platform.DMI.DIMM[idx];␊
349␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
350␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
351␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
352␉␉␉return true;␊
353␉␉}␊
354␉}␊
355␊
356 value->byte = 2; // means Unknown␊
357␉return true;␊
358//␉value->byte = SMB_MEM_TYPE_DDR2;␊
359//␉return true;␊
360}␊
361␊
362bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
363{␊
364␉value->word = 0xFFFF;␊
365␉return true;␊
366}␊
367␊
368bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
369{␊
370␉static int idx = -1;␊
371␉int␉map;␊
372␊
373 if (!bootInfo->memDetect) {␊
374␉␉return false;␊
375␉}␊
376 ␊
377␉idx++;␊
378␉if (idx < MAX_RAM_SLOTS) {␊
379␉␉map = Platform.DMI.DIMM[idx];␊
380␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
381␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
382␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
383␉␉␉return true;␊
384␉␉}␊
385␉}␊
386␊
387 value->dword = 0; // means Unknown␊
388␉return true;␊
389//␉value->dword = 800;␊
390//␉return true;␊
391}␊
392␊
393bool getSMBMemoryDeviceManufacturer(returnType *value)␊
394{␊
395␉static int idx = -1;␊
396␉int␉map;␊
397␊
398 if (!bootInfo->memDetect) {␊
399␉␉return false;␊
400␉}␊
401 ␊
402␉idx++;␊
403␉if (idx < MAX_RAM_SLOTS) {␊
404␉␉map = Platform.DMI.DIMM[idx];␊
405␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
406␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
407␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
408␉␉␉return true;␊
409␉␉}␊
410␉}␊
411␊
412␉value->string = NOT_AVAILABLE;␊
413␉return true;␊
414}␊
415␊
416bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
417{␊
418␉static int idx = -1;␊
419␉int␉map;␊
420␊
421 if (!bootInfo->memDetect) {␊
422␉␉return false;␊
423␉}␊
424 ␊
425␉idx++;␊
426␉// DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
427␉if (idx < MAX_RAM_SLOTS) {␊
428␉␉map = Platform.DMI.DIMM[idx];␊
429␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
430␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
431␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
432␉␉␉return true;␊
433␉␉}␊
434␉}␊
435␊
436␉value->string = NOT_AVAILABLE;␊
437␉return true;␊
438}␊
439␊
440bool getSMBMemoryDevicePartNumber(returnType *value)␊
441{␊
442␉static int idx = -1;␊
443␉int␉map;␊
444␊
445 if (!bootInfo->memDetect) {␊
446␉␉return false;␊
447␉}␊
448 ␊
449␉idx++;␊
450␉if (idx < MAX_RAM_SLOTS) {␊
451␉␉map = Platform.DMI.DIMM[idx];␊
452␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
453␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
454␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
455␉␉␉return true;␊
456␉␉}␊
457␉}␊
458␊
459␉value->string = NOT_AVAILABLE;␊
460␉return true;␊
461}␊
462␊
463␊
464// getting smbios addr with fast compare ops, late checksum testing ...␊
465#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
466static const char * const SMTAG = "_SM_";␊
467static const char* const DMITAG = "_DMI_";␊
468␊
469SMBEntryPoint *getAddressOfSmbiosTable(void)␊
470{␊
471␉SMBEntryPoint␉*smbios;␊
472␉/*␊
473␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
474␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
475␉ */␊
476␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
477␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
478␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
479␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
480␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
481␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
482␉␉␉return smbios;␊
483␉ }␊
484␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
485␉}␊
486␉printf("ERROR: Unable to find SMBIOS!\n");␊
487␉pause();␊
488␉return NULL;␊
489}␊
490␊
491

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