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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
38␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
39␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
40␊
41␉␉␉␉␉␉value->word = 0;␊
42␉␉␉␉␉␉break;␊
43␉␉␉␉␉default:␊
44␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
45␉␉␉␉}␊
46␉␉␉}␊
47␉␉␉␉break;␊
48␊
49␉␉␉default:␊
50␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
51␉␉}␊
52␉} else {␊
53␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
54␉}␊
55␊
56␉return true;␊
57}␊
58␊
59bool getProcessorInformationMaximumClock(returnType *value)␊
60{␊
61␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
62␉return true;␊
63}␊
64␊
65bool getSMBOemProcessorBusSpeed(returnType *value)␊
66{␊
67␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
68␉␉switch (Platform.CPU.Family) {␊
69␉␉␉case 0x06:␊
70␉␉␉{␊
71␉␉␉␉switch (Platform.CPU.Model) {␊
72␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
73␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
74␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
75␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
76␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
77␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
78␉␉␉␉␉␉return false;␊
79␊
80␉␉␉␉␉case 0x19:␊
81␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
83␉␉␉␉␉case CPU_MODEL_DALES:␊
84␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
85␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
86␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
87␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
88␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
89␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
90␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
91␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
92␉␉␉␉␉case CPU_MODEL_HASWELL:␊
93␉␉␉␉␉{␊
94␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
95␉␉␉␉␉␉int nhm_bus = 0x3F;␊
96␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
97␉␉␉␉␉␉unsigned long did, vid;␊
98␉␉␉␉␉␉unsigned int i;␊
99␉␉␉␉␉␉␊
100␉␉␉␉␉␉// Nehalem supports Scrubbing␊
101␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
102␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
103␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
104␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
105␉␉␉␉␉␉␉vid &= 0xFFFF;␊
106␉␉␉␉␉␉␉did &= 0xFF00;␊
107␉␉␉␉␉␉␉␊
108␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
109␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
110␉␉␉␉␉␉␉}␊
111␉␉␉␉␉␉}␊
112␊
113␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
114␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
115␉␉␉␉␉␉qpimult &= 0x7F;␊
116␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
117␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
118␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
119␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
120␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
121␉␉␉␉␉␉}␊
122␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
123␉␉␉␉␉␉value->word = qpibusspeed;␊
124␉␉␉␉␉␉return true;␊
125␉␉␉␉␉}␊
126␉␉␉␉␉default:␊
127␉␉␉␉␉␉break; //Unsupported CPU type␊
128␉␉␉␉}␊
129␉␉␉}␊
130␉␉␉default:␊
131␉␉␉␉break;␊
132␉␉}␊
133␉}␊
134␉return false;␊
135}␊
136␊
137uint16_t simpleGetSMBOemProcessorType(void)␊
138{␊
139␉if (Platform.CPU.NoCores >= 4) {␊
140␉␉return 0x0501;␉// 1281 - Quad-Core Xeon␊
141␉} else if (Platform.CPU.NoCores == 1) {␊
142␉␉return 0x0201;␉// // 513 - Core Duo␊
143␉};␊
144␉␊
145␉return 0x0301;␉␉// 769 - Core 2 Duo␊
146}␊
147␊
148bool getSMBOemProcessorType(returnType *value)␊
149{␊
150␉static bool done = false;␊
151␊
152␉value->word = simpleGetSMBOemProcessorType();␊
153␊
154␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
155␉␉if (!done) {␊
156␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
157␉␉␉done = true;␊
158␉␉}␊
159␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
160␉␉switch (Platform.CPU.Family) {␊
161 case 0x0F:␊
162␉␉␉case 0x06:␊
163␉␉␉{␊
164␉␉␉␉switch (Platform.CPU.Model) {␊
165 case CPU_MODEL_PENTIUM_M:␊
166␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
167 case CPU_MODEL_IRWINDALE:␊
168 case CPU_MODEL_NOCONA:␊
169 if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
170␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊
171 }␊
172 return true;␊
173 ␊
174␉␉␉␉␉case CPU_MODEL_PRESLER:␊
175 case CPU_MODEL_CELERON:␊
176 case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
177␉␉␉␉␉␉value->word = 0x201; // 513␊
178␉␉␉␉␉␉return true;␊
179 ␊
180␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
181 case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
182␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
183␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
184␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊
185 return true;␊
186␉␉␉␉␉␉}␊
187 if (Platform.CPU.NoCores <= 2) {␊
188␉␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769 - Core 2 Duo␊
189␉␉␉␉␉␉} else {␊
190 value->word = 0x402;␉␉␉// 1026 - Core 2 Quad as Xeon␊
191 }␊
192␉␉␉␉␉␉return true;␊
193 ␊
194␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
195␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
196␉␉␉␉␉␉return true;␊
197␊
198␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
199␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
200␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
201␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
202 if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
203␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// // 1281 - Lynnfiled Quad-Core Xeon␊
204 return true;␊
205␉␉␉␉␉␉}␊
206␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
207␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
208 return true;␊
209␉␉␉␉␉␉}␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
211␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
212 return true;␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
215␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
216 return true;␊
217␉␉␉␉␉␉}␊
218␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
219␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// 1537 - Core i3␊
220␉␉␉␉␉␉}␊
221␉␉␉␉␉␉return true;␊
222␊
223␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
224 case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
225 case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
226 if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
227␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
228 return true;␊
229␉␉␉␉␉␉}␊
230␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
231␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
232 return true;␊
233␉␉␉␉␉␉}␊
234␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
235␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
236 return true;␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
239␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 - Core i7␊
240 return true;␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
243␉␉␉␉␉␉␉value->word = 0x901;␉␉// 1538 - Core i3␊
244␉␉␉␉␉␉}␊
245␉␉␉␉␉␉return true;␊
246␊
247␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
248␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
250␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
251 return true;␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
254␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 - Core i3␊
255 return true;␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
258␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
259 return true;␊
260␉␉␉␉␉␉}␊
261␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
262␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
263 return true;␊
264␉␉␉␉␉␉}␊
265␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
266␉␉␉␉␉␉␉value->word = 0x902;␉␉// 1539 - Core i3␊
267␉␉␉␉␉␉}␊
268␉␉␉␉␉␉return true;␊
269␊
270␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
271 if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
272␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
273 return true;␊
274␉␉␉␉␉␉}␊
275␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
276␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it - but we yes:-)␊
277 return true;␊
278␉␉␉␉␉␉}␊
279␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
280␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
281 return true;␊
282␉␉␉␉␉␉}␊
283␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
284␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
285 return true;␊
286␉␉␉␉␉␉}␊
287␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
288␉␉␉␉␉␉␉value->word = 0x903;␉␉// 1540 - Core i3␊
289␉␉␉␉␉␉}␊
290␉␉␉␉␉␉return true;␊
291␊
292␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
293␉␉␉␉␉␉value->word = 0xA01; // 2561 - Xeon␊
294␉␉␉␉␉␉return true;␊
295␊
296␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
297␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
298␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
299␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
300 if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
301␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
302 return true;␊
303␉␉␉␉␉␉}␊
304␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
305␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
306 return true;␊
307␉␉␉␉␉␉}␊
308␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
309␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
310 return true;␊
311␉␉␉␉␉␉}␊
312␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
313␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
314 return true;␊
315␉␉␉␉␉␉}␊
316␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
317␉␉␉␉␉␉␉value->word = 0x904;␉␉// 1541 - Core i3␊
318␉␉␉␉␉␉}␊
319␉␉␉␉␉␉return true;␊
320␊
321␉␉␉␉␉case 0x15: // EP80579 integrated processor␊
322␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
323␉␉␉␉␉␉return true;␊
324␊
325␉␉␉␉␉case 0x13: // Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
326␉␉␉␉␉case 0x19: // Intel Core i5 650 @3.20 Ghz␊
327␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
328␉␉␉␉␉␉return true;␊
329␉␉␉␉␉default:␊
330␉␉␉␉␉␉break; // Unsupported CPU type␊
331␉␉␉␉}␊
332␉␉␉}␊
333␉␉␉default:␊
334␉␉␉␉break;␊
335␉␉}␊
336␉}␊
337␉␊
338␉return false;␊
339}␊
340␊
341bool getSMBMemoryDeviceMemoryType(returnType *value)␊
342{␊
343␉static int idx = -1;␊
344␉int␉map;␊
345␊
346 if (!bootInfo->memDetect) {␊
347␉␉return false;␊
348␉}␊
349 ␊
350␉idx++;␊
351␉if (idx < MAX_RAM_SLOTS) {␊
352␉␉map = Platform.DMI.DIMM[idx];␊
353␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
354␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
355␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
356␉␉␉return true;␊
357␉␉}␊
358␉}␊
359␊
360 value->byte = 2; // means Unknown␊
361␉return true;␊
362//␉value->byte = SMB_MEM_TYPE_DDR2;␊
363//␉return true;␊
364}␊
365␊
366bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
367{␊
368␉value->word = 0xFFFF;␊
369␉return true;␊
370}␊
371␊
372bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
373{␊
374␉static int idx = -1;␊
375␉int␉map;␊
376␊
377 if (!bootInfo->memDetect) {␊
378␉␉return false;␊
379␉}␊
380 ␊
381␉idx++;␊
382␉if (idx < MAX_RAM_SLOTS) {␊
383␉␉map = Platform.DMI.DIMM[idx];␊
384␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
385␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
386␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
387␉␉␉return true;␊
388␉␉}␊
389␉}␊
390␊
391 value->dword = 0; // means Unknown␊
392␉return true;␊
393//␉value->dword = 800;␊
394//␉return true;␊
395}␊
396␊
397bool getSMBMemoryDeviceManufacturer(returnType *value)␊
398{␊
399␉static int idx = -1;␊
400␉int␉map;␊
401␊
402 if (!bootInfo->memDetect) {␊
403␉␉return false;␊
404␉}␊
405 ␊
406␉idx++;␊
407␉if (idx < MAX_RAM_SLOTS) {␊
408␉␉map = Platform.DMI.DIMM[idx];␊
409␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
410␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
411␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
412␉␉␉return true;␊
413␉␉}␊
414␉}␊
415␊
416␉value->string = NOT_AVAILABLE;␊
417␉return true;␊
418}␊
419␊
420bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
421{␊
422␉static int idx = -1;␊
423␉int␉map;␊
424␊
425 if (!bootInfo->memDetect) {␊
426␉␉return false;␊
427␉}␊
428 ␊
429␉idx++;␊
430␉// DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
431␉if (idx < MAX_RAM_SLOTS) {␊
432␉␉map = Platform.DMI.DIMM[idx];␊
433␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
434␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
435␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
436␉␉␉return true;␊
437␉␉}␊
438␉}␊
439␊
440␉value->string = NOT_AVAILABLE;␊
441␉return true;␊
442}␊
443␊
444bool getSMBMemoryDevicePartNumber(returnType *value)␊
445{␊
446␉static int idx = -1;␊
447␉int␉map;␊
448␊
449 if (!bootInfo->memDetect) {␊
450␉␉return false;␊
451␉}␊
452 ␊
453␉idx++;␊
454␉if (idx < MAX_RAM_SLOTS) {␊
455␉␉map = Platform.DMI.DIMM[idx];␊
456␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
457␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
458␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
459␉␉␉return true;␊
460␉␉}␊
461␉}␊
462␊
463␉value->string = NOT_AVAILABLE;␊
464␉return true;␊
465}␊
466␊
467␊
468// getting smbios addr with fast compare ops, late checksum testing ...␊
469#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
470static const char * const SMTAG = "_SM_";␊
471static const char* const DMITAG = "_DMI_";␊
472␊
473SMBEntryPoint *getAddressOfSmbiosTable(void)␊
474{␊
475␉SMBEntryPoint␉*smbios;␊
476␉/*␊
477␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
478␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
479␉ */␊
480␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
481␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
482␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
483␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
484␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
485␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
486␉␉␉return smbios;␊
487␉ }␊
488␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
489␉}␊
490␉printf("ERROR: Unable to find SMBIOS!\n");␊
491␉pause();␊
492␉return NULL;␊
493}␊
494␊
495

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