1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
25 | ␉␉switch (Platform.CPU.Family) {␊ |
26 | ␉␉␉case 0x06:␊ |
27 | ␉␉␉{␊ |
28 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
29 | ␉␉␉␉{␊ |
30 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
31 | // sets external clock to 0␊ |
32 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
33 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
34 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
39 | ␊ |
40 | ␉␉␉␉␉␉value->word = 0;␊ |
41 | ␉␉␉␉␉␉break;␊ |
42 | ␉␉␉␉␉default:␊ |
43 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
44 | ␉␉␉␉}␊ |
45 | ␉␉␉}␊ |
46 | ␉␉␉␉break;␊ |
47 | ␊ |
48 | ␉␉␉default:␊ |
49 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
50 | ␉␉}␊ |
51 | ␉} else {␊ |
52 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
53 | ␉}␊ |
54 | ␊ |
55 | ␉return true;␊ |
56 | }␊ |
57 | ␊ |
58 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
59 | {␊ |
60 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
61 | ␉return true;␊ |
62 | }␊ |
63 | ␊ |
64 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
65 | {␊ |
66 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
67 | ␉␉switch (Platform.CPU.Family) {␊ |
68 | ␉␉␉case 0x06:␊ |
69 | ␉␉␉{␊ |
70 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
71 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
72 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
73 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
74 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
75 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
76 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
77 | ␉␉␉␉␉␉return false;␊ |
78 | ␊ |
79 | ␉␉␉␉␉case 0x19:␊ |
80 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
81 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
82 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
83 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
84 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
85 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
86 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
87 | //␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm) // MacMan removed not valid for this CPU␊ |
88 | //␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm) // MacMan removed not valid for this CPU␊ |
89 | //␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: // MacMan moved␊ |
90 | //␉␉␉␉␉case CPU_MODEL_HASWELL: // MacMan removed not valid for this CPU␊ |
91 | //␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)// MacMan moved␊ |
92 | ␉␉␉␉␉{␊ |
93 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
94 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
95 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
96 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
97 | ␉␉␉␉␉␉unsigned int i;␊ |
98 | ␉␉␉␉␉␉␊ |
99 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
100 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
101 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊ |
102 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
103 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
104 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
105 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
106 | ␉␉␉␉␉␉␉␊ |
107 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊ |
108 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
109 | ␉␉␉␉␉␉␉}␊ |
110 | ␉␉␉␉␉␉}␊ |
111 | ␊ |
112 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
113 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
114 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
115 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
116 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
117 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
118 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊ |
119 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
120 | ␉␉␉␉␉␉}␊ |
121 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
122 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
123 | ␉␉␉␉␉␉return true;␊ |
124 | ␉␉␉␉␉}␊ |
125 | // MacMan the following CPUs have fixed DMI2 speeds␊ |
126 | case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm)␊ |
127 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
128 | {␊ |
129 | unsigned long dmi2speed;␊ |
130 | dmi2speed = 5000;␊ |
131 | DBG("dmi2speed %d\n", dmi2speed);␊ |
132 | ␉␉␉␉␉␉value->word = dmi2speed;␊ |
133 | ␉␉␉␉␉␉return true;␊ |
134 | }␊ |
135 | ␉␉␉␉␉default:␊ |
136 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
137 | ␉␉␉␉}␊ |
138 | ␉␉␉}␊ |
139 | ␉␉␉default:␊ |
140 | ␉␉␉␉break;␊ |
141 | ␉␉}␊ |
142 | ␉}␊ |
143 | ␉return false;␊ |
144 | }␊ |
145 | ␊ |
146 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
147 | {␊ |
148 | ␉if (Platform.CPU.NoCores >= 4) {␊ |
149 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
150 | ␉} else if (Platform.CPU.NoCores == 1) {␊ |
151 | ␉␉return 0x201;␉// 513 - Core Solo␊ |
152 | ␉};␊ |
153 | ␉␊ |
154 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
155 | }␊ |
156 | ␊ |
157 | bool getSMBOemProcessorType(returnType *value)␊ |
158 | {␊ |
159 | ␉static bool done = false;␊ |
160 | ␊ |
161 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
162 | ␊ |
163 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
164 | ␉␉if (!done) {␊ |
165 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
166 | ␉␉␉done = true;␊ |
167 | ␉␉}␊ |
168 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊ |
169 | // MacMan changed OEM Processor Type ␊ |
170 | ␉␉switch (Platform.CPU.Family) {␊ |
171 | ␉␉␉case 0x06:␊ |
172 | ␉␉␉{␊ |
173 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
174 | ␊ |
175 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊ |
176 | ␉␉␉␉␉␉value->word = 0x101;␉␉␉// 257␊ |
177 | ␉␉␉␉␉␉return true;␊ |
178 | ␊ |
179 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
180 | ␉␉␉␉␉case CPU_MODEL_CELERON:␊ |
181 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
182 | ␉␉␉␉␉␉return true;␊ |
183 | ␊ |
184 | ␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
185 | ␉␉␉␉␉␉value->word = 0x401;␉␉␉// 1025␊ |
186 | ␉␉␉␉␉␉return true;␊ |
187 | ␊ |
188 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
189 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
190 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
191 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊ |
192 | ␉␉␉␉␉␉}␊ |
193 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊ |
194 | ␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
195 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
199 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
200 | case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
201 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
202 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
203 | ␉␉␉␉␉␉␉return true;␊ |
204 | ␉␉␉␉␉␉}␊ |
205 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
206 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
207 | ␉␉␉␉␉␉␉return true;␊ |
208 | ␉␉␉␉␉␉}␊ |
209 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
210 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
211 | ␉␉␉␉␉␉␉return true;␊ |
212 | ␉␉␉␉␉␉}␊ |
213 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
214 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
215 | ␉␉␉␉␉␉␉return true;␊ |
216 | ␉␉␉␉␉␉}␊ |
217 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
218 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
219 | ␉␉␉␉␉␉}␊ |
220 | ␉␉␉␉␉␉return true;␊ |
221 | ␊ |
222 | case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
223 | case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx, Xeon L75xx, LGA1567 (45nm)␊ |
224 | case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
225 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
226 | case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
227 | case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F - ␊ |
228 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
229 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
230 | ␉␉␉␉␉␉␉return true;␊ |
231 | ␉␉␉␉␉␉}␊ |
232 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
233 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
234 | ␉␉␉␉␉␉␉return true;␊ |
235 | ␉␉␉␉␉␉}␊ |
236 | ␉␉␉␉␉␉return true;␊ |
237 | ␊ |
238 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
239 | case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
240 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
241 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
242 | ␉␉␉␉␉␉␉return true;␊ |
243 | ␉␉␉␉␉␉}␊ |
244 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
245 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
246 | ␉␉␉␉␉␉␉return true;␊ |
247 | ␉␉␉␉␉␉}␊ |
248 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
249 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
250 | ␉␉␉␉␉␉␉return true;␊ |
251 | ␉␉␉␉␉␉}␊ |
252 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
253 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
254 | ␉␉␉␉␉␉␉return true;␊ |
255 | ␉␉␉␉␉␉}␊ |
256 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
257 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
258 | ␉␉␉␉␉␉}␊ |
259 | ␉␉␉␉␉␉return true;␊ |
260 | ␊ |
261 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
262 | ␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561␊ |
263 | ␉␉␉␉␉␉return true;␊ |
264 | ␊ |
265 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊ |
266 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
267 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
268 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
269 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
270 | ␉␉␉␉␉␉␉return true;␊ |
271 | ␉␉␉␉␉␉}␊ |
272 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
273 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
274 | ␉␉␉␉␉␉␉return true;␊ |
275 | ␉␉␉␉␉␉}␊ |
276 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
277 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
278 | ␉␉␉␉␉␉␉return true;␊ |
279 | ␉␉␉␉␉␉}␊ |
280 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
281 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
282 | ␉␉␉␉␉␉␉return true;␊ |
283 | ␉␉␉␉␉␉}␊ |
284 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
285 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
286 | ␉␉␉␉␉␉}␊ |
287 | ␉␉␉␉␉␉return true;␊ |
288 | ␊ |
289 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
290 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
291 | ␉␉␉␉␉␉return true;␊ |
292 | ␊ |
293 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
294 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
295 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
296 | ␉␉␉␉␉␉return true;␊ |
297 | ␉␉␉␉␉default:␊ |
298 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
299 | ␉␉␉␉}␊ |
300 | ␉␉␉}␊ |
301 | ␉␉␉default:␊ |
302 | ␉␉␉␉break;␊ |
303 | ␉␉}␊ |
304 | ␉}␊ |
305 | ␉␊ |
306 | ␉return false;␊ |
307 | }␊ |
308 | ␊ |
309 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
310 | {␊ |
311 | ␉static int idx = -1;␊ |
312 | ␉int␉map;␊ |
313 | ␊ |
314 | ␉idx++;␊ |
315 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
316 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
317 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊ |
318 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
319 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
320 | ␉␉␉return true;␊ |
321 | ␉␉}␊ |
322 | ␉}␊ |
323 | ␊ |
324 | ␉return false;␊ |
325 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
326 | //␉return true;␊ |
327 | }␊ |
328 | ␊ |
329 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
330 | {␊ |
331 | ␉value->word = 0xFFFF;␊ |
332 | ␉return true;␊ |
333 | }␊ |
334 | ␊ |
335 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
336 | {␊ |
337 | ␉static int idx = -1;␊ |
338 | ␉int␉map;␊ |
339 | ␊ |
340 | ␉idx++;␊ |
341 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
342 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
343 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊ |
344 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
345 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
346 | ␉␉␉return true;␊ |
347 | ␉␉}␊ |
348 | ␉}␊ |
349 | ␊ |
350 | ␉return false;␊ |
351 | //␉value->dword = 800;␊ |
352 | //␉return true;␊ |
353 | }␊ |
354 | ␊ |
355 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
356 | {␊ |
357 | ␉static int idx = -1;␊ |
358 | ␉int␉map;␊ |
359 | ␊ |
360 | ␉idx++;␊ |
361 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
362 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
363 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊ |
364 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
365 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
366 | ␉␉␉return true;␊ |
367 | ␉␉}␊ |
368 | ␉}␊ |
369 | ␊ |
370 | ␉if (!bootInfo->memDetect) {␊ |
371 | ␉␉return false;␊ |
372 | ␉}␊ |
373 | ␉value->string = NOT_AVAILABLE;␊ |
374 | ␉return true;␊ |
375 | }␊ |
376 | ␊ |
377 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
378 | {␊ |
379 | ␉static int idx = -1;␊ |
380 | ␉int␉map;␊ |
381 | ␊ |
382 | ␉idx++;␊ |
383 | ␊ |
384 | ␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
385 | ␊ |
386 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
387 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
388 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊ |
389 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
390 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
391 | ␉␉␉return true;␊ |
392 | ␉␉}␊ |
393 | ␉}␊ |
394 | ␊ |
395 | ␉if (!bootInfo->memDetect) {␊ |
396 | ␉␉return false;␊ |
397 | ␉}␊ |
398 | ␉value->string = NOT_AVAILABLE;␊ |
399 | ␉return true;␊ |
400 | }␊ |
401 | ␊ |
402 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
403 | {␊ |
404 | ␉static int idx = -1;␊ |
405 | ␉int␉map;␊ |
406 | ␊ |
407 | ␉idx++;␊ |
408 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
409 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
410 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊ |
411 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
412 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
413 | ␉␉␉return true;␊ |
414 | ␉␉}␊ |
415 | ␉}␊ |
416 | ␊ |
417 | ␉if (!bootInfo->memDetect) {␊ |
418 | ␉␉return false;␊ |
419 | ␉}␊ |
420 | ␉value->string = NOT_AVAILABLE;␊ |
421 | ␉return true;␊ |
422 | }␊ |
423 | ␊ |
424 | ␊ |
425 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
426 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
427 | static const char * const SMTAG = "_SM_";␊ |
428 | static const char* const DMITAG = "_DMI_";␊ |
429 | ␊ |
430 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
431 | {␊ |
432 | ␉SMBEntryPoint␉*smbios;␊ |
433 | ␉/*␊ |
434 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
435 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
436 | ␉ */␊ |
437 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
438 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
439 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
440 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
441 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
442 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊ |
443 | ␉␉␉return smbios;␊ |
444 | ␉ }␊ |
445 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
446 | ␉}␊ |
447 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
448 | ␉pause();␊ |
449 | ␉return NULL;␊ |
450 | }␊ |
451 | ␊ |
452 | |