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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30 int␉␉attempts = 0;␊
31 uint64_t latchTime;␊
32 uint64_t␉saveTime,intermediate;␊
33 unsigned int timerValue, lastValue;␊
34 //boolean_t␉int_enabled;␊
35 /*␊
36 * Table of correction factors to account for␊
37 *␉ - timer counter quantization errors, and␊
38 *␉ - undercounts 0..5␊
39 */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45 uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52 };␊
53 ␊
54 //int_enabled = ml_set_interrupts_enabled(FALSE);␊
55 ␊
56restart:␊
57 if (attempts >= 9) // increase to up to 9 attempts.␊
58 {␊
59 // This will flash-reboot. TODO: Use tscPanic instead.␊
60 printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61 }␊
62 attempts++;␊
63 enable_PIT2();␉␉// turn on PIT2␊
64 set_PIT2(0);␉␉// reset timer 2 to be zero␊
65 latchTime = rdtsc64();␉// get the time stamp to time ␊
66 latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67 set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68 saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69 get_PIT2(&lastValue);␊
70 get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71 do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74 {␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81 } while (timerValue > 5);␊
82 printf("timerValue␉ %d\n",timerValue);␊
83 printf("intermediate 0x%016llx\n",intermediate);␊
84 printf("saveTime␉ 0x%016llx\n",saveTime);␊
85 ␊
86 intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87 intermediate *= scale[timerValue];␉// rescale measured time spent␊
88 intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89 intermediate += latchTime;␉␉// add on our save fudge␊
90 ␊
91 set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92 disable_PIT2();␉␉␉// turn off PIT 2␊
93␊
94 //ml_set_interrupts_enabled(int_enabled);␊
95 return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␉␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1) {␊
128␉␉␉continue;␊
129 }␊
130␉␉/* The TSC must increment at LEAST once every millisecond.␊
131␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
132␉␉ * be >= 30. Anything less and the processor is way too slow.␊
133␉␉ */␊
134␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {␊
135␉␉␉continue;␊
136 }␊
137␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
138␉␉if ( (tscEnd - tscStart) < tscDelta ) {␊
139␉␉␉tscDelta = tscEnd - tscStart;␊
140 }␊
141␉}␊
142␉/* tscDelta is now the least number of TSC ticks the processor made in␊
143␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
144␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
145␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
146␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
147␉ * dividing by the milliseconds, we simply multiply by 1000.␊
148␉ */␊
149␉␊
150␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
151␉ * that we're going to multiply by 1000 first so we do need at least some␊
152␉ * arithmetic headroom. For now, 32-bit should be enough.␊
153␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
154␉ */␊
155␉if (tscDelta > (1ULL<<32)) {␊
156␉␉retval = 0;␊
157␉} else {␊
158␉␉retval = tscDelta * 1000 / 30;␊
159␉}␊
160␉disable_PIT2();␊
161␉return retval;␊
162}␊
163␊
164/*␊
165 * Original comment/code:␊
166 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
167 *␊
168 * Measures the Actual Performance Frequency in Hz (64-bit)␊
169 * (just a naming change, mperf --> aperf )␊
170 */␊
171static uint64_t measure_aperf_frequency(void)␊
172{␊
173␉uint64_t aperfStart;␊
174␉uint64_t aperfEnd;␊
175␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
176␉unsigned long pollCount;␊
177␉uint64_t retval = 0;␊
178␉int i;␊
179␉␊
180␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
181␉ * counter 2. We run this loop 3 times to make sure the cache␊
182␉ * is hot and we take the minimum delta from all of the runs.␊
183␉ * That is to say that we're biased towards measuring the minimum␊
184␉ * number of APERF ticks that occur while waiting for the timer to␊
185␉ * expire.␊
186␉ */␊
187␉for(i = 0; i < 10; ++i)␊
188␉{␊
189␉␉enable_PIT2();␊
190␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
191␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
192␉␉pollCount = poll_PIT2_gate();␊
193␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
194␉␉/* The poll loop must have run at least a few times for accuracy */␊
195␉␉if (pollCount <= 1) {␊
196␉␉␉continue;␊
197 }␊
198␉␉/* The TSC must increment at LEAST once every millisecond.␊
199␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
200␉␉ * be >= 30. Anything less and the processor is way too slow.␊
201␉␉ */␊
202␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC) {␊
203␉␉␉continue;␊
204 }␊
205␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
206␉␉if ( (aperfEnd - aperfStart) < aperfDelta ) {␊
207␉␉␉aperfDelta = aperfEnd - aperfStart;␊
208 }␊
209␉}␊
210␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
211␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
212␉ */␊
213␉␊
214␉if (aperfDelta > (1ULL<<32)) {␊
215␉␉retval = 0;␊
216␉} else {␊
217␉␉retval = aperfDelta * 1000 / 30;␊
218␉}␊
219␉disable_PIT2();␊
220␉return retval;␊
221}␊
222␊
223/*␊
224 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
225 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
226 *␉ a max multi. (used to calculate the FSB freq.),␊
227 *␉ and a current multi. (used to calculate the CPU freq.)␊
228 * - fsbFrequency = tscFrequency / multi␊
229 * - cpuFrequency = fsbFrequency * multi␊
230 */␊
231void scan_cpu(PlatformInfo_t *p)␊
232{␊
233␉uint64_t␉tscFrequency = 0;␊
234␉uint64_t␉fsbFrequency = 0;␊
235␉uint64_t␉cpuFrequency =0;␊
236␉uint64_t␉msr = 0;␊
237␉uint64_t␉flex_ratio = 0;␊
238␉uint32_t␉max_ratio = 0;␊
239␉uint32_t␉min_ratio = 0;␊
240␉uint8_t␉␉bus_ratio_max = 0;␊
241␉uint8_t␉␉bus_ratio_min = 0;␊
242␉uint8_t␉␉currdiv = 0;␊
243␉uint8_t␉␉currcoef = 0;␊
244␉uint8_t␉␉maxdiv = 0;␊
245␉uint8_t␉␉maxcoef = 0;␊
246␊
247␉const char␉*newratio;␊
248␉int␉␉len = 0;␊
249␉␊
250␉/* get cpuid values */␊
251␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
252␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
253␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
254␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
255␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
256␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
257␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5) {␉␉␊
258␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); ␉␊
259␉}␉␊
260␉if (p->CPU.CPUID[CPUID_0][0] >= 6) {␊
261␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␉␉␊
262␉}␊
263␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
264␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
265␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
266␉} else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
267␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
268␉}␊
269␉␊
270#if DEBUG_CPU␊
271␉{␊
272␉␉int␉␉i;␊
273␉␉printf("CPUID Raw Values:\n");␊
274␉␉for (i=0; i<CPUID_MAX; i++) {␊
275␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
276␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
277␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
278␉␉}␊
279␉}␊
280#endif␊
281 ␊
282/*␊
283 EAX (Intel):␊
284 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
285 +--------+----------------+--------+----+----+--------+--------+--------+␊
286 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
287 +--------+----------------+--------+----+----+--------+--------+--------+␊
288 ␊
289 EAX (AMD):␊
290 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
291 +--------+----------------+--------+----+----+--------+--------+--------+␊
292 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
293 +--------+----------------+--------+----+----+--------+--------+--------+␊
294*/␊
295␉␊
296␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
297␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
298 // stepping = cpu_feat_eax & 0xF;␊
299␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
300 // model = (cpu_feat_eax >> 4) & 0xF;␊
301␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
302 // family = (cpu_feat_eax >> 8) & 0xF;␊
303␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
304 // type = (cpu_feat_eax >> 12) & 0x3;␊
305␉//p->CPU.Type␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊
306 // ext_model = (cpu_feat_eax >> 16) & 0xF;␊
307␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
308 // ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
309␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
310␉␊
311␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
312␉␊
313␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
314␉␉p->CPU.Family == 0x06 &&␊
315␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊
316␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
317␉␉) {␊
318␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// MacMan: Undocumented MSR in Nehalem and newer CPUs␊
319␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// MacMan: Using undocumented MSR to get actual values␊
320␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// MacMan: Using undocumented MSR to get actual values␊
321␉} else if (p->CPU.Vendor == CPUID_VENDOR_AMD) {␊
322␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
323␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
324␉} else {␊
325␉␉// Use previous method for Cores and Threads␊
326␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
327␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
328␉}␊
329␉␊
330␉/* get brand string (if supported) */␊
331␉/* Copyright: from Apple's XNU cpuid.c */␊
332␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
333␉␉uint32_t␉reg[4];␊
334␉␉char␉␉str[128], *s;␊
335␉␉/*␊
336␉␉ * The brand string 48 bytes (max), guaranteed to␊
337␉␉ * be NULL terminated.␊
338␉␉ */␊
339␉␉do_cpuid(0x80000002, reg);␊
340␉␉bcopy((char *)reg, &str[0], 16);␊
341␉␉do_cpuid(0x80000003, reg);␊
342␉␉bcopy((char *)reg, &str[16], 16);␊
343␉␉do_cpuid(0x80000004, reg);␊
344␉␉bcopy((char *)reg, &str[32], 16);␊
345␉␉for (s = str; *s != '\0'; s++) {␊
346␉␉␉if (*s != ' ') {␊
347 break;␊
348 }␊
349␉␉}␊
350␉␉␊
351␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
352␉␉␊
353␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
354␉␉␉/*␊
355␉␉␉ * This string means we have a firmware-programmable brand string,␊
356␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
357␉␉␉ */␊
358␉␉␉p->CPU.BrandString[0] = '\0';␊
359␉␉}␊
360␉}␊
361␉␊
362␉/* setup features */␊
363␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
364␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
365␉}␊
366␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
367␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
368␉}␊
369␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
370␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
371␉}␊
372␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
373␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
374␉}␊
375␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
376␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
377␉}␊
378␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
379␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
380␉}␊
381␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
382␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
383␉}␊
384␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
385␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
386␉}␊
387␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
388␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
389␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
390␉}␊
391␉␊
392␉tscFrequency = measure_tsc_frequency();␊
393␉/* if usual method failed */␊
394␉if ( tscFrequency < 1000 ) { //TEST␊
395␉tscFrequency = timeRDTSC() * 20;␊
396␉}␊
397␉fsbFrequency = 0;␊
398␉cpuFrequency = 0;␊
399␉␊
400␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
401␉␉int intelCPU = p->CPU.Model;␊
402␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
403␉␉␉/* Nehalem CPU model */␊
404␉␉␉if (p->CPU.Family == 0x06 && (␊
405 p->CPU.Model == CPU_MODEL_NEHALEM ||␊
406␉␉␉␉␉p->CPU.Model == CPU_MODEL_FIELDS ||␊
407␉␉␉␉␉p->CPU.Model == CPU_MODEL_DALES ||␊
408␉␉␉␉␉p->CPU.Model == CPU_MODEL_DALES_32NM ||␊
409␉␉␉␉␉p->CPU.Model == CPU_MODEL_WESTMERE ||␊
410␉␉␉␉␉p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
411␉␉␉␉␉p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
412␉␉␉␉␉p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
413␉␉␉␉␉p->CPU.Model == CPU_MODEL_JAKETOWN ||␊
414␉␉␉␉␉p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
415 p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON||␊
416 p->CPU.Model == CPU_MODEL_HASWELL ||␊
417␉␉␉␉␉p->CPU.Model == CPU_MODEL_HASWELL_SVR ||␊
418␉␉␉␉␉p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
419␉␉␉␉␉p->CPU.Model == CPU_MODEL_CRYSTALWELL )){␊
420␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
421//␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
422␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
423 ␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40);␉//MacMan: Changed bitfield to match Apple tsc.c␊
424␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
425//␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
426␉␉␉␉if (bitfield(msr, 16, 16)) {␊
427␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
428␉␉␉␉␉if (flex_ratio == 0) {␊
429␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
430␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
431␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
432//␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
433␉␉␉␉␉} else {␊
434␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
435␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
436␉␉␉␉␉␉}␊
437␉␉␉␉␉}␊
438␉␉␉␉}␊
439␉␉␉␉␊
440␉␉␉␉if (bus_ratio_max) {␊
441␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
442␉␉␉␉}␊
443␉␉␉␉//MacMan: Turbo Ratio Limit␊
444␉␉␉␉switch (intelCPU) ␊
445␉␉␉␉{␊
446␉␉␉␉␉case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7␊
447␉␉␉␉␉case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
448␉␉␉␉␉{␊
449␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
450␉␉␉␉␉␉DBG("cpu.c (%d)CPU_MODEL_NEHALEM_EX or CPU_MODEL_WESTMERE_EX Found\n", __LINE__);␊
451␉␉␉␉␉␉break;␊
452␉␉␉␉␉}␊
453␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm)␊
454␉␉␉␉␉case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm)␊
455␉␉␉␉␉case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)␊
456 case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 LGA2011 (22nm)␊
457 case CPU_MODEL_HASWELL: // Intel Core i3, i5, i7, Xeon E3 LGA1050 (22nm)␊
458 case CPU_MODEL_HASWELL_ULT:␊
459 case CPU_MODEL_CRYSTALWELL:␊
460␉␉␉␉␉{␊
461␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
462␉␉␉␉␉␉currcoef = bitfield(msr, 15, 8);␊
463␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
464␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
465␉␉␉␉␉␉break;␊
466␉␉␉␉␉}␊
467␉␉␉␉␉default:␊
468␉␉␉␉␉{␊
469␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
470␉␉␉␉␉␉currcoef = bitfield(msr, 7, 0);␊
471␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
472␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
473␉␉␉␉␉␉break;␊
474␉␉␉␉␉}␊
475␉␉␉␉}␊
476␊
477␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
478␉␉␉␉␉max_ratio = atoi(newratio);␊
479␉␉␉␉␉max_ratio = (max_ratio * 10);␊
480␉␉␉␉␉if (len >= 3) {␊
481 max_ratio = (max_ratio + 5);␊
482 }␊
483 ␊
484␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
485␉␉␉␉␉␊
486␉␉␉␉␉// extreme overclockers may love 320 ;)␊
487␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
488␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
489␉␉␉␉␉␉if (len >= 3) {␊
490 maxdiv = 1;␊
491 } else {␊
492 maxdiv = 0;␊
493 }␊
494␉␉␉␉␉} else {␊
495␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
496␉␉␉␉␉}␊
497␉␉␉␉}␊
498␉␉␉␉p->CPU.MaxRatio = bus_ratio_max;␊
499␉␉␉␉p->CPU.MinRatio = bus_ratio_min;␊
500␉␉␉} else {␊
501␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
502␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
503␉␉␉␉currcoef = bitfield(msr, 15, 8); //MacMan: Fixed bitfield to Intel documentation␊
504␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
505␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
506␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
507␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
508␉␉␉␉␊
509␉␉␉␉// This will always be model >= 3␊
510␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) {␊
511␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
512␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
513␉␉␉␉} else {␊
514␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
515␉␉␉␉␉/* XXX */␊
516␉␉␉␉␉maxcoef = currcoef;␊
517␉␉␉␉}␊
518␉␉␉␉␊
519␉␉␉␉if (maxcoef) {␊
520␉␉␉␉␉if (maxdiv) {␊
521␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
522␉␉␉␉␉} else {␊
523␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
524␉␉␉␉␉}␊
525␉␉␉␉␉if (currdiv) {␊
526␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
527␉␉␉␉␉} else {␊
528␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
529␉␉␉␉␉}␊
530␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
531␉␉␉␉}␊
532␉␉␉}␊
533␉␉}␊
534␉␉/* Mobile CPU */␊
535␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
536␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
537␉␉}␊
538␉} else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f)) {␊
539␉␉switch(p->CPU.ExtFamily) {␊
540␉␉␉case 0x00: /* K8 */␊
541␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
542␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
543␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
544␉␉␉␉break;␊
545␉␉␉␉␊
546␉␉␉case 0x01: /* K10 */␊
547␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
548␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
549␉␉␉␉// EffFreq: effective frequency interface␊
550␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) {␊
551␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
552␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
553␉␉␉␉␉cpuFrequency = aperf;␊
554␉␉␉␉}␊
555␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
556␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
557␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
558␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
559␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
560␉␉␉␉␊
561␉␉␉␉break;␊
562␉␉␉␉␊
563␉␉␉case 0x05: /* K14 */␊
564␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
565␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
566␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
567␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
568␉␉␉␉␊
569␉␉␉␉break;␊
570␉␉␉␉␊
571␉␉␉case 0x02: /* K11 */␊
572␉␉␉␉// not implimented␊
573␉␉␉␉break;␊
574␉␉}␊
575␉␉␊
576␉␉if (maxcoef) {␊
577␉␉␉if (currdiv) {␊
578␉␉␉␉if (!currcoef) {␊
579 currcoef = maxcoef;␊
580 }␊
581 ␊
582␉␉␉␉if (!cpuFrequency) {␊
583␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
584␉␉␉␉} else {␊
585␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
586␉␉␉␉}␊
587␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
588␉␉␉} else {␊
589␉␉␉␉if (!cpuFrequency) {␊
590␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
591␉␉␉␉} else {␊
592␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
593 }␊
594␉␉␉␉DBG("%d\n", currcoef);␊
595␉␉␉}␊
596␉␉} else if (currcoef) {␊
597␉␉␉if (currdiv) {␊
598␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
599␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
600␉␉␉} else {␊
601␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
602␉␉␉␉DBG("%d\n", currcoef);␊
603␉␉␉}␊
604␉␉}␊
605␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
606␉}␊
607␉␊
608#if 0␊
609␉if (!fsbFrequency) {␊
610␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
611␉␉cpuFrequency = tscFrequency;␊
612␉␉DBG("0 ! using the default value for FSB !\n");␊
613␉}␊
614#endif␊
615␉␊
616␉p->CPU.MaxCoef = maxcoef;␊
617␉if (maxdiv == 0){␊
618␉␉p->CPU.MaxDiv = bus_ratio_max;␊
619␉} else {␊
620␉␉p->CPU.MaxDiv = maxdiv;␊
621␉}␊
622␉p->CPU.CurrCoef = currcoef;␊
623␉if (currdiv == 0){␊
624␉␉p->CPU.CurrDiv = currcoef;␊
625␉} else {␊
626␉␉p->CPU.CurrDiv = currdiv;␊
627␉}␊
628␉p->CPU.TSCFrequency = tscFrequency;␊
629␉p->CPU.FSBFrequency = fsbFrequency;␊
630␉p->CPU.CPUFrequency = cpuFrequency;␊
631␉␊
632␉// keep formatted with spaces instead of tabs␊
633␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
634␉DBG("CPU: Vendor: 0x%x\n",␉␉␉␉ p->CPU.Vendor);␊
635␉DBG("CPU: Family / ExtFamily: 0x%x / 0x%x\n",␉␉ p->CPU.Family, p->CPU.ExtFamily);␊
636␉DBG("CPU: Model / ExtModel / Stepping: 0x%x / 0x%x / 0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
637␉DBG("CPU: Number of Cores / Threads: %d / %d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
638␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
639␉DBG("CPU: TSC Frequency: %d MHz\n", p->CPU.TSCFrequency / 1000000);␊
640␉DBG("CPU: FSB Frequency: %d MHz\n", p->CPU.FSBFrequency / 1000000);␊
641␉DBG("CPU: CPU Frequency: %d MHz\n", p->CPU.CPUFrequency / 1000000);␊
642␉DBG("CPU: Minimum Bus Ratio: %d\n", p->CPU.MinRatio);␊
643␉DBG("CPU: Maximum Bus Ratio: %d\n", p->CPU.MaxRatio);␊
644␉DBG("CPU: Current Bus Ratio: %d\n", p->CPU.CurrCoef);␊
645//␉DBG("CPU: Maximum Multiplier: %d\n",␉␉␉␉ p->CPU.MaxCoef);␊
646//␉DBG("CPU: Maximum Divider: %d\n",␉␉␉␉ p->CPU.MaxDiv);␊
647//␉DBG("CPU: Current Divider: %d\n",␉␉␉␉ p->CPU.CurrDiv);␊
648␊
649#if DEBUG_CPU␊
650␉pause();␊
651#endif␊
652}␊
653

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