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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
31 // sets external clock to 0␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_HASWELL:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
38␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
39␊
40␉␉␉␉␉␉value->word = 0;␊
41␉␉␉␉␉␉break;␊
42␉␉␉␉␉default:␊
43␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
44␉␉␉␉}␊
45␉␉␉}␊
46␉␉␉␉break;␊
47␊
48␉␉␉default:␊
49␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
50␉␉}␊
51␉} else {␊
52␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
53␉}␊
54␊
55␉return true;␊
56}␊
57␊
58bool getProcessorInformationMaximumClock(returnType *value)␊
59{␊
60␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
61␉return true;␊
62}␊
63␊
64bool getSMBOemProcessorBusSpeed(returnType *value)␊
65{␊
66␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
67␉␉switch (Platform.CPU.Family) {␊
68␉␉␉case 0x06:␊
69␉␉␉{␊
70␉␉␉␉switch (Platform.CPU.Model) {␊
71␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
72␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
73␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
74␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
75␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
76␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
77␉␉␉␉␉␉return false;␊
78␊
79␉␉␉␉␉case 0x19:␊
80␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
81␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
82␉␉␉␉␉case CPU_MODEL_DALES:␊
83␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
84␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
85␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
86␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
87//␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm) // MacMan removed not valid for this CPU␊
88//␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm) // MacMan removed not valid for this CPU␊
89//␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: // MacMan moved␊
90//␉␉␉␉␉case CPU_MODEL_HASWELL: // MacMan removed not valid for this CPU␊
91//␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)// MacMan moved␊
92␉␉␉␉␉{␊
93␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
94␉␉␉␉␉␉int nhm_bus = 0x3F;␊
95␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
96␉␉␉␉␉␉unsigned long did, vid;␊
97␉␉␉␉␉␉unsigned int i;␊
98␉␉␉␉␉␉␊
99␉␉␉␉␉␉// Nehalem supports Scrubbing␊
100␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
101␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
102␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
103␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
104␉␉␉␉␉␉␉vid &= 0xFFFF;␊
105␉␉␉␉␉␉␉did &= 0xFF00;␊
106␉␉␉␉␉␉␉␊
107␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
108␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
109␉␉␉␉␉␉␉}␊
110␉␉␉␉␉␉}␊
111␊
112␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
113␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
114␉␉␉␉␉␉qpimult &= 0x7F;␊
115␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
116␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
117␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
118␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
119␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
120␉␉␉␉␉␉}␊
121␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
122␉␉␉␉␉␉value->word = qpibusspeed;␊
123␉␉␉␉␉␉return true;␊
124␉␉␉␉␉}␊
125// MacMan the following CPUs have fixed DMI2 speeds␊
126 case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm)␊
127␉␉␉␉␉case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)␊
128 case CPU_MODEL_HASWELL_SVR: // Intel Core i7, Xeon E5 LGA2011v3␊
129 {␊
130 unsigned long dmi2speed;␊
131 dmi2speed = 5000;␊
132 DBG("dmi2speed %d\n", dmi2speed);␊
133␉␉␉␉␉␉value->word = dmi2speed;␊
134␉␉␉␉␉␉return true;␊
135 }␊
136␉␉␉␉␉default:␊
137␉␉␉␉␉␉break; //Unsupported CPU type␊
138␉␉␉␉}␊
139␉␉␉}␊
140␉␉␉default:␊
141␉␉␉␉break;␊
142␉␉}␊
143␉}␊
144␉return false;␊
145}␊
146␊
147uint16_t simpleGetSMBOemProcessorType(void)␊
148{␊
149␉if (Platform.CPU.NoCores >= 4) {␊
150␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊
151␉} else if (Platform.CPU.NoCores == 1) {␊
152␉␉return 0x201;␉// 513 - Core Solo␊
153␉};␊
154␉␊
155␉return 0x301;␉␉// 769 - Core 2 Duo␊
156}␊
157␊
158bool getSMBOemProcessorType(returnType *value)␊
159{␊
160␉static bool done = false;␊
161␊
162␉value->word = simpleGetSMBOemProcessorType();␊
163␊
164␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
165␉␉if (!done) {␊
166/*␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model); */␊
167␉␉␉done = true;␊
168␉␉}␊
169␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
170 // MacMan changed OEM Processor Type ␊
171␉␉switch (Platform.CPU.Family) {␊
172␉␉␉case 0x06:␊
173␉␉␉{␊
174␉␉␉␉switch (Platform.CPU.Model) {␊
175␊
176␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
177␉␉␉␉␉␉value->word = 0x101;␉␉␉// 257␊
178␉␉␉␉␉␉return true;␊
179␊
180␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
181␉␉␉␉␉case CPU_MODEL_CELERON:␊
182␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
183␉␉␉␉␉␉return true;␊
184␊
185␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
186␉␉␉␉␉␉value->word = 0x401;␉␉␉// 1025␊
187␉␉␉␉␉␉return true;␊
188␊
189␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
190␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
191␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
192␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊
193␉␉␉␉␉␉}␊
194␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
195␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
196␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
197␉␉␉␉␉␉return true;␊
198␊
199␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
200␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
201 case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
202␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
203␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
204␉␉␉␉␉␉␉return true;␊
205␉␉␉␉␉␉}␊
206␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
207␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
208␉␉␉␉␉␉␉return true;␊
209␉␉␉␉␉␉}␊
210␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
211␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
212␉␉␉␉␉␉␉return true;␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
215␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
216␉␉␉␉␉␉␉return true;␊
217␉␉␉␉␉␉}␊
218␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
219␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
220␉␉␉␉␉␉}␊
221␉␉␉␉␉␉return true;␊
222␊
223 case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
224 case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx, Xeon L75xx, LGA1567 (45nm)␊
225 case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
226␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
227 case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
228 case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F - ␊
229␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
230␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
231␉␉␉␉␉␉␉return true;␊
232␉␉␉␉␉␉}␊
233␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
234␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
235␉␉␉␉␉␉␉return true;␊
236␉␉␉␉␉␉}␊
237␉␉␉␉␉␉return true;␊
238␊
239␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
240 case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
241␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
242␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
243␉␉␉␉␉␉␉return true;␊
244␉␉␉␉␉␉}␊
245␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
246␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
247␉␉␉␉␉␉␉return true;␊
248␉␉␉␉␉␉}␊
249␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
250␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
251␉␉␉␉␉␉␉return true;␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
254␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
255␉␉␉␉␉␉␉return true;␊
256␉␉␉␉␉␉}␊
257␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
258␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
259␉␉␉␉␉␉}␊
260␉␉␉␉␉␉return true;␊
261␊
262␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
263␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561␊
264␉␉␉␉␉␉return true;␊
265␊
266␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
267␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
268␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
269␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
270␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
271␉␉␉␉␉␉␉return true;␊
272␉␉␉␉␉␉}␊
273␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
274␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
275␉␉␉␉␉␉␉return true;␊
276␉␉␉␉␉␉}␊
277␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
278␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
279␉␉␉␉␉␉␉return true;␊
280␉␉␉␉␉␉}␊
281␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
282␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
283␉␉␉␉␉␉␉return true;␊
284␉␉␉␉␉␉}␊
285␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
286␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
287␉␉␉␉␉␉}␊
288␉␉␉␉␉␉return true;␊
289␊
290␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
291␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
292␉␉␉␉␉␉return true;␊
293␊
294␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
295␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
296␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
297␉␉␉␉␉␉return true;␊
298␉␉␉␉␉default:␊
299␉␉␉␉␉␉break; //Unsupported CPU type␊
300␉␉␉␉}␊
301␉␉␉}␊
302␉␉␉default:␊
303␉␉␉␉break;␊
304␉␉}␊
305␉}␊
306␉␊
307␉return false;␊
308}␊
309␊
310bool getSMBMemoryDeviceMemoryType(returnType *value)␊
311{␊
312␉static int idx = -1;␊
313␉int␉map;␊
314␊
315␉idx++;␊
316␉if (idx < MAX_RAM_SLOTS) {␊
317␉␉map = Platform.DMI.DIMM[idx];␊
318␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
319␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
320␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
321␉␉␉return true;␊
322␉␉}␊
323␉}␊
324␊
325␉return false;␊
326//␉value->byte = SMB_MEM_TYPE_DDR2;␊
327//␉return true;␊
328}␊
329␊
330bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
331{␊
332␉value->word = 0xFFFF;␊
333␉return true;␊
334}␊
335␊
336bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
337{␊
338␉static int idx = -1;␊
339␉int␉map;␊
340␊
341␉idx++;␊
342␉if (idx < MAX_RAM_SLOTS) {␊
343␉␉map = Platform.DMI.DIMM[idx];␊
344␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
345␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
346␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
347␉␉␉return true;␊
348␉␉}␊
349␉}␊
350␊
351␉return false;␊
352//␉value->dword = 800;␊
353//␉return true;␊
354}␊
355␊
356bool getSMBMemoryDeviceManufacturer(returnType *value)␊
357{␊
358␉static int idx = -1;␊
359␉int␉map;␊
360␊
361␉idx++;␊
362␉if (idx < MAX_RAM_SLOTS) {␊
363␉␉map = Platform.DMI.DIMM[idx];␊
364␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
365␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
366␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
367␉␉␉return true;␊
368␉␉}␊
369␉}␊
370␊
371␉if (!bootInfo->memDetect) {␊
372␉␉return false;␊
373␉}␊
374␉value->string = NOT_AVAILABLE;␊
375␉return true;␊
376}␊
377␊
378bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
379{␊
380␉static int idx = -1;␊
381␉int␉map;␊
382␊
383␉idx++;␊
384␊
385␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
386␊
387␉if (idx < MAX_RAM_SLOTS) {␊
388␉␉map = Platform.DMI.DIMM[idx];␊
389␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
390␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
391␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
392␉␉␉return true;␊
393␉␉}␊
394␉}␊
395␊
396␉if (!bootInfo->memDetect) {␊
397␉␉return false;␊
398␉}␊
399␉value->string = NOT_AVAILABLE;␊
400␉return true;␊
401}␊
402␊
403bool getSMBMemoryDevicePartNumber(returnType *value)␊
404{␊
405␉static int idx = -1;␊
406␉int␉map;␊
407␊
408␉idx++;␊
409␉if (idx < MAX_RAM_SLOTS) {␊
410␉␉map = Platform.DMI.DIMM[idx];␊
411␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
412␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
413␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
414␉␉␉return true;␊
415␉␉}␊
416␉}␊
417␊
418␉if (!bootInfo->memDetect) {␊
419␉␉return false;␊
420␉}␊
421␉value->string = NOT_AVAILABLE;␊
422␉return true;␊
423}␊
424␊
425␊
426// getting smbios addr with fast compare ops, late checksum testing ...␊
427#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
428static const char * const SMTAG = "_SM_";␊
429static const char* const DMITAG = "_DMI_";␊
430␊
431SMBEntryPoint *getAddressOfSmbiosTable(void)␊
432{␊
433␉SMBEntryPoint␉*smbios;␊
434␉/*␊
435␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
436␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
437␉ */␊
438␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
439␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
440␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
441␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
442␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
443␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
444␉␉␉return smbios;␊
445␉ }␊
446␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
447␉}␊
448␉printf("ERROR: Unable to find SMBIOS!\n");␊
449␉pause();␊
450␉return NULL;␊
451}␊
452␊
453

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