Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
34␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉case CPU_MODEL_HASWELL:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
38␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
39␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
40␊
41␉␉␉␉␉␉value->word = 0;␊
42␉␉␉␉␉␉break;␊
43␉␉␉␉␉default:␊
44␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
45␉␉␉␉}␊
46␉␉␉}␊
47␉␉␉␉break;␊
48␊
49␉␉␉default:␊
50␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
51␉␉}␊
52␉} else {␊
53␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
54␉}␊
55␊
56␉return true;␊
57}␊
58␊
59bool getProcessorInformationMaximumClock(returnType *value)␊
60{␊
61␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
62␉return true;␊
63}␊
64␊
65bool getSMBOemProcessorBusSpeed(returnType *value)␊
66{␊
67␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
68␉{␊
69␉␉switch (Platform.CPU.Family)␊
70␉␉{␊
71␉␉␉case 0x06:␊
72␉␉␉{␊
73␉␉␉␉switch (Platform.CPU.Model) {␊
74␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
75␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
76␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
77␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
78␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
79␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
80␉␉␉␉␉␉return false;␊
81␊
82␉␉␉␉␉case 0x19:␊
83␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
84␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
85␉␉␉␉␉case CPU_MODEL_DALES:␊
86␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
87␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
88␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
89␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
90␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
91␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
92␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
93␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
94␉␉␉␉␉case CPU_MODEL_HASWELL:␊
95␉␉␉␉␉{␊
96␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
97␉␉␉␉␉␉int nhm_bus = 0x3F;␊
98␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
99␉␉␉␉␉␉unsigned long did, vid;␊
100␉␉␉␉␉␉unsigned int i;␊
101␉␉␉␉␉␉␊
102␉␉␉␉␉␉// Nehalem supports Scrubbing␊
103␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
104␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
105␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
106␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
107␉␉␉␉␉␉␉vid &= 0xFFFF;␊
108␉␉␉␉␉␉␉did &= 0xFF00;␊
109␉␉␉␉␉␉␉␊
110␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
111␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
112␉␉␉␉␉␉␉}␊
113␉␉␉␉␉␉}␊
114␊
115␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
116␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
117␉␉␉␉␉␉qpimult &= 0x7F;␊
118␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
119␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
120␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
121␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
122␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
123␉␉␉␉␉␉}␊
124␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
125␉␉␉␉␉␉value->word = qpibusspeed;␊
126␉␉␉␉␉␉return true;␊
127␉␉␉␉␉}␊
128␉␉␉␉␉default:␊
129␉␉␉␉␉␉break; //Unsupported CPU type␊
130␉␉␉␉}␊
131␉␉␉}␊
132␉␉␉default:␊
133␉␉␉␉break;␊
134␉␉}␊
135␉}␊
136␉return false;␊
137}␊
138␊
139uint16_t simpleGetSMBOemProcessorType(void)␊
140{␊
141␉if (Platform.CPU.NoCores >= 4) {␊
142␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊
143␉} else if (Platform.CPU.NoCores == 1) {␊
144␉␉return 0x201;␉// 513 - Core Duo␊
145␉};␊
146␉␊
147␉return 0x301;␉␉// 769 - Core 2 Duo␊
148}␊
149␊
150bool getSMBOemProcessorType(returnType *value)␊
151{␊
152␉static bool done = false;␊
153␊
154␉value->word = simpleGetSMBOemProcessorType();␊
155␊
156␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
157␉␉if (!done) {␊
158␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
159␉␉␉done = true;␊
160␉␉}␊
161␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
162␉␉switch (Platform.CPU.Family) {␊
163␉␉␉case 0x0F:␊
164␉␉␉case 0x06:␊
165␉␉␉{␊
166␉␉␉␉switch (Platform.CPU.Model) {␊
167␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
168␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
169␉␉␉␉␉case CPU_MODEL_PRESCOTT:␊
170␉␉␉␉␉case CPU_MODEL_NOCONA:␊
171␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
172␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
173␉␉␉␉␉␉}␊
174␉␉␉␉␉␉return true;␊
175␊
176␉␉␉␉␉case CPU_MODEL_PRESLER:␊
177␉␉␉␉␉case CPU_MODEL_CELERON:␊
178␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
179␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
180␉␉␉␉␉␉return true;␊
181␊
182␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
183␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
184␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
185␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
186␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
187␉␉␉␉␉␉return true;␊
188␉␉␉␉␉␉}␊
189␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
190␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
191␉␉␉␉␉␉} else {␊
192␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
193␉␉␉␉␉␉}␊
194␉␉␉␉␉␉return true;␊
195␊
196␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
197␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
198␉␉␉␉␉␉return true;␊
199␊
200␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
201␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
202␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
203␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
204␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
205␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
206␉␉␉␉␉␉␉return true;␊
207␉␉␉␉␉␉}␊
208␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
209␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
210␉␉␉␉␉␉␉return true;␊
211␉␉␉␉␉␉}␊
212␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
213␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
214␉␉␉␉␉␉␉return true;␊
215␉␉␉␉␉␉}␊
216␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
217␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
218␉␉␉␉␉␉␉return true;␊
219␉␉␉␉␉␉}␊
220␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
221␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
222␉␉␉␉␉␉}␊
223␉␉␉␉␉␉return true;␊
224␊
225␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
226␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
227␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
228␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
229␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
230␉␉␉␉␉␉␉return true;␊
231␉␉␉␉␉␉}␊
232␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
233␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
234␉␉␉␉␉␉␉return true;␊
235␉␉␉␉␉␉}␊
236␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
237␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
238␉␉␉␉␉␉␉return true;␊
239␉␉␉␉␉␉}␊
240␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
241␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
242␉␉␉␉␉␉␉return true;␊
243␉␉␉␉␉␉}␊
244␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
245␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
246␉␉␉␉␉␉}␊
247␉␉␉␉␉␉return true;␊
248␊
249␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
250␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
251␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
252␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
253␉␉␉␉␉␉␉return true;␊
254␉␉␉␉␉␉}␊
255␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
256␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
257␉␉␉␉␉␉␉return true;␊
258␉␉␉␉␉␉}␊
259␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
260␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
261␉␉␉␉␉␉␉return true;␊
262␉␉␉␉␉␉}␊
263␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
264␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
265␉␉␉␉␉␉␉return true;␊
266␉␉␉␉␉␉}␊
267␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
268␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
269␉␉␉␉␉␉}␊
270␉␉␉␉␉␉return true;␊
271␊
272␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
273␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
274␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
275␉␉␉␉␉␉␉return true;␊
276␉␉␉␉␉␉}␊
277␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
278␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
279␉␉␉␉␉␉␉return true;␊
280␉␉␉␉␉␉}␊
281␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
282␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
283␉␉␉␉␉␉␉return true;␊
284␉␉␉␉␉␉}␊
285␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
286␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
287␉␉␉␉␉␉␉return true;␊
288␉␉␉␉␉␉}␊
289␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
290␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
291␉␉␉␉␉␉}␊
292␉␉␉␉␉␉return true;␊
293␊
294␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
295␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
296␉␉␉␉␉␉return true;␊
297␊
298␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
299␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
300␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
301␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
302␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
303␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
304␉␉␉␉␉␉␉return true;␊
305␉␉␉␉␉␉}␊
306␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
307␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
308␉␉␉␉␉␉␉return true;␊
309␉␉␉␉␉␉}␊
310␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
311␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
312␉␉␉␉␉␉␉return true;␊
313␉␉␉␉␉␉}␊
314␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
315␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
316␉␉␉␉␉␉␉return true;␊
317␉␉␉␉␉␉}␊
318␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
319␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
320␉␉␉␉␉␉}␊
321␉␉␉␉␉␉return true;␊
322␊
323␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
324␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
325␉␉␉␉␉␉return true;␊
326␊
327␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
328␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
329␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
330␉␉␉␉␉␉return true;␊
331␉␉␉␉␉default:␊
332␉␉␉␉␉␉break; //Unsupported CPU type␊
333␉␉␉␉}␊
334␉␉␉}␊
335␉␉␉default:␊
336␉␉␉␉break;␊
337␉␉}␊
338␉}␊
339␉␊
340␉return false;␊
341}␊
342␊
343bool getSMBMemoryDeviceMemoryType(returnType *value)␊
344{␊
345␉static int idx = -1;␊
346␉int␉map;␊
347␊
348␉if (!bootInfo->memDetect) {␊
349␉␉return false;␊
350␉}␊
351␊
352␉idx++;␊
353␉if (idx < MAX_RAM_SLOTS) {␊
354␉␉map = Platform.DMI.DIMM[idx];␊
355␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
356␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
357␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
358␉␉␉return true;␊
359␉␉}␊
360␉}␊
361␊
362␉value->byte = 2; // means Unknown␊
363␉return true;␊
364//␉value->byte = SMB_MEM_TYPE_DDR2;␊
365//␉return true;␊
366}␊
367␊
368bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
369{␊
370␉value->word = 0xFFFF;␊
371␉return true;␊
372}␊
373␊
374bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
375{␊
376␉static int idx = -1;␊
377␉int␉map;␊
378␊
379␉if (!bootInfo->memDetect) {␊
380␉␉return false;␊
381␉}␊
382␊
383␉idx++;␊
384␉if (idx < MAX_RAM_SLOTS) {␊
385␉␉map = Platform.DMI.DIMM[idx];␊
386␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
387␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
388␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
389␉␉␉return true;␊
390␉␉}␊
391␉}␊
392␊
393␉value->dword = 0; // means Unknown␊
394␉return true;␊
395//␉value->dword = 800;␊
396//␉return true;␊
397}␊
398␊
399bool getSMBMemoryDeviceManufacturer(returnType *value)␊
400{␊
401␉static int idx = -1;␊
402␉int␉map;␊
403␊
404␉if (!bootInfo->memDetect) {␊
405␉␉return false;␊
406␉}␊
407␊
408␉idx++;␊
409␉if (idx < MAX_RAM_SLOTS) {␊
410␉␉map = Platform.DMI.DIMM[idx];␊
411␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
412␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
413␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
414␉␉␉return true;␊
415␉␉}␊
416␉}␊
417␊
418␉value->string = NOT_AVAILABLE;␊
419␉return true;␊
420}␊
421␊
422bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
423{␊
424␉static int idx = -1;␊
425␉int␉map;␊
426␊
427␉if (!bootInfo->memDetect) {␊
428␉␉return false;␊
429␉}␊
430␊
431␉idx++;␊
432␊
433␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
434␊
435␉if (idx < MAX_RAM_SLOTS) {␊
436␉␉map = Platform.DMI.DIMM[idx];␊
437␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
438␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
439␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
440␉␉␉return true;␊
441␉␉}␊
442␉}␊
443␊
444␉value->string = NOT_AVAILABLE;␊
445␉return true;␊
446}␊
447␊
448bool getSMBMemoryDevicePartNumber(returnType *value)␊
449{␊
450␉static int idx = -1;␊
451␉int␉map;␊
452␊
453␉if (!bootInfo->memDetect) {␊
454␉␉return false;␊
455␉}␊
456␊
457␉idx++;␊
458␉if (idx < MAX_RAM_SLOTS) {␊
459␉␉map = Platform.DMI.DIMM[idx];␊
460␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
461␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
462␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
463␉␉␉return true;␊
464␉␉}␊
465␉}␊
466␊
467␉value->string = NOT_AVAILABLE;␊
468␉return true;␊
469}␊
470␊
471␊
472// getting smbios addr with fast compare ops, late checksum testing ...␊
473#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
474static const char * const SMTAG = "_SM_";␊
475static const char* const DMITAG = "_DMI_";␊
476␊
477SMBEntryPoint *getAddressOfSmbiosTable(void)␊
478{␊
479␉SMBEntryPoint␉*smbios;␊
480␉/*␊
481␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
482␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
483␉ */␊
484␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
485␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
486␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
487␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
488␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
489␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
490␉␉␉return smbios;␊
491␉ }␊
492␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
493␉}␊
494␉printf("ERROR: Unable to find SMBIOS!\n");␊
495␉pause();␊
496␉return NULL;␊
497}␊
498␊
499

Archive Download this file

Revision: 2456