| 1 | /*␊ |
| 2 | * platform.h␊ |
| 3 | * AsereBLN: reworked and extended␊ |
| 4 | *␊ |
| 5 | */␊ |
| 6 | ␊ |
| 7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
| 8 | #define __LIBSAIO_PLATFORM_H␊ |
| 9 | ␊ |
| 10 | //#include "libsaio.h"␊ |
| 11 | ␊ |
| 12 | extern bool platformCPUFeature(uint32_t);␊ |
| 13 | extern void scan_platform(void);␊ |
| 14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
| 15 | ␊ |
| 16 | ␊ |
| 17 | #define CPU_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊ |
| 18 | #define CPU_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊ |
| 19 | #define CPU_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊ |
| 20 | #define CPU_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊ |
| 21 | #define CPU_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊ |
| 22 | #define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊ |
| 23 | #define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊ |
| 24 | #define CPU_MODEL_CONROE␉␉0x0F␉␉␉// ␊ |
| 25 | #define CPU_MODEL_CELERON␉␉0x16␉␉␉// Merom, Conroe (65nm)␊ |
| 26 | #define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊ |
| 27 | #define CPU_MODEL_WOLFDALE␉␉0x17␉␉␉// ␊ |
| 28 | #define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊ |
| 29 | #define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Pineview, Bonnell␊ |
| 30 | #define CPU_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊ |
| 31 | #define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊ |
| 32 | #define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊ |
| 33 | #define CPU_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊ |
| 34 | #define CPU_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊ |
| 35 | #define CPU_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊ |
| 36 | #define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊ |
| 37 | #define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
| 38 | #define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊ |
| 39 | #define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊ |
| 40 | #define CPU_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊ |
| 41 | //#define CPU_MODEL_BONNELL_ATOM␉0x35␉␉␉// Bonnell␊ |
| 42 | #define CPU_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊ |
| 43 | #define CPU_MODEL_SILVERMONT␉␉0x37␉␉␉// Atom Silvermont␊ |
| 44 | #define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊ |
| 45 | #define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊ |
| 46 | #define CPU_MODEL_BROADWELL␉␉0x3D␉␉␉// Core M, Broadwell / Core-AVX2␊ |
| 47 | #define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊ |
| 48 | #define CPU_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server␊ |
| 49 | //#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊ |
| 50 | #define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊ |
| 51 | #define CPU_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Crystal Well␊ |
| 52 | // 4A silvermont / atom␊ |
| 53 | #define CPU_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000␊ |
| 54 | // 4E Core???␊ |
| 55 | #define CPU_MODEL_BRODWELL_SVR␉␉0x4F␉␉␉// Broadwell Server␊ |
| 56 | #define CPU_MODEL_BRODWELL_MSVR␉␉0x56␉␉␉// Broadwell Micro Server␊ |
| 57 | // 5A silvermont / atom␊ |
| 58 | // 5D silvermont / atom␊ |
| 59 | ␊ |
| 60 | /* CPUID Vendor */␊ |
| 61 | #define CPUID_VENDOR_INTEL 0x756E6547␊ |
| 62 | #define CPUID_VENDOR_AMD 0x68747541␊ |
| 63 | ␊ |
| 64 | /* Unknown CPU */␊ |
| 65 | #define CPU_STRING_UNKNOWN␉"Unknown CPU Type"␊ |
| 66 | #define bit(n)␉␉␉(1ULL << (n))␊ |
| 67 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| 68 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 69 | ␊ |
| 70 | ␊ |
| 71 | /*␊ |
| 72 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
| 73 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
| 74 | */␊ |
| 75 | #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
| 76 | #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
| 77 | #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
| 78 | #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
| 79 | #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
| 80 | #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
| 81 | #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
| 82 | #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
| 83 | #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
| 84 | #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
| 85 | #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
| 86 | #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
| 87 | #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
| 88 | #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
| 89 | #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
| 90 | #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
| 91 | #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
| 92 | #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
| 93 | #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
| 94 | #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
| 95 | #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
| 96 | #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
| 97 | #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
| 98 | #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
| 99 | #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
| 100 | #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
| 101 | #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
| 102 | #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
| 103 | #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
| 104 | ␊ |
| 105 | #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
| 106 | #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
| 107 | #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
| 108 | #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
| 109 | #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
| 110 | #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
| 111 | #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
| 112 | #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
| 113 | #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
| 114 | #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
| 115 | #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
| 116 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
| 117 | #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊ |
| 118 | #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
| 119 | #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
| 120 | #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
| 121 | ␊ |
| 122 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
| 123 | #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
| 124 | #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
| 125 | #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
| 126 | #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊ |
| 127 | #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
| 128 | #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
| 129 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
| 130 | #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
| 131 | #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
| 132 | #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
| 133 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
| 134 | #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
| 135 | #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
| 136 | #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
| 137 | ␊ |
| 138 | /*␊ |
| 139 | * Leaf 7, subleaf 0 additional features.␊ |
| 140 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
| 141 | */␊ |
| 142 | #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
| 143 | #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊ |
| 144 | #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
| 145 | #define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊ |
| 146 | #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊ |
| 147 | #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
| 148 | #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
| 149 | #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
| 150 | #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊ |
| 151 | #define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊ |
| 152 | ␊ |
| 153 | /*␊ |
| 154 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 155 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
| 156 | */␊ |
| 157 | #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
| 158 | #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
| 159 | ␊ |
| 160 | #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
| 161 | #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
| 162 | #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
| 163 | ␊ |
| 164 | #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
| 165 | ␊ |
| 166 | /*␊ |
| 167 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 168 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
| 169 | */␊ |
| 170 | #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
| 171 | ␊ |
| 172 | #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
| 173 | ␊ |
| 174 | #define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊ |
| 175 | #define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊ |
| 176 | ␊ |
| 177 | //-- processor type -> p_type:␊ |
| 178 | #define PT_OEM␉0x00␉// Intel Original OEM Processor;␊ |
| 179 | #define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊ |
| 180 | #define PT_DUAL␉0x02␉// Intel Dual Processor;␊ |
| 181 | #define PT_RES␉0x03␉// Intel Reserved;␊ |
| 182 | ␊ |
| 183 | /* Known MSR registers */␊ |
| 184 | #define MSR_IA32_PLATFORM_ID 0x0017␊ |
| 185 | #define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊ |
| 186 | #define IA32_TSC_ADJUST 0x003B␊ |
| 187 | #define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊ |
| 188 | #define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊ |
| 189 | #define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
| 190 | /* turbo for penryn */␊ |
| 191 | #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊ |
| 192 | #define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊ |
| 193 | #define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊ |
| 194 | #define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊ |
| 195 | #define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊ |
| 196 | #define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊ |
| 197 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
| 198 | #define␉MSR_IA32_PERF_STATUS 0x0198␊ |
| 199 | #define MSR_IA32_PERF_CONTROL 0x0199␊ |
| 200 | #define MSR_IA32_CLOCK_MODULATION 0x019A␊ |
| 201 | #define MSR_THERMAL_STATUS 0x019C␊ |
| 202 | #define MSR_IA32_MISC_ENABLE 0x01A0␊ |
| 203 | #define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊ |
| 204 | #define MSR_MISC_PWR_MGMT 0x01AA␊ |
| 205 | #define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊ |
| 206 | ␊ |
| 207 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
| 208 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
| 209 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
| 210 | #define MSR_POWER_CTL␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊ |
| 211 | ␊ |
| 212 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
| 213 | #define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊ |
| 214 | //MSR 00000606 0000-0000-000A-1003␊ |
| 215 | #define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */␊ |
| 216 | // bit 15 = 1 -- the value valid for C-state PM␊ |
| 217 | #define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */␊ |
| 218 | //MSR 0000060B 0000-0000-0000-8854␊ |
| 219 | //Valid + 010=1024ns + 0x54=84mks␊ |
| 220 | #define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */␊ |
| 221 | //MSR 0000060C 0000-0000-0000-8854␊ |
| 222 | #define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */␊ |
| 223 | ␊ |
| 224 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊ |
| 225 | #define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊ |
| 226 | #define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊ |
| 227 | ␊ |
| 228 | //AMD␊ |
| 229 | #define K8_FIDVID_STATUS 0xC0010042␊ |
| 230 | #define K10_COFVID_LIMIT 0xC0010061␊ |
| 231 | #define K10_PSTATE_STATUS 0xC0010064␊ |
| 232 | #define K10_COFVID_STATUS 0xC0010071␊ |
| 233 | ␊ |
| 234 | #define MSR_AMD_MPERF 0x000000E7␊ |
| 235 | #define MSR_AMD_APERF 0x000000E8␊ |
| 236 | ␊ |
| 237 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| 238 | ␊ |
| 239 | // DFE: This constant comes from older xnu:␊ |
| 240 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| 241 | ␊ |
| 242 | /* CPUID index into cpuid_raw */␊ |
| 243 | #define CPUID_0␉␉␉␉0␊ |
| 244 | #define CPUID_1␉␉␉␉1␊ |
| 245 | #define CPUID_2␉␉␉␉2␊ |
| 246 | #define CPUID_3␉␉␉␉3␊ |
| 247 | #define CPUID_4␉␉␉␉4␊ |
| 248 | #define CPUID_5␉␉␉␉5␊ |
| 249 | #define CPUID_6␉␉␉␉6␊ |
| 250 | #define CPUID_80␉␉␉7␊ |
| 251 | #define CPUID_81␉␉␉8␊ |
| 252 | #define CPUID_88␉␉␉9␊ |
| 253 | #define CPUID_MAX␉␉␉10␊ |
| 254 | ␊ |
| 255 | /* CPU Features */␊ |
| 256 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊ |
| 257 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊ |
| 258 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊ |
| 259 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊ |
| 260 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊ |
| 261 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊ |
| 262 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊ |
| 263 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊ |
| 264 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊ |
| 265 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊ |
| 266 | ␊ |
| 267 | /* SMBIOS Memory Types */ ␊ |
| 268 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
| 269 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
| 270 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
| 271 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
| 272 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
| 273 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
| 274 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
| 275 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
| 276 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
| 277 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
| 278 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
| 279 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
| 280 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
| 281 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
| 282 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
| 283 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
| 284 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
| 285 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
| 286 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
| 287 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
| 288 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
| 289 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
| 290 | #define SMB_MEM_TYPE_DDR4␉␉26␊ |
| 291 | ␊ |
| 292 | /* Memory Configuration Types */ ␊ |
| 293 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
| 294 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
| 295 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
| 296 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
| 297 | ␊ |
| 298 | /* Maximum number of ram slots */␊ |
| 299 | #define MAX_RAM_SLOTS␉␉␉8␊ |
| 300 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
| 301 | ␊ |
| 302 | /* Maximum number of SPD bytes */␊ |
| 303 | #define MAX_SPD_SIZE␉␉␉256␊ |
| 304 | ␊ |
| 305 | /* Size of SMBIOS UUID in bytes */␊ |
| 306 | #define UUID_LEN␉␉␉16␊ |
| 307 | ␊ |
| 308 | typedef struct _RamSlotInfo_t␊ |
| 309 | {␊ |
| 310 | ␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊ |
| 311 | ␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊ |
| 312 | ␉const char*␉␉Vendor;␊ |
| 313 | ␉const char*␉␉PartNo;␊ |
| 314 | ␉const char*␉␉SerialNo;␊ |
| 315 | ␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊ |
| 316 | ␉bool␉␉␉InUse;␊ |
| 317 | ␉uint8_t␉␉␉Type;␊ |
| 318 | ␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊ |
| 319 | ␉uint8_t␉␉␉BankConnCnt;␊ |
| 320 | } RamSlotInfo_t;␊ |
| 321 | ␊ |
| 322 | //==============================================================================␊ |
| 323 | ␊ |
| 324 | typedef struct _PlatformInfo_t␊ |
| 325 | {␊ |
| 326 | ␉struct CPU {␊ |
| 327 | ␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor - char Vendor[16];␊ |
| 328 | ␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊ |
| 329 | ␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊ |
| 330 | ␉␉uint8_t␉␉␉Family;␉␉␉␉␉// Family␊ |
| 331 | ␉␉uint8_t␉␉␉Model;␉␉␉␉␉// Model␊ |
| 332 | ␉␉uint8_t␉␉␉ExtModel;␉␉␉␉// Extended Model␊ |
| 333 | ␉␉uint8_t␉␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
| 334 | ␉␉uint8_t␉␉␉Stepping;␉␉␉␉// Stepping␊ |
| 335 | ␉␉uint64_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
| 336 | ␉␉uint64_t␉␉ExtFeatures;␊ |
| 337 | ␉␉uint32_t␉␉CoresPerPackage;␊ |
| 338 | ␉␉uint32_t␉␉LogicalPerPackage;␊ |
| 339 | ␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊ |
| 340 | ␉␉//uint8_t␉␉Brand;␊ |
| 341 | ␉␉//uint8_t␉␉ProcessorFlag;␊ |
| 342 | ␊ |
| 343 | ␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
| 344 | ␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
| 345 | ␊ |
| 346 | ␉␉//uint32_t␉␉CacheSize[LCACHE_MAX];␊ |
| 347 | ␉␉//uint32_t␉␉CacheLineSize;␊ |
| 348 | ␊ |
| 349 | ␉␉//uint8_t␉␉cache_info[64];␉␉␉␉// list of cache descriptors␊ |
| 350 | ␊ |
| 351 | ␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊ |
| 352 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊ |
| 353 | ␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊ |
| 354 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
| 355 | ␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊ |
| 356 | ␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊ |
| 357 | ␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊ |
| 358 | ␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊ |
| 359 | ␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊ |
| 360 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊ |
| 361 | ␊ |
| 362 | ␉␉uint32_t␉␉MCodeVersion; // CPU Microcode version␊ |
| 363 | ␉} CPU;␊ |
| 364 | ␊ |
| 365 | ␉struct RAM {␊ |
| 366 | ␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
| 367 | ␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊ |
| 368 | ␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
| 369 | ␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊ |
| 370 | ␉␉uint8_t␉␉␉TRP;␊ |
| 371 | ␉␉uint8_t␉␉␉RAS;␊ |
| 372 | ␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
| 373 | ␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
| 374 | ␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
| 375 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
| 376 | ␉} RAM;␊ |
| 377 | ␊ |
| 378 | ␉struct DMI {␊ |
| 379 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots populated by SMBIOS␊ |
| 380 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
| 381 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
| 382 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
| 383 | ␉} DMI;␊ |
| 384 | ␊ |
| 385 | ␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊ |
| 386 | ␉uint8_t␉␉␉␉*UUID;␊ |
| 387 | } PlatformInfo_t;␊ |
| 388 | ␊ |
| 389 | extern PlatformInfo_t Platform;␊ |
| 390 | ␊ |
| 391 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
| 392 | |
