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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
25␉␉switch (Platform.CPU.Family) {␊
26␉␉␉case 0x06:␊
27␉␉␉{␊
28␉␉␉␉switch (Platform.CPU.Model)␊
29␉␉␉␉{␊
30␉␉␉␉␉// set external clock to 0 for SANDY␊
31␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
32␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
33␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
34␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
35␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
36␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
37␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
38␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
39␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
40␊
41␉␉␉␉␉␉value->word = 0;␊
42␉␉␉␉␉␉break;␊
43␉␉␉␉␉default:␊
44␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
45␉␉␉␉}␊
46␉␉␉}␊
47␉␉␉␉break;␊
48␊
49␉␉␉default:␊
50␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
51␉␉}␊
52␉} else {␊
53␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
54␉}␊
55␊
56␉return true;␊
57}␊
58␊
59bool getProcessorInformationMaximumClock(returnType *value)␊
60{␊
61␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
62␉return true;␊
63}␊
64␊
65bool getSMBOemProcessorBusSpeed(returnType *value)␊
66{␊
67␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
68␉{␊
69␉␉switch (Platform.CPU.Family)␊
70␉␉{␊
71␉␉␉case 0x06:␊
72␉␉␉{␊
73␉␉␉␉switch (Platform.CPU.Model)␊
74␉␉␉␉{␊
75␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
76␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
77␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
78␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
79␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
80␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
81␉␉␉␉␉␉return false;␊
82␊
83␉␉␉␉␉case 0x19:␊
84␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
85␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
86␉␉␉␉␉case CPUID_MODEL_DALES:␊
87␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
88␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
89␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
90␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
91␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
92␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
93␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
94␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
95␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
96␉␉␉␉␉{␊
97␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
98␉␉␉␉␉␉int nhm_bus = 0x3F;␊
99␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
100␉␉␉␉␉␉unsigned long did, vid;␊
101␉␉␉␉␉␉unsigned int i;␊
102␉␉␉␉␉␉␊
103␉␉␉␉␉␉// Nehalem supports Scrubbing␊
104␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
105␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊
106␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
107␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
108␉␉␉␉␉␉␉vid &= 0xFFFF;␊
109␉␉␉␉␉␉␉did &= 0xFF00;␊
110␉␉␉␉␉␉␉␊
111␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊
112␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
113␉␉␉␉␉␉␉}␊
114␉␉␉␉␉␉}␊
115␊
116␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
117␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
118␉␉␉␉␉␉qpimult &= 0x7F;␊
119␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
120␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
121␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
122␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
123␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
124␉␉␉␉␉␉}␊
125␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
126␉␉␉␉␉␉value->word = qpibusspeed;␊
127␉␉␉␉␉␉return true;␊
128␉␉␉␉␉}␊
129␉␉␉␉␉default:␊
130␉␉␉␉␉␉break; //Unsupported CPU type␊
131␉␉␉␉}␊
132␉␉␉}␊
133␉␉␉default:␊
134␉␉␉␉break;␊
135␉␉}␊
136␉}␊
137␉return false;␊
138}␊
139␊
140uint16_t simpleGetSMBOemProcessorType(void)␊
141{␊
142␉if (Platform.CPU.NoCores >= 4) {␊
143␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊
144␉} else if (Platform.CPU.NoCores == 1) {␊
145␉␉return 0x201;␉// 513 - Core Duo␊
146␉};␊
147␉␊
148␉return 0x301;␉␉// 769 - Core 2 Duo␊
149}␊
150␊
151bool getSMBOemProcessorType(returnType *value)␊
152{␊
153␉static bool done = false;␊
154␊
155␉value->word = simpleGetSMBOemProcessorType();␊
156␊
157␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊
158␉␉if (!done) {␊
159␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
160␉␉␉done = true;␊
161␉␉}␊
162␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
163␉␉switch (Platform.CPU.Family) {␊
164␉␉␉case 0x0F:␊
165␉␉␉case 0x06:␊
166␉␉␉{␊
167␉␉␉␉switch (Platform.CPU.Model)␊
168␉␉␉␉{␊
169␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
170␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
171␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
172␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
173␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
174␉␉␉␉␉␉{␊
175␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
176␉␉␉␉␉␉}␊
177␉␉␉␉␉␉return true;␊
178␊
179␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
180␉␉␉␉␉case CPUID_MODEL_CELERON:␊
181␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
182␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
183␉␉␉␉␉␉return true;␊
184␊
185␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
186␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
187␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
188␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
189␉␉␉␉␉␉{␊
190␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
191␉␉␉␉␉␉return true;␊
192␉␉␉␉␉␉}␊
193␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
194␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
195␉␉␉␉␉␉} else {␊
196␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
197␉␉␉␉␉␉}␊
198␉␉␉␉␉␉return true;␊
199␊
200␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
201␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
202␉␉␉␉␉␉return true;␊
203␊
204␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
205␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
206␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
207␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
208␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
209␉␉␉␉␉␉{␊
210␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
211␉␉␉␉␉␉␉return true;␊
212␉␉␉␉␉␉}␊
213␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
214␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
215␉␉␉␉␉␉␉return true;␊
216␉␉␉␉␉␉}␊
217␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
218␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
219␉␉␉␉␉␉␉return true;␊
220␉␉␉␉␉␉}␊
221␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
222␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
223␉␉␉␉␉␉␉return true;␊
224␉␉␉␉␉␉}␊
225␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
226␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
227␉␉␉␉␉␉}␊
228␉␉␉␉␉␉return true;␊
229␊
230␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
231␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
232␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
233␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
234␉␉␉␉␉␉{␊
235␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
236␉␉␉␉␉␉␉return true;␊
237␉␉␉␉␉␉}␊
238␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
239␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
240␉␉␉␉␉␉␉return true;␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
243␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
244␉␉␉␉␉␉␉return true;␊
245␉␉␉␉␉␉}␊
246␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
247␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
248␉␉␉␉␉␉␉return true;␊
249␉␉␉␉␉␉}␊
250␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
251␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
252␉␉␉␉␉␉}␊
253␉␉␉␉␉␉return true;␊
254␊
255␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
256␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
257␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
258␉␉␉␉␉␉{␊
259␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
260␉␉␉␉␉␉␉return true;␊
261␉␉␉␉␉␉}␊
262␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
263␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
264␉␉␉␉␉␉␉return true;␊
265␉␉␉␉␉␉}␊
266␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
267␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
268␉␉␉␉␉␉␉return true;␊
269␉␉␉␉␉␉}␊
270␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
271␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
272␉␉␉␉␉␉␉return true;␊
273␉␉␉␉␉␉}␊
274␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
275␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
276␉␉␉␉␉␉}␊
277␉␉␉␉␉␉return true;␊
278␊
279␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
280␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
281␉␉␉␉␉␉{␊
282␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
283␉␉␉␉␉␉␉return true;␊
284␉␉␉␉␉␉}␊
285␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
286␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
287␉␉␉␉␉␉␉return true;␊
288␉␉␉␉␉␉}␊
289␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
290␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
291␉␉␉␉␉␉␉return true;␊
292␉␉␉␉␉␉}␊
293␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
294␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
295␉␉␉␉␉␉␉return true;␊
296␉␉␉␉␉␉}␊
297␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
298␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
299␉␉␉␉␉␉}␊
300␉␉␉␉␉␉return true;␊
301␊
302␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
303␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
304␉␉␉␉␉␉return true;␊
305␊
306␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊
307␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
308␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
309␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
310␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
311␉␉␉␉␉␉{␊
312␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
313␉␉␉␉␉␉␉return true;␊
314␉␉␉␉␉␉}␊
315␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
316␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
317␉␉␉␉␉␉␉return true;␊
318␉␉␉␉␉␉}␊
319␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
320␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
321␉␉␉␉␉␉␉return true;␊
322␉␉␉␉␉␉}␊
323␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
324␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
325␉␉␉␉␉␉␉return true;␊
326␉␉␉␉␉␉}␊
327␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
328␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
329␉␉␉␉␉␉}␊
330␉␉␉␉␉␉return true;␊
331␊
332␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
333␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
334␉␉␉␉␉␉return true;␊
335␊
336␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
337␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
338␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
339␉␉␉␉␉␉return true;␊
340␉␉␉␉␉default:␊
341␉␉␉␉␉␉break; //Unsupported CPU type␊
342␉␉␉␉}␊
343␉␉␉}␊
344␉␉␉default:␊
345␉␉␉␉break;␊
346␉␉}␊
347␉}␊
348␉␊
349␉return false;␊
350}␊
351␊
352bool getSMBMemoryDeviceMemoryType(returnType *value)␊
353{␊
354␉static int idx = -1;␊
355␉int␉map;␊
356␊
357␉if (!bootInfo->memDetect) {␊
358␉␉return false;␊
359␉}␊
360␊
361␉idx++;␊
362␉if (idx < MAX_RAM_SLOTS) {␊
363␉␉map = Platform.DMI.DIMM[idx];␊
364␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊
365␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
366␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
367␉␉␉return true;␊
368␉␉}␊
369␉}␊
370␊
371␉value->byte = 2; // means Unknown␊
372␉return true;␊
373//␉value->byte = SMB_MEM_TYPE_DDR2;␊
374//␉return true;␊
375}␊
376␊
377bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
378{␊
379␉value->word = 0xFFFF;␊
380␉return true;␊
381}␊
382␊
383bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
384{␊
385␉static int idx = -1;␊
386␉int␉map;␊
387␊
388␉if (!bootInfo->memDetect) {␊
389␉␉return false;␊
390␉}␊
391␊
392␉idx++;␊
393␉if (idx < MAX_RAM_SLOTS) {␊
394␉␉map = Platform.DMI.DIMM[idx];␊
395␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊
396␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
397␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
398␉␉␉return true;␊
399␉␉}␊
400␉}␊
401␊
402␉value->dword = 0; // means Unknown␊
403␉return true;␊
404//␉value->dword = 800;␊
405//␉return true;␊
406}␊
407␊
408bool getSMBMemoryDeviceManufacturer(returnType *value)␊
409{␊
410␉static int idx = -1;␊
411␉int␉map;␊
412␊
413␉if (!bootInfo->memDetect) {␊
414␉␉return false;␊
415␉}␊
416␊
417␉idx++;␊
418␉if (idx < MAX_RAM_SLOTS) {␊
419␉␉map = Platform.DMI.DIMM[idx];␊
420␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊
421␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
422␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
423␉␉␉return true;␊
424␉␉}␊
425␉}␊
426␊
427␉value->string = NOT_AVAILABLE;␊
428␉return true;␊
429}␊
430␊
431bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
432{␊
433␉static int idx = -1;␊
434␉int␉map;␊
435␊
436␉if (!bootInfo->memDetect) {␊
437␉␉return false;␊
438␉}␊
439␊
440␉idx++;␊
441␊
442␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
443␊
444␉if (idx < MAX_RAM_SLOTS) {␊
445␉␉map = Platform.DMI.DIMM[idx];␊
446␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊
447␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
448␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
449␉␉␉return true;␊
450␉␉}␊
451␉}␊
452␊
453␉value->string = NOT_AVAILABLE;␊
454␉return true;␊
455}␊
456␊
457bool getSMBMemoryDevicePartNumber(returnType *value)␊
458{␊
459␉static int idx = -1;␊
460␉int␉map;␊
461␊
462␉if (!bootInfo->memDetect) {␊
463␉␉return false;␊
464␉}␊
465␊
466␉idx++;␊
467␉if (idx < MAX_RAM_SLOTS) {␊
468␉␉map = Platform.DMI.DIMM[idx];␊
469␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊
470␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
471␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
472␉␉␉return true;␊
473␉␉}␊
474␉}␊
475␊
476␉value->string = NOT_AVAILABLE;␊
477␉return true;␊
478}␊
479␊
480␊
481// getting smbios addr with fast compare ops, late checksum testing ...␊
482#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
483static const char * const SMTAG = "_SM_";␊
484static const char* const DMITAG = "_DMI_";␊
485␊
486SMBEntryPoint *getAddressOfSmbiosTable(void)␊
487{␊
488␉SMBEntryPoint␉*smbios;␊
489␉/*␊
490␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
491␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
492␉ */␊
493␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
494␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
495␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
496␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
497␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
498␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊
499␉␉␉return smbios;␊
500␉ }␊
501␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
502␉}␊
503␉printf("ERROR: Unable to find SMBIOS!\n");␊
504␉pause();␊
505␉return NULL;␊
506}␊
507␊
508

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