1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
24 | */␊ |
25 | static uint64_t measure_tsc_frequency(void)␊ |
26 | {␊ |
27 | ␉uint64_t tscStart;␊ |
28 | ␉uint64_t tscEnd;␊ |
29 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
30 | ␉unsigned long pollCount;␊ |
31 | ␉uint64_t retval = 0;␊ |
32 | ␉int i;␊ |
33 | ␊ |
34 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
35 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
36 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
37 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
38 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
39 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
40 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
41 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
42 | ␉ */␊ |
43 | ␉for(i = 0; i < 10; ++i)␊ |
44 | ␉{␊ |
45 | ␉␉enable_PIT2();␊ |
46 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
47 | ␉␉tscStart = rdtsc64();␊ |
48 | ␉␉pollCount = poll_PIT2_gate();␊ |
49 | ␉␉tscEnd = rdtsc64();␊ |
50 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
51 | ␉␉if (pollCount <= 1)␊ |
52 | ␉␉{␊ |
53 | ␉␉␉continue;␊ |
54 | ␉␉}␊ |
55 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
56 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
57 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
58 | ␉␉ */␊ |
59 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
60 | ␉␉{␊ |
61 | ␉␉␉continue;␊ |
62 | ␉␉}␊ |
63 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
64 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
65 | ␉␉{␊ |
66 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
67 | ␉␉}␊ |
68 | ␉}␊ |
69 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
70 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
71 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
72 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
73 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
74 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
75 | ␉ */␊ |
76 | ␊ |
77 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
78 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
79 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
80 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
81 | ␉ */␊ |
82 | ␉if (tscDelta > (1ULL<<32))␊ |
83 | ␉{␊ |
84 | ␉␉retval = 0;␊ |
85 | ␉}␊ |
86 | ␉else␊ |
87 | ␉{␊ |
88 | ␉␉retval = tscDelta * 1000 / 30;␊ |
89 | ␉}␊ |
90 | ␉disable_PIT2();␊ |
91 | ␉return retval;␊ |
92 | }␊ |
93 | ␊ |
94 | /*␊ |
95 | * timeRDTSC()␊ |
96 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
97 | * It pauses until the value is latched in the counter␊ |
98 | * and then reads the time stamp counter to return to the caller.␊ |
99 | */␊ |
100 | uint64_t timeRDTSC(void)␊ |
101 | {␊ |
102 | ␉int␉␉attempts = 0;␊ |
103 | ␉uint64_t latchTime;␊ |
104 | ␉uint64_t␉saveTime,intermediate;␊ |
105 | ␉unsigned int timerValue, lastValue;␊ |
106 | ␉//boolean_t␉int_enabled;␊ |
107 | ␉/*␊ |
108 | ␉ * Table of correction factors to account for␊ |
109 | ␉ *␉ - timer counter quantization errors, and␊ |
110 | ␉ *␉ - undercounts 0..5␊ |
111 | ␉ */␊ |
112 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
113 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
114 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
115 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
116 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
117 | ␉uint64_t␉scale[6] = {␊ |
118 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
119 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
120 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
121 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
122 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
123 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
124 | ␉};␊ |
125 | ␊ |
126 | ␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊ |
127 | ␊ |
128 | restart:␊ |
129 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
130 | ␉{␊ |
131 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
132 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
133 | ␉}␊ |
134 | ␉attempts++;␊ |
135 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
136 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
137 | ␉latchTime = rdtsc64();␉// get the time stamp to time ␊ |
138 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
139 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
140 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
141 | ␉get_PIT2(&lastValue);␊ |
142 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
143 | ␉do {␊ |
144 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
145 | ␉␉if (timerValue > lastValue)␊ |
146 | ␉␉{␊ |
147 | ␉␉␉// Timer wrapped␊ |
148 | ␉␉␉set_PIT2(0);␊ |
149 | ␉␉␉disable_PIT2();␊ |
150 | ␉␉␉goto restart;␊ |
151 | ␉␉}␊ |
152 | ␉␉lastValue = timerValue;␊ |
153 | ␉} while (timerValue > 5);␊ |
154 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
155 | ␉printf("intermediate 0x%016llx\n",intermediate);␊ |
156 | ␉printf("saveTime␉ 0x%016llx\n",saveTime);␊ |
157 | ␊ |
158 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
159 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
160 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
161 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
162 | ␊ |
163 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
164 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
165 | ␉␊ |
166 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
167 | ␉return intermediate;␊ |
168 | }␊ |
169 | ␊ |
170 | /*␊ |
171 | * Original comment/code:␊ |
172 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
173 | *␊ |
174 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
175 | * (just a naming change, mperf --> aperf )␊ |
176 | */␊ |
177 | static uint64_t measure_aperf_frequency(void)␊ |
178 | {␊ |
179 | ␉uint64_t aperfStart;␊ |
180 | ␉uint64_t aperfEnd;␊ |
181 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
182 | ␉unsigned long pollCount;␊ |
183 | ␉uint64_t retval = 0;␊ |
184 | ␉int i;␊ |
185 | ␊ |
186 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
187 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
188 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
189 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
190 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
191 | ␉ * expire.␊ |
192 | ␉ */␊ |
193 | ␉for(i = 0; i < 10; ++i)␊ |
194 | ␉{␊ |
195 | ␉␉enable_PIT2();␊ |
196 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
197 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
198 | ␉␉pollCount = poll_PIT2_gate();␊ |
199 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
200 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
201 | ␉␉if (pollCount <= 1)␊ |
202 | ␉␉{␊ |
203 | ␉␉␉continue;␊ |
204 | ␉␉}␊ |
205 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
206 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
207 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
208 | ␉␉ */␊ |
209 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
210 | ␉␉{␊ |
211 | ␉␉␉continue;␊ |
212 | ␉␉}␊ |
213 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
214 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
215 | ␉␉{␊ |
216 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
217 | ␉␉}␊ |
218 | ␉}␊ |
219 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
220 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
221 | ␉ */␊ |
222 | ␊ |
223 | ␉if (aperfDelta > (1ULL<<32))␊ |
224 | ␉{␊ |
225 | ␉␉retval = 0;␊ |
226 | ␉}␊ |
227 | ␉else␊ |
228 | ␉{␊ |
229 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
230 | ␉}␊ |
231 | ␉disable_PIT2();␊ |
232 | ␉return retval;␊ |
233 | }␊ |
234 | ␊ |
235 | /*␊ |
236 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
237 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
238 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
239 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
240 | * - fsbFrequency = tscFrequency / multi␊ |
241 | * - cpuFrequency = fsbFrequency * multi␊ |
242 | */␊ |
243 | void scan_cpu(PlatformInfo_t *p)␊ |
244 | {␊ |
245 | ␉uint64_t␉tscFrequency = 0;␊ |
246 | ␉uint64_t␉fsbFrequency = 0;␊ |
247 | ␉uint64_t␉cpuFrequency = 0;␊ |
248 | ␉uint64_t␉msr = 0;␊ |
249 | ␉uint64_t␉flex_ratio = 0;␊ |
250 | ␉uint32_t␉max_ratio = 0;␊ |
251 | ␉uint32_t␉min_ratio = 0;␊ |
252 | ␉uint8_t␉␉bus_ratio_max = 0;␊ |
253 | ␉uint8_t␉␉currdiv = 0;␊ |
254 | ␉uint8_t␉␉currcoef = 0;␊ |
255 | ␉uint8_t␉␉maxdiv = 0;␊ |
256 | ␉uint8_t␉␉maxcoef = 0;␊ |
257 | ␉const char␉*newratio;␊ |
258 | ␉int␉␉len = 0;␊ |
259 | ␉int␉␉myfsb = 0;␊ |
260 | ␉uint8_t␉␉bus_ratio_min = 0;␊ |
261 | ␊ |
262 | ␉/* get cpuid values */␊ |
263 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
264 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
265 | ␊ |
266 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
267 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
268 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
269 | ␊ |
270 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
271 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊ |
272 | ␉{␊ |
273 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
274 | ␉}␊ |
275 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊ |
276 | ␉{␊ |
277 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
278 | ␉}␊ |
279 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
280 | ␉{␊ |
281 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
282 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
283 | ␉}␊ |
284 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
285 | ␉{␊ |
286 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
287 | ␉}␊ |
288 | ␊ |
289 | // #if DEBUG_CPU␊ |
290 | ␉{␊ |
291 | ␉␉int␉␉i;␊ |
292 | ␉␉DBG("CPUID Raw Values:\n");␊ |
293 | ␉␉for (i = 0; i < CPUID_MAX; i++) {␊ |
294 | ␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
295 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
296 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
297 | ␉␉}␊ |
298 | ␉}␊ |
299 | // #endif␊ |
300 | ␊ |
301 | /* http://www.flounder.com/cpuid_explorer2.htm␊ |
302 | EAX (Intel):␊ |
303 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
304 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
305 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
306 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
307 | ␊ |
308 | EAX (AMD):␊ |
309 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
310 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
311 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
312 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
313 | */␊ |
314 | ␉p->CPU.MCodeVersion␉= (uint32_t)(rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);␊ |
315 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
316 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
317 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF;␊ |
318 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF;␊ |
319 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF;␊ |
320 | ␉//p->CPU.Type␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
321 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
322 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
323 | ␊ |
324 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
325 | ␊ |
326 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
327 | ␉␉p->CPU.Family == 0x06 &&␊ |
328 | ␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊ |
329 | ␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
330 | ␉␉) {␊ |
331 | ␉␉/*␊ |
332 | ␉␉ * Find the number of enabled cores and threads␊ |
333 | ␉␉ * (which determines whether SMT/Hyperthreading is active).␊ |
334 | ␉␉ */␊ |
335 | ␉␉switch (p->CPU.Model)␊ |
336 | ␉␉{␊ |
337 | ␉␉␉case CPUID_MODEL_NEHALEM:␊ |
338 | ␉␉␉case CPUID_MODEL_FIELDS:␊ |
339 | ␉␉␉case CPUID_MODEL_DALES:␊ |
340 | ␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
341 | ␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
342 | ␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
343 | ␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
344 | ␉␉␉case CPUID_MODEL_HASWELL:␊ |
345 | ␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
346 | ␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
347 | ␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
348 | ␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
349 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
350 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊ |
351 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
352 | ␉␉␉␉break;␊ |
353 | ␊ |
354 | ␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
355 | ␉␉␉case CPUID_MODEL_WESTMERE:␊ |
356 | ␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
357 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
358 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊ |
359 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
360 | ␉␉␉␉break;␊ |
361 | ␊ |
362 | ␉␉␉default:␊ |
363 | ␉␉␉␉p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
364 | ␉␉␉␉p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊ |
365 | ␉␉␉␉//workaround for N270. I don't know why it detected wrong␊ |
366 | ␉␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) &&␊ |
367 | ␉␉␉␉␉(p->CPU.Stepping == 2)) {␊ |
368 | ␉␉␉␉p->CPU.NoCores = 1;␊ |
369 | ␉␉␉}␊ |
370 | ␉␉break;␊ |
371 | ␊ |
372 | ␉␉} // end switch␊ |
373 | ␊ |
374 | ␉} else if (p->CPU.Vendor == CPUID_VENDOR_AMD) {␊ |
375 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
376 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
377 | ␉} else {␊ |
378 | ␉␉// Use previous method for Cores and Threads␊ |
379 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
380 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
381 | ␉}␊ |
382 | ␊ |
383 | ␉/* get BrandString (if supported) */␊ |
384 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
385 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
386 | ␉{␊ |
387 | ␉␉uint32_t␉reg[4];␊ |
388 | ␉␉char␉␉str[128], *s;␊ |
389 | ␉␉/*␊ |
390 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
391 | ␉␉ * be NULL terminated.␊ |
392 | ␉␉ */␊ |
393 | ␉␉do_cpuid(0x80000002, reg);␊ |
394 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
395 | ␉␉do_cpuid(0x80000003, reg);␊ |
396 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
397 | ␉␉do_cpuid(0x80000004, reg);␊ |
398 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
399 | ␉␉for (s = str; *s != '\0'; s++)␊ |
400 | ␉␉{␊ |
401 | ␉␉␉if (*s != ' ')␊ |
402 | ␉␉␉{␊ |
403 | ␉␉␉␉break;␊ |
404 | ␉␉␉}␊ |
405 | ␉␉}␊ |
406 | ␊ |
407 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
408 | ␉␉{␊ |
409 | ␉␉␉/*␊ |
410 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
411 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
412 | ␉␉␉ */␊ |
413 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
414 | ␉␉}␊ |
415 | ␉}␊ |
416 | ␊ |
417 | ␉/* setup features */␊ |
418 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
419 | ␉{␊ |
420 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
421 | ␉}␊ |
422 | ␊ |
423 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
424 | ␉{␊ |
425 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
426 | ␉}␊ |
427 | ␊ |
428 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
429 | ␉{␊ |
430 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
431 | ␉}␊ |
432 | ␊ |
433 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
434 | ␉{␊ |
435 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
436 | ␉}␊ |
437 | ␊ |
438 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
439 | ␉{␊ |
440 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
441 | ␉}␊ |
442 | ␊ |
443 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
444 | ␉{␊ |
445 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
446 | ␉}␊ |
447 | ␊ |
448 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
449 | ␉{␊ |
450 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
451 | ␉}␊ |
452 | ␊ |
453 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
454 | ␉{␊ |
455 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
456 | ␉}␊ |
457 | ␊ |
458 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
459 | ␊ |
460 | ␉if (p->CPU.NoThreads > p->CPU.NoCores)␊ |
461 | ␉{␊ |
462 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
463 | ␉}␊ |
464 | ␊ |
465 | ␉tscFrequency = measure_tsc_frequency();␊ |
466 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
467 | ␉/* if usual method failed */␊ |
468 | ␉if ( tscFrequency < 1000 )␉//TEST␊ |
469 | ␉{␊ |
470 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
471 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
472 | ␉} else {␊ |
473 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
474 | ␉}␊ |
475 | ␊ |
476 | ␉fsbFrequency = 0;␊ |
477 | ␉cpuFrequency = 0;␊ |
478 | ␊ |
479 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊ |
480 | ␉␉int intelCPU = p->CPU.Model;␊ |
481 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␉{␊ |
482 | ␉␉␉/* Nehalem CPU model */␊ |
483 | ␉␉␉switch (p->CPU.Model) {␊ |
484 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
485 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
486 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
487 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
488 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
489 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
490 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
491 | /* --------------------------------------------------------- */␊ |
492 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
493 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
494 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
495 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
496 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
497 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
498 | ␊ |
499 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
500 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
501 | /* --------------------------------------------------------- */␊ |
502 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
503 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
504 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
505 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
506 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
507 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
508 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
509 | ␉␉␉␉␉{␊ |
510 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
511 | ␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
512 | ␉␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
513 | ␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
514 | ␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
515 | ␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
516 | ␉␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
517 | ␉␉␉␉␉␉ is inadvertently set to 0.␊ |
518 | ␉␉␉␉␉␉ */␊ |
519 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
520 | ␉␉␉␉␉␉{␊ |
521 | ␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
522 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
523 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
524 | ␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
525 | ␉␉␉␉␉␉}␊ |
526 | ␉␉␉␉␉␉else␊ |
527 | ␉␉␉␉␉␉{␊ |
528 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
529 | ␉␉␉␉␉␉␉{␊ |
530 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
531 | ␉␉␉␉␉␉␉}␊ |
532 | ␉␉␉␉␉␉}␊ |
533 | ␉␉␉␉␉}␊ |
534 | ␊ |
535 | ␉␉␉␉␉if (bus_ratio_max)␊ |
536 | ␉␉␉␉␉{␊ |
537 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
538 | ␉␉␉␉␉}␊ |
539 | ␊ |
540 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
541 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
542 | ␉␉␉␉␉{␊ |
543 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
544 | ␊ |
545 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
546 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
547 | ␉␉␉␉␉}␊ |
548 | ␉␉␉␉␉else␊ |
549 | ␉␉␉␉␉{␊ |
550 | ␉␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
551 | ␉␉␉␉␉}␊ |
552 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
553 | ␉␉␉␉␉{␊ |
554 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
555 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
556 | ␉␉␉␉␉␉if (len >= 3)␊ |
557 | ␉␉␉␉␉␉{␊ |
558 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
559 | ␉␉␉␉␉␉}␊ |
560 | ␊ |
561 | ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
562 | ␊ |
563 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
564 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
565 | ␉␉␉␉␉␉{␊ |
566 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
567 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
568 | ␉␉␉␉␉␉␉{␊ |
569 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
570 | ␉␉␉␉␉␉␉}␊ |
571 | ␉␉␉␉␉␉␉else␊ |
572 | ␉␉␉␉␉␉␉{␊ |
573 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
574 | ␉␉␉␉␉␉␉}␊ |
575 | ␉␉␉␉␉␉}␊ |
576 | ␉␉␉␉␉␉else␊ |
577 | ␉␉␉␉␉␉{␊ |
578 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
579 | ␉␉␉␉␉␉}␊ |
580 | ␉␉␉␉␉}␊ |
581 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
582 | ␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
583 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
584 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
585 | ␊ |
586 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
587 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
588 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
589 | ␊ |
590 | ␉␉␉␉break;␊ |
591 | ␊ |
592 | ␉␉␉default:␊ |
593 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
594 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
595 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
596 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
597 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
598 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
599 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
600 | ␊ |
601 | ␉␉␉␉// This will always be model >= 3␊ |
602 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
603 | ␉␉␉␉{␊ |
604 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
605 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
606 | ␉␉␉␉}␊ |
607 | ␉␉␉␉else␊ |
608 | ␉␉␉␉{␊ |
609 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
610 | ␉␉␉␉␉/* XXX */␊ |
611 | ␉␉␉␉␉maxcoef = currcoef;␊ |
612 | ␉␉␉␉}␊ |
613 | ␊ |
614 | ␉␉␉␉if (maxcoef)␊ |
615 | ␉␉␉␉{␊ |
616 | ␉␉␉␉␉if (maxdiv)␊ |
617 | ␉␉␉␉␉{␊ |
618 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
619 | ␉␉␉␉␉}␊ |
620 | ␉␉␉␉␉else␊ |
621 | ␉␉␉␉␉{␊ |
622 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
623 | ␉␉␉␉␉}␊ |
624 | ␊ |
625 | ␉␉␉␉␉if (currdiv)␊ |
626 | ␉␉␉␉␉{␊ |
627 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
628 | ␉␉␉␉␉}␊ |
629 | ␉␉␉␉␉else␊ |
630 | ␉␉␉␉␉{␊ |
631 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
632 | ␉␉␉␉␉}␊ |
633 | ␊ |
634 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
635 | ␉␉␉␉}␊ |
636 | ␉␉␉␉break;␊ |
637 | ␉␉␉}␊ |
638 | ␉␉}␊ |
639 | ␉␉/* Mobile CPU */␊ |
640 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
641 | ␉␉{␊ |
642 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
643 | ␉␉}␊ |
644 | ␉}␊ |
645 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
646 | ␉{␊ |
647 | ␉␉switch(p->CPU.ExtFamily)␊ |
648 | ␉␉{␊ |
649 | ␉␉␉case 0x00: /* K8 */␊ |
650 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
651 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
652 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
653 | ␉␉␉␉break;␊ |
654 | ␊ |
655 | ␉␉␉case 0x01: /* K10 */␊ |
656 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
657 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
658 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
659 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
660 | ␉␉␉␉{␊ |
661 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
662 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
663 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
664 | ␉␉␉␉}␊ |
665 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
666 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
667 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
668 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
669 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
670 | ␊ |
671 | ␉␉␉␉break;␊ |
672 | ␊ |
673 | ␉␉␉case 0x05: /* K14 */␊ |
674 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
675 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
676 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
677 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
678 | ␊ |
679 | ␉␉␉␉break;␊ |
680 | ␊ |
681 | ␉␉␉case 0x02: /* K11 */␊ |
682 | ␉␉␉␉// not implimented␊ |
683 | ␉␉␉␉break;␊ |
684 | ␉␉}␊ |
685 | ␊ |
686 | ␉␉if (maxcoef)␊ |
687 | ␉␉{␊ |
688 | ␉␉␉if (currdiv)␊ |
689 | ␉␉␉{␊ |
690 | ␉␉␉␉if (!currcoef)␊ |
691 | ␉␉␉␉{␊ |
692 | ␉␉␉␉␉currcoef = maxcoef;␊ |
693 | ␉␉␉␉}␊ |
694 | ␊ |
695 | ␉␉␉␉if (!cpuFrequency)␊ |
696 | ␉␉␉␉{␊ |
697 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
698 | ␉␉␉␉}␊ |
699 | ␉␉␉␉else␊ |
700 | ␉␉␉␉{␊ |
701 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
702 | ␉␉␉␉}␊ |
703 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
704 | ␉␉␉}␊ |
705 | ␉␉␉else␊ |
706 | ␉␉␉{␊ |
707 | ␉␉␉␉if (!cpuFrequency)␊ |
708 | ␉␉␉␉{␊ |
709 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
710 | ␉␉␉␉}␊ |
711 | ␉␉␉␉else␊ |
712 | ␉␉␉␉{␊ |
713 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
714 | ␉␉␉␉}␊ |
715 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
716 | ␉␉␉}␊ |
717 | ␉␉}␊ |
718 | ␉␉else if (currcoef)␊ |
719 | ␉␉{␊ |
720 | ␉␉␉if (currdiv)␊ |
721 | ␉␉␉{␊ |
722 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
723 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
724 | ␉␉␉}␊ |
725 | ␉␉␉else␊ |
726 | ␉␉␉{␊ |
727 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
728 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
729 | ␉␉␉}␊ |
730 | ␉␉}␊ |
731 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
732 | ␉}␊ |
733 | ␉␊ |
734 | #if 0␊ |
735 | ␉if (!fsbFrequency)␊ |
736 | ␉{␊ |
737 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
738 | ␉␉cpuFrequency = tscFrequency;␊ |
739 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
740 | ␉}␊ |
741 | ␊ |
742 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
743 | ␊ |
744 | #endif␊ |
745 | ␊ |
746 | ␉p->CPU.MaxCoef = maxcoef;␊ |
747 | ␉p->CPU.MaxDiv = maxdiv;␊ |
748 | ␉p->CPU.CurrCoef = currcoef;␊ |
749 | ␉p->CPU.CurrDiv = currdiv;␊ |
750 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
751 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
752 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
753 | ␊ |
754 | ␉// keep formatted with spaces instead of tabs␊ |
755 | ␉DBG("\n---------------------------------------------\n");␊ |
756 | ␉DBG("--------------- CPU INFO ---------------\n");␊ |
757 | ␉DBG("---------------------------------------------\n");␊ |
758 | ␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString); // Processor name (BIOS)␊ |
759 | ␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor); // Vendor ex: GenuineIntel␊ |
760 | ␉DBG("Family: 0x%x\n",␉␉p->CPU.Family); // Family ex: 6 (06h)␊ |
761 | ␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊ |
762 | ␉DBG("Signature: %x\n",␉␉p->CPU.Signature); // CPUID signature␊ |
763 | ␉/*switch (p->CPU.Type) {␊ |
764 | ␉␉case PT_OEM:␊ |
765 | ␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊ |
766 | ␉␉␉break;␊ |
767 | ␉␉case PT_OD:␊ |
768 | ␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊ |
769 | ␉␉␉break;␊ |
770 | ␉␉case PT_DUAL:␊ |
771 | ␉␉␉DBG("Processor type: Intel Dual Processor\n");␊ |
772 | ␉␉␉break;␊ |
773 | ␉␉case PT_RES:␊ |
774 | ␉␉␉DBG("Processor type: Intel Reserved\n");␊ |
775 | ␉␉␉break;␊ |
776 | ␉␉default:␊ |
777 | ␉␉␉break;␊ |
778 | ␉}*/␊ |
779 | ␉DBG("Model: 0x%x\n",␉␉p->CPU.Model); // Model ex: 37 (025h)␊ |
780 | ␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊ |
781 | ␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping); // Stepping ex: 5 (05h)␊ |
782 | ␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊ |
783 | ␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊ |
784 | ␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊ |
785 | ␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊ |
786 | ␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
787 | ␉DBG("FSBFreq: %dMHz\n",␉␉(p->CPU.FSBFrequency + 500000) / 1000000);␊ |
788 | ␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
789 | ␉DBG("Cores: %d\n",␉␉p->CPU.NoCores); // Cores␊ |
790 | ␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads); // Logical procesor␊ |
791 | ␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊ |
792 | ␉DBG("Microcode version: %d\n",␉␉p->CPU.MCodeVersion); // CPU microcode version␊ |
793 | ␉DBG("\n---------------------------------------------\n");␊ |
794 | #if DEBUG_CPU␊ |
795 | ␉pause();␊ |
796 | #endif␊ |
797 | }␊ |
798 | |