Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/state_generator.c

1/*␊
2 * Copyright 2008 mackerintel␊
3 *␊
4 * state_generator.h␊
5 * Chameleon␊
6 *␊
7 * Created by Mozodojo on 20/07/10.␊
8 * Copyright 2010 mozodojo. All rights reserved.␊
9 *␊
10 */␊
11␊
12#include "libsaio.h"␊
13#include "boot.h"␊
14#include "bootstruct.h"␊
15#include "acpi.h"␊
16#include "efi_tables.h"␊
17#include "fake_efi.h"␊
18#include "acpi_patcher.h"␊
19#include "platform.h"␊
20#include "cpu.h"␊
21#include "aml_generator.h"␊
22#include "state_generator.h"␊
23␊
24#ifndef DEBUG_STATE␊
25#define DEBUG_STATE 0␊
26#endif␊
27␊
28#if DEBUG_STATE==2␊
29#define DBG(x...) {printf(x); sleep(1);}␊
30#elif DEBUG_STATE==1␊
31#define DBG(x...) printf(x)␊
32#else␊
33#define DBG(x...) msglog(x)␊
34#endif␊
35␊
36extern uint8_t acpi_cpu_count;␊
37extern uint32_t acpi_cpu_p_blk;␊
38extern char* acpi_cpu_name[32];␊
39␊
40static char const pss_ssdt_header[] =␊
41{␊
42␉0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */␊
43␉0x01, 0x6A, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x00, /* ..PmRef. */␊
44␉0x43, 0x70, 0x75, 0x50, 0x6D, 0x00, 0x00, 0x00, /* CpuPm... */␊
45␉0x00, 0x30, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* .0..INTL */␊
46␉0x31, 0x03, 0x10, 0x20,␉␉␉␉/* 1.._␉␉*/␊
47};␊
48␊
49static char const cst_ssdt_header[] =␊
50{␊
51␉0x53, 0x53, 0x44, 0x54, 0xE7, 0x00, 0x00, 0x00, /* SSDT.... */␊
52␉0x01, 0x17, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x41, /* ..PmRefA */␊
53␉0x43, 0x70, 0x75, 0x43, 0x73, 0x74, 0x00, 0x00, /* CpuCst.. */␊
54␉0x00, 0x10, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* ....INTL */␊
55␉0x31, 0x03, 0x10, 0x20␉␉␉␉/* 1.._␉␉*/␊
56};␊
57␊
58char resource_template_register_fixedhw[] =␊
59{␊
60␉0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F,␊
61␉0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
62␉0x00, 0x00, 0x01, 0x79, 0x00␊
63};␊
64␊
65char resource_template_register_systemio[] =␊
66{␊
67␉0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x01,␊
68␉0x08, 0x00, 0x00, 0x15, 0x04, 0x00, 0x00, 0x00,␊
69␉0x00, 0x00, 0x00, 0x79, 0x00,␊
70};␊
71␊
72␊
73struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt* dsdt)␊
74{␊
75␊
76␉if (Platform.CPU.Vendor != 0x756E6547)␊
77␉{␊
78␉␉DBG("Not an Intel platform: P-States will not be generated !!!\n");␊
79␉␉return NULL;␊
80␉}␊
81␊
82␉if (!(Platform.CPU.Features & CPU_FEATURE_MSR))␊
83␉{␊
84␉␉DBG("Unsupported CPU: P-States will not be generated !!! No MSR support\n");␊
85␉␉return NULL;␊
86␉}␊
87␊
88␉if (acpi_cpu_count == 0)␊
89␉{␊
90␉␉get_acpi_cpu_names((void*)dsdt, dsdt->Length);␊
91␉}␊
92␊
93␉if (acpi_cpu_count > 0)␊
94␉{␊
95␉␉struct p_state initial, maximum, minimum, p_states[32];␊
96␉␉uint8_t p_states_count = 0;␊
97␊
98␉␉// Retrieving P-States, ported from code by superhai (c)␊
99␉␉switch (Platform.CPU.Family)␊
100␉␉{␊
101␉␉␉case 0x06:␊
102␉␉␉{␊
103␉␉␉␉switch (Platform.CPU.Model)␊
104␉␉␉␉{␊
105␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
106␉␉␉␉␉case CPUID_MODEL_YONAH:␉// Intel Mobile Core Solo, Duo␊
107␉␉␉␉␉case CPUID_MODEL_MEROM:␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
108␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
109␉␉␉␉␉case CPUID_MODEL_ATOM:␉// Intel Atom (45nm)␊
110␉␉␉␉␉{␊
111␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
112␊
113␉␉␉␉␉␉if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))␊
114␉␉␉␉␉␉{␊
115␉␉␉␉␉␉␉wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28))); ␊
116␉␉␉␉␉␉␉delay(1);␊
117␉␉␉␉␉␉␉cpu_dynamic_fsb = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);␊
118␉␉␉␉␉␉}␊
119␊
120␉␉␉␉␉␉bool cpu_noninteger_bus_ratio = (rdmsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46));␊
121␊
122␉␉␉␉␉␉initial.Control = rdmsr64(MSR_IA32_PERF_STATUS);␊
123␊
124␉␉␉␉␉␉maximum.Control = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio);␊
125␉␉␉␉␉␉maximum.CID = ((maximum.FID & 0x1F) << 1) | cpu_noninteger_bus_ratio;␊
126␊
127␉␉␉␉␉␉minimum.FID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 24) & 0x1F) | (0x80 * cpu_dynamic_fsb);␊
128␉␉␉␉␉␉minimum.VID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 48) & 0x3F);␊
129␊
130␉␉␉␉␉␉if (minimum.FID == 0)␊
131␉␉␉␉␉␉{␊
132␉␉␉␉␉␉␉uint64_t msr;␊
133␉␉␉␉␉␉␉uint8_t i;␊
134␉␉␉␉␉␉␉// Probe for lowest fid␊
135␉␉␉␉␉␉␉for (i = maximum.FID; i >= 0x6; i--)␊
136␉␉␉␉␉␉␉{␊
137␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
138␉␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (i << 8) | minimum.VID);␊
139␉␉␉␉␉␉␉␉intel_waitforsts();␊
140␉␉␉␉␉␉␉␉minimum.FID = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0x1F; ␊
141␉␉␉␉␉␉␉␉delay(1);␊
142␉␉␉␉␉␉␉}␊
143␊
144␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
145␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);␊
146␉␉␉␉␉␉␉intel_waitforsts();␊
147␉␉␉␉␉␉}␊
148␊
149␉␉␉␉␉␉if (minimum.VID == maximum.VID) ␊
150␉␉␉␉␉␉{␊
151␉␉␉␉␉␉␉uint64_t msr;␊
152␉␉␉␉␉␉␉uint8_t i;␊
153␉␉␉␉␉␉␉// Probe for lowest vid␊
154␉␉␉␉␉␉␉for (i = maximum.VID; i > 0xA; i--) ␊
155␉␉␉␉␉␉␉{␊
156␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
157␉␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (minimum.FID << 8) | i);␊
158␉␉␉␉␉␉␉␉intel_waitforsts();␊
159␉␉␉␉␉␉␉␉minimum.VID = rdmsr64(MSR_IA32_PERF_STATUS) & 0x3F; ␊
160␉␉␉␉␉␉␉␉delay(1);␊
161␉␉␉␉␉␉␉}␊
162␊
163␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_CONTROL);␊
164␉␉␉␉␉␉␉wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);␊
165␉␉␉␉␉␉␉intel_waitforsts();␊
166␉␉␉␉␉␉}␊
167␊
168␉␉␉␉␉␉minimum.CID = ((minimum.FID & 0x1F) << 1) >> cpu_dynamic_fsb;␊
169␊
170␉␉␉␉␉␉// Sanity check␊
171␉␉␉␉␉␉if (maximum.CID < minimum.CID)␊
172␉␉␉␉␉␉{␊
173␉␉␉␉␉␉␉DBG("P-States: Insane FID values!");␊
174␉␉␉␉␉␉␉p_states_count = 0;␊
175␉␉␉␉␉␉}␊
176␉␉␉␉␉␉else␊
177␉␉␉␉␉␉{␊
178␉␉␉␉␉␉␉uint8_t vidstep;␊
179␉␉␉␉␉␉␉uint8_t u, invalid = 0;␊
180␉␉␉␉␉␉␉// Finalize P-States␊
181␉␉␉␉␉␉␉// Find how many P-States machine supports␊
182␉␉␉␉␉␉␉p_states_count = (uint8_t)(maximum.CID - minimum.CID + 1);␊
183␊
184␉␉␉␉␉␉␉if (p_states_count > 32)␊
185␉␉␉␉␉␉␉{␊
186␉␉␉␉␉␉␉␉p_states_count = 32;␊
187␉␉␉␉␉␉␉}␊
188␊
189␉␉␉␉␉␉␉vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);␊
190␊
191␉␉␉␉␉␉␉for (u = 0; u < p_states_count; u++)␊
192␉␉␉␉␉␉␉{␊
193␉␉␉␉␉␉␉␉uint8_t i = u - invalid;␊
194␊
195␉␉␉␉␉␉␉␉p_states[i].CID = maximum.CID - u;␊
196␉␉␉␉␉␉␉␉p_states[i].FID = (uint8_t)(p_states[i].CID >> 1);␊
197␊
198␉␉␉␉␉␉␉␉if (p_states[i].FID < 0x6)␊
199␉␉␉␉␉␉␉␉{␊
200␉␉␉␉␉␉␉␉␉if (cpu_dynamic_fsb)␊
201␉␉␉␉␉␉␉␉␉{␊
202␉␉␉␉␉␉␉␉␉␉p_states[i].FID = (p_states[i].FID << 1) | 0x80;␊
203␉␉␉␉␉␉␉␉␉}␊
204␉␉␉␉␉␉␉␉}␊
205␉␉␉␉␉␉␉␉else if (cpu_noninteger_bus_ratio)␊
206␉␉␉␉␉␉␉␉{␊
207␉␉␉␉␉␉␉␉␉p_states[i].FID = p_states[i].FID | (0x40 * (p_states[i].CID & 0x1));␊
208␉␉␉␉␉␉␉␉}␊
209␊
210␉␉␉␉␉␉␉␉if (i && p_states[i].FID == p_states[i-1].FID)␊
211␉␉␉␉␉␉␉␉{␊
212␉␉␉␉␉␉␉␉␉invalid++;␊
213␉␉␉␉␉␉␉␉}␊
214␉␉␉␉␉␉␉␉p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;␊
215␉␉␉␉␉␉␉␉uint32_t multiplier = p_states[i].FID & 0x1f;␉␉// = 0x08␊
216␉␉␉␉␉␉␉␉bool half = p_states[i].FID & 0x40;␉␉␉␉␉// = 0x01␊
217␉␉␉␉␉␉␉␉bool dfsb = p_states[i].FID & 0x80;␉␉␉␉␉// = 0x00␊
218␉␉␉␉␉␉␉␉uint32_t fsb = (uint32_t)(Platform.CPU.FSBFrequency / 1000000); // = 400␊
219␉␉␉␉␉␉␉␉uint32_t halffsb = (fsb + 1) >> 1;␉␉␉␉␉// = 200␊
220␉␉␉␉␉␉␉␉uint32_t frequency = (multiplier * fsb);␉␉␉// = 3200␊
221␊
222␉␉␉␉␉␉␉␉p_states[i].Frequency = (uint32_t)(frequency + (half * halffsb)) >> dfsb;␉// = 3200 + 200 = 3400␊
223␉␉␉␉␉␉␉}␊
224␊
225␉␉␉␉␉␉␉p_states_count -= invalid;␊
226␉␉␉␉␉␉}␊
227␊
228␉␉␉␉␉␉break;␊
229␉␉␉␉␉}␊
230␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
231␉␉␉␉␉case CPUID_MODEL_DALES:␊
232␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
233␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
234␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
235␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
236␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
237␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
238␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
239␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
240␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉//␊
241␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON: //␊
242␉␉␉␉␉//case CPUID_MODEL_HASWELL_H:␉//␊
243␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉//␊
244␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉//␊
245␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉//␊
246␊
247␉␉␉␉␉{␊
248␉␉␉␉␉if ((Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_JAKETOWN) ||␊
249␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_HASWELL) ||␊
250␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPUID_MODEL_HASWELL_SVR) ||␊
251␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPUID_MODEL_CRYSTALWELL))␊
252␉␉␉␉␉{␊
253␉␉␉␉␉␉maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
254␉␉␉␉␉}␊
255␉␉␉␉␉else␊
256␉␉␉␉␉{␊
257␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;␊
258␉␉␉␉␉}␊
259␊
260␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
261␊
262␉␉␉␉␉DBG("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␊
263␊
264␉␉␉␉␉// Sanity check␊
265␉␉␉␉␉if (maximum.Control < minimum.Control)␊
266␉␉␉␉␉{␊
267␉␉␉␉␉␉DBG("Insane control values!");␊
268␉␉␉␉␉␉p_states_count = 0;␊
269␉␉␉␉␉}␊
270␉␉␉␉␉else␊
271␉␉␉␉␉{␊
272␉␉␉␉␉␉uint8_t i;␊
273␉␉␉␉␉␉p_states_count = 0;␊
274␊
275␉␉␉␉␉␉for (i = maximum.Control; i >= minimum.Control; i--)␊
276␉␉␉␉␉␉{␊
277␉␉␉␉␉␉␉p_states[p_states_count].Control = i;␊
278␉␉␉␉␉␉␉p_states[p_states_count].CID = p_states[p_states_count].Control << 1;␊
279␉␉␉␉␉␉␉p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;␊
280␉␉␉␉␉␉␉p_states_count++;␊
281␉␉␉␉␉␉}␊
282␉␉␉␉␉}␊
283␊
284␉␉␉␉␉break;␊
285␉␉␉␉}␊
286␉␉␉␉default:␊
287␉␉␉␉␉DBG("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);␊
288␉␉␉␉␉break;␊
289␉␉␉}␊
290␉␉}␊
291␉}␊
292␊
293␉// Generating SSDT␊
294␉if (p_states_count > 0)␊
295␉{␊
296␊
297␉␉int i;␊
298␊
299␉␉AML_CHUNK* root = aml_create_node(NULL);␊
300␉␉aml_add_buffer(root, pss_ssdt_header, sizeof(pss_ssdt_header)); // SSDT header␊
301␊
302␉␉AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");␊
303␉␉AML_CHUNK* name = aml_add_name(scop, "PSS_");␊
304␉␉AML_CHUNK* pack = aml_add_package(name);␊
305␊
306␉␉for (i = 0; i < p_states_count; i++)␊
307␉␉{␊
308␉␉␉AML_CHUNK* pstt = aml_add_package(pack);␊
309␊
310␉␉␉aml_add_dword(pstt, p_states[i].Frequency);␊
311␉␉␉aml_add_dword(pstt, 0x00000000); // Power␊
312␉␉␉aml_add_dword(pstt, 0x0000000A); // Latency␊
313␉␉␉aml_add_dword(pstt, 0x0000000A); // Latency␊
314␉␉␉aml_add_dword(pstt, p_states[i].Control);␊
315␉␉␉aml_add_dword(pstt, i+1); // Status␊
316␉␉}␊
317␊
318␉␉␉// Add aliaces␊
319␉␉␉for (i = 0; i < acpi_cpu_count; i++)␊
320␉␉␉{␊
321␉␉␉␉char name[9];␊
322␉␉␉␉sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);␊
323␊
324␉␉␉␉scop = aml_add_scope(root, name);␊
325␉␉␉␉aml_add_alias(scop, "PSS_", "_PSS");␊
326␉␉␉}␊
327␊
328␉␉␉aml_calculate_size(root);␊
329␊
330␉␉␉struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);␊
331␊
332␉␉␉aml_write_node(root, (void*)ssdt, 0);␊
333␊
334␉␉␉ssdt->Length = root->Size;␊
335␉␉␉ssdt->Checksum = 0;␊
336␉␉␉ssdt->Checksum = (uint8_t)(256 - checksum8(ssdt, ssdt->Length));␊
337␊
338␉␉␉aml_destroy_node(root);␊
339␊
340␉␉␉//dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length);␊
341␊
342␉␉␉DBG("SSDT with CPU P-States generated successfully\n");␊
343␊
344␉␉␉return ssdt;␊
345␉␉}␊
346␉}␊
347␉else␊
348␉{␊
349␉␉DBG("ACPI CPUs not found: P-States not generated !!!\n");␊
350␉}␊
351␊
352␉return NULL;␊
353}␊
354␊
355struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt* fadt)␊
356{␊
357␊
358␉if (Platform.CPU.Vendor != 0x756E6547)␊
359␉{␊
360␉␉DBG("Not an Intel platform: C-States will not be generated !!!\n");␊
361␉␉return NULL;␊
362␉}␊
363␊
364␉if (fadt == NULL)␊
365␉{␊
366␉␉DBG("FACP not exists: C-States will not be generated !!!\n");␊
367␉␉return NULL;␊
368␉}␊
369␊
370␉struct acpi_2_dsdt* dsdt = (void*)fadt->DSDT;␊
371␊
372␉if (dsdt == NULL)␊
373␉{␊
374␉␉DBG("DSDT not found: C-States will not be generated !!!\n");␊
375␉␉return NULL;␊
376␉}␊
377␊
378␉if (acpi_cpu_count == 0)␊
379␉␉get_acpi_cpu_names((void*)dsdt, dsdt->Length);␊
380␊
381␉if (acpi_cpu_count > 0)␊
382␉{␊
383␉␉bool c2_enabled = false;␊
384␉␉bool c3_enabled = false;␊
385␉␉bool c4_enabled = false;␊
386␉␉bool cst_using_systemio = false;␊
387␊
388␉␉getBoolForKey(kEnableC2State, &c2_enabled, &bootInfo->chameleonConfig);␊
389␉␉getBoolForKey(kEnableC3State, &c3_enabled, &bootInfo->chameleonConfig);␊
390␉␉getBoolForKey(kEnableC4State, &c4_enabled, &bootInfo->chameleonConfig);␊
391␉␉getBoolForKey(kCSTUsingSystemIO, &cst_using_systemio, &bootInfo->chameleonConfig);␊
392␊
393␉␉c2_enabled = c2_enabled | (fadt->C2_Latency < 100);␊
394␉␉c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);␊
395␊
396␉␉unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + (c3_enabled ? 1 : 0);␊
397␊
398␉␉AML_CHUNK* root = aml_create_node(NULL);␊
399␉␉aml_add_buffer(root, cst_ssdt_header, sizeof(cst_ssdt_header)); // SSDT header␊
400␉␉AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");␊
401␉␉AML_CHUNK* name = aml_add_name(scop, "CST_");␊
402␉␉AML_CHUNK* pack = aml_add_package(name);␊
403␉␉aml_add_byte(pack, cstates_count);␊
404␊
405␉␉AML_CHUNK* tmpl = aml_add_package(pack);␊
406␉␉if (cst_using_systemio)␊
407␉␉{␊
408␉␉␉// C1␊
409␉␉␉resource_template_register_fixedhw[8] = 0x00;␊
410␉␉␉resource_template_register_fixedhw[9] = 0x00;␊
411␉␉␉resource_template_register_fixedhw[18] = 0x00;␊
412␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
413␉␉␉aml_add_byte(tmpl, 0x01);␉␉// C1␊
414␉␉␉aml_add_word(tmpl, 0x0001);␉␉// Latency␊
415␉␉␉aml_add_dword(tmpl, 0x000003e8);␉// Power␊
416␊
417␉␉␉uint8_t p_blk_lo, p_blk_hi;␊
418␊
419␉␉␉if (c2_enabled) // C2␊
420␉␉␉{␊
421␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 4;␊
422␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 4) >> 8;␊
423␊
424␉␉␉␉tmpl = aml_add_package(pack);␊
425␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C2␊
426␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C2␊
427␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
428␉␉␉␉aml_add_byte(tmpl, 0x02);␉␉// C2␊
429␉␉␉␉aml_add_word(tmpl, 0x0040);␉␉// Latency␊
430␉␉␉␉aml_add_dword(tmpl, 0x000001f4);␉// Power␊
431␉␉␉}␊
432␊
433␉␉␉if (c4_enabled) // C4␊
434␉␉␉{␊
435␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 5;␊
436␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
437␊
438␉␉␉␉tmpl = aml_add_package(pack);␊
439␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C4␊
440␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C4␊
441␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
442␉␉␉␉aml_add_byte(tmpl, 0x04);␉␉// C4␊
443␉␉␉␉aml_add_word(tmpl, 0x0080);␉␉// Latency␊
444␉␉␉␉aml_add_dword(tmpl, 0x000000C8);␉// Power␊
445␉␉␉}␊
446␉␉␉else if (c3_enabled) // C3␊
447␉␉␉{␊
448␉␉␉␉p_blk_lo = acpi_cpu_p_blk + 5;␊
449␉␉␉␉p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;␊
450␊
451␉␉␉␉tmpl = aml_add_package(pack);␊
452␉␉␉␉resource_template_register_systemio[11] = p_blk_lo; // C3␊
453␉␉␉␉resource_template_register_systemio[12] = p_blk_hi; // C3␊
454␉␉␉␉aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));␊
455␉␉␉␉aml_add_byte(tmpl, 0x03);␉␉// C3␊
456␉␉␉␉aml_add_word(tmpl, 0x0060);␉␉// Latency␊
457␉␉␉␉aml_add_dword(tmpl, 0x0000015e);␉// Power␊
458␉␉␉}␊
459␉␉}␊
460␉␉else␊
461␉␉{␊
462␉␉␉// C1␊
463␉␉␉resource_template_register_fixedhw[8] = 0x01;␊
464␉␉␉resource_template_register_fixedhw[9] = 0x02;␊
465␉␉␉resource_template_register_fixedhw[18] = 0x01;␊
466␊
467␉␉␉resource_template_register_fixedhw[11] = 0x00; // C1␊
468␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
469␉␉␉aml_add_byte(tmpl, 0x01);␉␉// C1␊
470␉␉␉aml_add_word(tmpl, 0x0001);␉␉// Latency␊
471␉␉␉aml_add_dword(tmpl, 0x000003e8);␉// Power␊
472␊
473␉␉␉resource_template_register_fixedhw[18] = 0x03;␊
474␊
475␉␉␉if (c2_enabled) // C2␊
476␉␉␉{␊
477␉␉␉␉tmpl = aml_add_package(pack);␊
478␉␉␉␉resource_template_register_fixedhw[11] = 0x10; // C2␊
479␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
480␉␉␉␉aml_add_byte(tmpl, 0x02);␉␉// C2␊
481␉␉␉␉aml_add_word(tmpl, 0x0040);␉␉// Latency␊
482␉␉␉␉aml_add_dword(tmpl, 0x000001f4);␉// Power␊
483␉␉␉}␊
484␊
485␉␉␉if (c4_enabled) // C4␊
486␉␉␉{␊
487␉␉␉␉tmpl = aml_add_package(pack);␊
488␉␉␉␉resource_template_register_fixedhw[11] = 0x30; // C4␊
489␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
490␉␉␉␉aml_add_byte(tmpl, 0x04);␉␉// C4␊
491␉␉␉␉aml_add_word(tmpl, 0x0080);␉␉// Latency␊
492␉␉␉␉aml_add_dword(tmpl, 0x000000C8);␉// Power␊
493␉␉␉}␊
494␉␉␉else if (c3_enabled)␊
495␉␉␉{␊
496␉␉␉␉tmpl = aml_add_package(pack);␊
497␉␉␉␉resource_template_register_fixedhw[11] = 0x20; // C3␊
498␉␉␉␉aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));␊
499␉␉␉␉aml_add_byte(tmpl, 0x03);␉␉// C3␊
500␉␉␉␉aml_add_word(tmpl, 0x0060);␉␉// Latency␊
501␉␉␉␉aml_add_dword(tmpl, 0x0000015e);␉// Power␊
502␉␉␉}␊
503␉␉}␊
504␊
505␉␉// Aliaces␊
506␉␉int i;␊
507␉␉for (i = 0; i < acpi_cpu_count; i++)␊
508␉␉{␊
509␉␉␉char name[9];␊
510␉␉␉sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);␊
511␊
512␉␉␉scop = aml_add_scope(root, name);␊
513␉␉␉aml_add_alias(scop, "CST_", "_CST");␊
514␉␉}␊
515␊
516␉␉aml_calculate_size(root);␊
517␊
518␉␉struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);␊
519␊
520␉␉aml_write_node(root, (void*)ssdt, 0);␊
521␊
522␉␉ssdt->Length = root->Size;␊
523␉␉ssdt->Checksum = 0;␊
524␉␉ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);␊
525␊
526␉␉aml_destroy_node(root);␊
527␊
528␉␉// dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length);␊
529␊
530␉␉DBG("SSDT with CPU C-States generated successfully\n");␊
531␊
532␉␉return ssdt;␊
533␉}␊
534␉else␊
535␉{␊
536␉␉DBG("ACPI CPUs not found: C-States not generated !!!\n");␊
537␉}␊
538␊
539␉return NULL;␊
540}␊
541

Archive Download this file

Revision: 2484