1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
36 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
37 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
38 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
39 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
40 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
42 | ␊ |
43 | ␉␉␉␉␉␉value->word = 0;␊ |
44 | ␉␉␉␉␉␉break;␊ |
45 | ␉␉␉␉␉default:␊ |
46 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
47 | ␉␉␉␉}␊ |
48 | ␉␉␉}␊ |
49 | ␉␉␉␉break;␊ |
50 | ␊ |
51 | ␉␉␉default:␊ |
52 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
53 | ␉␉}␊ |
54 | ␉}␊ |
55 | ␉else␊ |
56 | ␉{␊ |
57 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
58 | ␉}␊ |
59 | ␊ |
60 | ␉return true;␊ |
61 | }␊ |
62 | ␊ |
63 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
64 | {␊ |
65 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
66 | ␉return true;␊ |
67 | }␊ |
68 | ␊ |
69 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
70 | {␊ |
71 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
72 | ␉{␊ |
73 | ␉␉switch (Platform.CPU.Family)␊ |
74 | ␉␉{␊ |
75 | ␉␉␉case 0x06:␊ |
76 | ␉␉␉{␊ |
77 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
78 | ␉␉␉␉{␊ |
79 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
80 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
81 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
82 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
83 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
85 | ␉␉␉␉␉␉return false;␊ |
86 | ␊ |
87 | ␉␉␉␉␉case 0x19:␊ |
88 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
89 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
90 | ␉␉␉␉␉case CPUID_MODEL_DALES:␊ |
91 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
92 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
93 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
94 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
95 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
96 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
97 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
98 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
99 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
100 | ␉␉␉␉␉{␊ |
101 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
102 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
103 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
104 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
105 | ␉␉␉␉␉␉unsigned int i;␊ |
106 | ␉␉␉␉␉␉␊ |
107 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
108 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
109 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
110 | ␉␉␉␉␉␉{␊ |
111 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
112 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
113 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
114 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
115 | ␉␉␉␉␉␉␉␊ |
116 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
117 | ␉␉␉␉␉␉␉{␊ |
118 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
119 | ␉␉␉␉␉␉␉}␊ |
120 | ␉␉␉␉␉␉}␊ |
121 | ␊ |
122 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
123 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
124 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
125 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
126 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
127 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
128 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
129 | ␉␉␉␉␉␉{␊ |
130 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
131 | ␉␉␉␉␉␉}␊ |
132 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
133 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
134 | ␉␉␉␉␉␉return true;␊ |
135 | ␉␉␉␉␉}␊ |
136 | ␉␉␉␉␉default:␊ |
137 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
138 | ␉␉␉␉}␊ |
139 | ␉␉␉}␊ |
140 | ␉␉␉default:␊ |
141 | ␉␉␉␉break;␊ |
142 | ␉␉}␊ |
143 | ␉}␊ |
144 | ␉return false;␊ |
145 | }␊ |
146 | ␊ |
147 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
148 | {␊ |
149 | ␉if (Platform.CPU.NoCores >= 4)␊ |
150 | ␉{␊ |
151 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
152 | ␉}␊ |
153 | ␉else if (Platform.CPU.NoCores == 1)␊ |
154 | ␉{␊ |
155 | ␉␉return 0x201;␉// 513 - Core Duo␊ |
156 | ␉};␊ |
157 | ␉␊ |
158 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
159 | }␊ |
160 | ␊ |
161 | bool getSMBOemProcessorType(returnType *value)␊ |
162 | {␊ |
163 | ␉static bool done = false;␊ |
164 | ␊ |
165 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
166 | ␊ |
167 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
168 | ␉{␊ |
169 | ␉␉if (!done)␊ |
170 | ␉␉{␊ |
171 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
172 | ␉␉␉done = true;␊ |
173 | ␉␉}␊ |
174 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊ |
175 | ␉␉switch (Platform.CPU.Family)␊ |
176 | ␉␉{␊ |
177 | ␉␉␉case 0x0F:␊ |
178 | ␉␉␉case 0x06:␊ |
179 | ␉␉␉{␊ |
180 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
181 | ␉␉␉␉{␊ |
182 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
183 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
184 | ␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊ |
185 | ␉␉␉␉␉case CPUID_MODEL_NOCONA:␊ |
186 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
187 | ␉␉␉␉␉␉{␊ |
188 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
189 | ␉␉␉␉␉␉}␊ |
190 | ␉␉␉␉␉␉return true;␊ |
191 | ␊ |
192 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
193 | ␉␉␉␉␉case CPUID_MODEL_CELERON:␊ |
194 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
195 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
199 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
200 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
201 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
202 | ␉␉␉␉␉␉{␊ |
203 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
204 | ␉␉␉␉␉␉␉return true;␊ |
205 | ␉␉␉␉␉␉}␊ |
206 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
207 | ␉␉␉␉␉␉{␊ |
208 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊ |
209 | ␉␉␉␉␉␉}␊ |
210 | ␉␉␉␉␉␉else␊ |
211 | ␉␉␉␉␉␉{␊ |
212 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
213 | ␉␉␉␉␉␉}␊ |
214 | ␉␉␉␉␉␉return true;␊ |
215 | ␊ |
216 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
217 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
218 | ␉␉␉␉␉␉return true;␊ |
219 | ␊ |
220 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
221 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
222 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
223 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
224 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
225 | ␉␉␉␉␉␉{␊ |
226 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
227 | ␉␉␉␉␉␉␉return true;␊ |
228 | ␉␉␉␉␉␉}␊ |
229 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
230 | ␉␉␉␉␉␉{␊ |
231 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
232 | ␉␉␉␉␉␉␉return true;␊ |
233 | ␉␉␉␉␉␉}␊ |
234 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
235 | ␉␉␉␉␉␉{␊ |
236 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
237 | ␉␉␉␉␉␉␉return true;␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
240 | ␉␉␉␉␉␉{␊ |
241 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
242 | ␉␉␉␉␉␉␉return true;␊ |
243 | ␉␉␉␉␉␉}␊ |
244 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
245 | ␉␉␉␉␉␉{␊ |
246 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊ |
247 | ␉␉␉␉␉␉}␊ |
248 | ␉␉␉␉␉␉return true;␊ |
249 | ␊ |
250 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
251 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
252 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
253 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
254 | ␉␉␉␉␉␉{␊ |
255 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
256 | ␉␉␉␉␉␉␉return true;␊ |
257 | ␉␉␉␉␉␉}␊ |
258 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
259 | ␉␉␉␉␉␉{␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
264 | ␉␉␉␉␉␉{␊ |
265 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
266 | ␉␉␉␉␉␉␉return true;␊ |
267 | ␉␉␉␉␉␉}␊ |
268 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
269 | ␉␉␉␉␉␉{␊ |
270 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
271 | ␉␉␉␉␉␉␉return true;␊ |
272 | ␉␉␉␉␉␉}␊ |
273 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
274 | ␉␉␉␉␉␉{␊ |
275 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊ |
276 | ␉␉␉␉␉␉}␊ |
277 | ␉␉␉␉␉␉return true;␊ |
278 | ␊ |
279 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
280 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
281 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
282 | ␉␉␉␉␉␉{␊ |
283 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
284 | ␉␉␉␉␉␉␉return true;␊ |
285 | ␉␉␉␉␉␉}␊ |
286 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
287 | ␉␉␉␉␉␉{␊ |
288 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
289 | ␉␉␉␉␉␉␉return true;␊ |
290 | ␉␉␉␉␉␉}␊ |
291 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
292 | ␉␉␉␉␉␉{␊ |
293 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
294 | ␉␉␉␉␉␉␉return true;␊ |
295 | ␉␉␉␉␉␉}␊ |
296 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
297 | ␉␉␉␉␉␉{␊ |
298 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
299 | ␉␉␉␉␉␉␉return true;␊ |
300 | ␉␉␉␉␉␉}␊ |
301 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
302 | ␉␉␉␉␉␉{␊ |
303 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊ |
304 | ␉␉␉␉␉␉}␊ |
305 | ␉␉␉␉␉␉return true;␊ |
306 | ␊ |
307 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
308 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
309 | ␉␉␉␉␉␉{␊ |
310 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
311 | ␉␉␉␉␉␉␉return true;␊ |
312 | ␉␉␉␉␉␉}␊ |
313 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
314 | ␉␉␉␉␉␉{␊ |
315 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
316 | ␉␉␉␉␉␉␉return true;␊ |
317 | ␉␉␉␉␉␉}␊ |
318 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
319 | ␉␉␉␉␉␉{␊ |
320 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
321 | ␉␉␉␉␉␉␉return true;␊ |
322 | ␉␉␉␉␉␉}␊ |
323 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
324 | ␉␉␉␉␉␉{␊ |
325 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
326 | ␉␉␉␉␉␉␉return true;␊ |
327 | ␉␉␉␉␉␉}␊ |
328 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
329 | ␉␉␉␉␉␉{␊ |
330 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊ |
331 | ␉␉␉␉␉␉}␊ |
332 | ␉␉␉␉␉␉return true;␊ |
333 | ␊ |
334 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
335 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
336 | ␉␉␉␉␉␉return true;␊ |
337 | ␊ |
338 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊ |
339 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
340 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
341 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
342 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
343 | ␉␉␉␉␉␉{␊ |
344 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
345 | ␉␉␉␉␉␉␉return true;␊ |
346 | ␉␉␉␉␉␉}␊ |
347 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
348 | ␉␉␉␉␉␉{␊ |
349 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
350 | ␉␉␉␉␉␉␉return true;␊ |
351 | ␉␉␉␉␉␉}␊ |
352 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
353 | ␉␉␉␉␉␉{␊ |
354 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
355 | ␉␉␉␉␉␉␉return true;␊ |
356 | ␉␉␉␉␉␉}␊ |
357 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
358 | ␉␉␉␉␉␉{␊ |
359 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
360 | ␉␉␉␉␉␉␉return true;␊ |
361 | ␉␉␉␉␉␉}␊ |
362 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
363 | ␉␉␉␉␉␉{␊ |
364 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊ |
365 | ␉␉␉␉␉␉}␊ |
366 | ␉␉␉␉␉␉return true;␊ |
367 | ␊ |
368 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
369 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
370 | ␉␉␉␉␉␉return true;␊ |
371 | ␊ |
372 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
373 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
374 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
375 | ␉␉␉␉␉␉return true;␊ |
376 | ␉␉␉␉␉default:␊ |
377 | ␉␉␉␉␉␉break; // Unsupported CPU type␊ |
378 | ␉␉␉␉}␊ |
379 | ␉␉␉}␊ |
380 | ␉␉␉default:␊ |
381 | ␉␉␉␉break;␊ |
382 | ␉␉}␊ |
383 | ␉}␊ |
384 | ␉␊ |
385 | ␉return false;␊ |
386 | }␊ |
387 | ␊ |
388 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
389 | {␊ |
390 | ␉static int idx = -1;␊ |
391 | ␉int␉map;␊ |
392 | ␊ |
393 | ␉if (!bootInfo->memDetect)␊ |
394 | ␉{␊ |
395 | ␉␉return false;␊ |
396 | ␉}␊ |
397 | ␊ |
398 | ␉idx++;␊ |
399 | ␉if (idx < MAX_RAM_SLOTS)␊ |
400 | ␉{␊ |
401 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
402 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
403 | ␉␉{␊ |
404 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
405 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
406 | ␉␉␉return true;␊ |
407 | ␉␉}␊ |
408 | ␉}␊ |
409 | ␊ |
410 | ␉value->byte = 2; // means Unknown␊ |
411 | ␉return true;␊ |
412 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
413 | //␉return true;␊ |
414 | }␊ |
415 | ␊ |
416 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
417 | {␊ |
418 | ␉value->word = 0xFFFF;␊ |
419 | ␉return true;␊ |
420 | }␊ |
421 | ␊ |
422 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
423 | {␊ |
424 | ␉static int idx = -1;␊ |
425 | ␉int␉map;␊ |
426 | ␊ |
427 | ␉if (!bootInfo->memDetect)␊ |
428 | ␉{␊ |
429 | ␉␉return false;␊ |
430 | ␉}␊ |
431 | ␊ |
432 | ␉idx++;␊ |
433 | ␉if (idx < MAX_RAM_SLOTS)␊ |
434 | ␉{␊ |
435 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
436 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
437 | ␉␉{␊ |
438 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
439 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
440 | ␉␉␉return true;␊ |
441 | ␉␉}␊ |
442 | ␉}␊ |
443 | ␊ |
444 | ␉value->dword = 0; // means Unknown␊ |
445 | ␉return true;␊ |
446 | //␉value->dword = 800;␊ |
447 | //␉return true;␊ |
448 | }␊ |
449 | ␊ |
450 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
451 | {␊ |
452 | ␉static int idx = -1;␊ |
453 | ␉int␉map;␊ |
454 | ␊ |
455 | ␉if (!bootInfo->memDetect)␊ |
456 | ␉{␊ |
457 | ␉␉return false;␊ |
458 | ␉}␊ |
459 | ␊ |
460 | ␉idx++;␊ |
461 | ␉if (idx < MAX_RAM_SLOTS)␊ |
462 | ␉{␊ |
463 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
464 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
465 | ␉␉{␊ |
466 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
467 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
468 | ␉␉␉return true;␊ |
469 | ␉␉}␊ |
470 | ␉}␊ |
471 | ␊ |
472 | ␉value->string = NOT_AVAILABLE;␊ |
473 | ␉return true;␊ |
474 | }␊ |
475 | ␊ |
476 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
477 | {␊ |
478 | ␉static int idx = -1;␊ |
479 | ␉int␉map;␊ |
480 | ␊ |
481 | ␉if (!bootInfo->memDetect)␊ |
482 | ␉{␊ |
483 | ␉␉return false;␊ |
484 | ␉}␊ |
485 | ␊ |
486 | ␉idx++;␊ |
487 | ␊ |
488 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
489 | ␊ |
490 | ␉if (idx < MAX_RAM_SLOTS)␊ |
491 | ␉{␊ |
492 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
493 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
494 | ␉␉{␊ |
495 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
496 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
497 | ␉␉␉return true;␊ |
498 | ␉␉}␊ |
499 | ␉}␊ |
500 | ␊ |
501 | ␉value->string = NOT_AVAILABLE;␊ |
502 | ␉return true;␊ |
503 | }␊ |
504 | ␊ |
505 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
506 | {␊ |
507 | ␉static int idx = -1;␊ |
508 | ␉int␉map;␊ |
509 | ␊ |
510 | ␉if (!bootInfo->memDetect)␊ |
511 | ␉{␊ |
512 | ␉␉return false;␊ |
513 | ␉}␊ |
514 | ␊ |
515 | ␉idx++;␊ |
516 | ␉if (idx < MAX_RAM_SLOTS)␊ |
517 | ␉{␊ |
518 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
519 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
520 | ␉␉{␊ |
521 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
522 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
523 | ␉␉␉return true;␊ |
524 | ␉␉}␊ |
525 | ␉}␊ |
526 | ␊ |
527 | ␉value->string = NOT_AVAILABLE;␊ |
528 | ␉return true;␊ |
529 | }␊ |
530 | ␊ |
531 | ␊ |
532 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
533 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
534 | static const char * const SMTAG = "_SM_";␊ |
535 | static const char* const DMITAG = "_DMI_";␊ |
536 | ␊ |
537 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
538 | {␊ |
539 | ␉SMBEntryPoint␉*smbios;␊ |
540 | ␉/*␊ |
541 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
542 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
543 | ␉ */␊ |
544 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
545 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
546 | ␉{␊ |
547 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
548 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
549 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
550 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
551 | ␉␉{␊ |
552 | ␉␉␉return smbios;␊ |
553 | ␉ }␊ |
554 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
555 | ␉}␊ |
556 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
557 | ␉pause();␊ |
558 | ␉return NULL;␊ |
559 | }␊ |
560 | ␊ |
561 | |