1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␉msglog(x)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
25 | ␉␉switch (Platform.CPU.Family) {␊ |
26 | ␉␉␉case 0x06:␊ |
27 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
28 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
29 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
30 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
31 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
32 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
33 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
34 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
35 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
36 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
37 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
38 | ␉␉␉␉␉␉value->word = 0;␊ |
39 | ␉␉␉␉␉␉break;␊ |
40 | ␉␉␉␉␉default:␊ |
41 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
42 | break;␊ |
43 | ␉␉␉␉}␊ |
44 | ␉␉␉␉break;␊ |
45 | ␊ |
46 | ␉␉␉default:␊ |
47 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
48 | break;␊ |
49 | ␉␉}␊ |
50 | ␉} else {␊ |
51 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
52 | ␉}␊ |
53 | ␊ |
54 | ␉return true;␊ |
55 | }␊ |
56 | ␊ |
57 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
58 | {␊ |
59 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
60 | ␉return true;␊ |
61 | }␊ |
62 | ␊ |
63 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
64 | {␊ |
65 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
66 | ␉␉switch (Platform.CPU.Family) {␊ |
67 | ␉␉␉case 0x06:␊ |
68 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
69 | /*␊ |
70 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
71 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
72 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
73 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
74 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
75 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
76 | ␉␉␉␉␉␉return false;␊ |
77 | */␊ |
78 | ␉␉␉␉␉case 0x19:␊ |
79 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
80 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
81 | ␉␉␉␉␉case CPUID_MODEL_DALES:␊ |
82 | case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
83 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
85 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
86 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
87 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
88 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
89 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
90 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
91 | {␊ |
92 | // thanks to dgobe for i3/i5/i7 bus speed detection␊ |
93 | int nhm_bus = 0x3F;␊ |
94 | static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
95 | unsigned long did, vid;␊ |
96 | unsigned int i;␊ |
97 | ␊ |
98 | // Nehalem supports Scrubbing␊ |
99 | // First, locate the PCI bus where the MCH is located␊ |
100 | for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊ |
101 | vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
102 | did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
103 | vid &= 0xFFFF;␊ |
104 | did &= 0xFF00;␊ |
105 | ␊ |
106 | if(vid == 0x8086 && did >= 0x2C00) {␊ |
107 | nhm_bus = possible_nhm_bus[i];␊ |
108 | }␊ |
109 | }␊ |
110 | ␊ |
111 | unsigned long qpimult, qpibusspeed;␊ |
112 | qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
113 | qpimult &= 0x7F;␊ |
114 | verbose("qpimult %d\n", qpimult);␊ |
115 | qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
116 | // Rek: rounding decimals to match original mac profile info␊ |
117 | if (qpibusspeed%100 != 0) {␊ |
118 | qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
119 | }␊ |
120 | verbose("qpibusspeed %d\n", qpibusspeed);␊ |
121 | value->word = qpibusspeed;␊ |
122 | return true;␊ |
123 | }␊ |
124 | break;␊ |
125 | ␊ |
126 | ␉␉␉␉␉default:␊ |
127 | ␉␉␉␉␉␉break;␊ |
128 | ␉␉␉␉}␊ |
129 | break;␊ |
130 | ␊ |
131 | ␉␉␉default:␊ |
132 | ␉␉␉␉break;␊ |
133 | ␉␉}␊ |
134 | ␉}␊ |
135 | ␊ |
136 | ␉return false; //Unsupported CPU type␊ |
137 | }␊ |
138 | ␊ |
139 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
140 | {␊ |
141 | ␉if (Platform.CPU.NoCores >= 4) {␊ |
142 | ␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊ |
143 | ␉} else if (Platform.CPU.NoCores == 2) {␊ |
144 | ␉␉return 0x301;␉// 513 - Core 2 Duo␊ |
145 | ␉}␊ |
146 | ␉␊ |
147 | ␉return 0x201;␉␉// 769 - Core Duo␊ |
148 | }␊ |
149 | ␊ |
150 | bool getSMBOemProcessorType(returnType *value)␊ |
151 | {␊ |
152 | ␉static bool done = false;␊ |
153 | ␊ |
154 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
155 | ␊ |
156 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
157 | ␉␉if (!done) {␊ |
158 | ␉␉␉//DBG("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
159 | ␉␉␉done = true;␊ |
160 | ␉␉}␊ |
161 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊ |
162 | ␉␉switch (Platform.CPU.Family) {␊ |
163 | ␉␉␉case 0x06:␊ |
164 | ␉␉␉case 0x0F:␊ |
165 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
166 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
167 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
168 | case CPUID_MODEL_NOCONA:␊ |
169 | ␉␉␉␉␉case CPUID_MODEL_IRWINDALE:␊ |
170 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
171 | ␉␉␉␉␉␉{␊ |
172 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
173 | ␉␉␉␉␉␉}␊ |
174 | ␉␉␉␉␉␉return true;␊ |
175 | ␊ |
176 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
177 | ␉␉␉␉␉case CPUID_MODEL_CELERON:␊ |
178 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
179 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
180 | ␉␉␉␉␉␉return true;␊ |
181 | ␊ |
182 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
183 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
184 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
185 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
186 | ␉␉␉␉␉␉{␊ |
187 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
188 | return true;␊ |
189 | ␉␉␉␉␉␉}␊ |
190 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
191 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo , Pentium Dual Core etc.␊ |
192 | ␉␉␉␉␉␉} else {␊ |
193 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
194 | ␉␉␉␉␉␉}␊ |
195 | ␉␉␉␉␉␉return true;␊ |
196 | ␊ |
197 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
198 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
199 | ␉␉␉␉␉␉return true;␊ |
200 | ␊ |
201 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
202 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
203 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
204 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
205 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
206 | ␉␉␉␉␉␉{␊ |
207 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
208 | ␉␉␉␉␉␉␉return true;␊ |
209 | ␉␉␉␉␉␉}␊ |
210 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
211 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
212 | ␉␉␉␉␉␉␉return true;␊ |
213 | ␉␉␉␉␉␉}␊ |
214 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
215 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
216 | ␉␉␉␉␉␉␉return true;␊ |
217 | ␉␉␉␉␉␉}␊ |
218 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
219 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
220 | ␉␉␉␉␉␉␉return true;␊ |
221 | ␉␉␉␉␉␉}␊ |
222 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
223 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Pentium Dual Core as Core i3␊ |
224 | ␉␉␉␉␉␉}␊ |
225 | ␉␉␉␉␉␉return true;␊ |
226 | ␊ |
227 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
228 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
229 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
230 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
231 | ␉␉␉␉␉␉{␊ |
232 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
233 | ␉␉␉␉␉␉␉return true;␊ |
234 | ␉␉␉␉␉␉}␊ |
235 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
236 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
237 | ␉␉␉␉␉␉␉return true;␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
240 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
241 | ␉␉␉␉␉␉␉return true;␊ |
242 | ␉␉␉␉␉␉}␊ |
243 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
244 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
245 | ␉␉␉␉␉␉␉return true;␊ |
246 | ␉␉␉␉␉␉}␊ |
247 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
248 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Pentium Dual Core as Core i3␊ |
249 | ␉␉␉␉␉␉}␊ |
250 | ␉␉␉␉␉␉return true;␊ |
251 | ␊ |
252 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
253 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
254 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
255 | ␉␉␉␉␉␉{␊ |
256 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
257 | ␉␉␉␉␉␉␉return true;␊ |
258 | ␉␉␉␉␉␉}␊ |
259 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
264 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
265 | ␉␉␉␉␉␉␉return true;␊ |
266 | ␉␉␉␉␉␉}␊ |
267 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
268 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
269 | ␉␉␉␉␉␉␉return true;␊ |
270 | ␉␉␉␉␉␉}␊ |
271 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
272 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Pentium Dual Core as Core i3␊ |
273 | ␉␉␉␉␉␉}␊ |
274 | ␉␉␉␉␉␉return true;␊ |
275 | ␊ |
276 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
277 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
278 | ␉␉␉␉␉␉{␊ |
279 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
280 | ␉␉␉␉␉␉␉return true;␊ |
281 | ␉␉␉␉␉␉}␊ |
282 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
283 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
284 | ␉␉␉␉␉␉␉return true;␊ |
285 | ␉␉␉␉␉␉}␊ |
286 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
287 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
288 | ␉␉␉␉␉␉␉return true;␊ |
289 | ␉␉␉␉␉␉}␊ |
290 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
291 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
292 | ␉␉␉␉␉␉␉return true;␊ |
293 | ␉␉␉␉␉␉}␊ |
294 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
295 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Pentium Dual Core as Core i3␊ |
296 | ␉␉␉␉␉␉}␊ |
297 | ␉␉␉␉␉␉return true;␊ |
298 | ␊ |
299 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␉␉// 0x3E - Mac Pro 6,1␊ |
300 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
301 | ␉␉␉␉␉␉return true;␊ |
302 | ␊ |
303 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊ |
304 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
305 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
306 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
307 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
308 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
309 | ␉␉␉␉␉␉␉return true;␊ |
310 | ␉␉␉␉␉␉}␊ |
311 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
312 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
313 | ␉␉␉␉␉␉␉return true;␊ |
314 | ␉␉␉␉␉␉}␊ |
315 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
316 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
317 | ␉␉␉␉␉␉␉return true;␊ |
318 | ␉␉␉␉␉␉}␊ |
319 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
320 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
321 | ␉␉␉␉␉␉␉return true;␊ |
322 | ␉␉␉␉␉␉}␊ |
323 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
324 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Pentium Dual Core as Core i3␊ |
325 | ␉␉␉␉␉␉}␊ |
326 | ␉␉␉␉␉␉return true;␊ |
327 | ␊ |
328 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
329 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
330 | ␉␉␉␉␉␉return true;␊ |
331 | ␊ |
332 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
333 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
334 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
335 | ␉␉␉␉␉␉return true;␊ |
336 | ␉␉␉␉␉default:␊ |
337 | ␉␉␉␉␉␉break;␊ |
338 | ␉␉␉␉}␊ |
339 | break;␊ |
340 | ␊ |
341 | default:␊ |
342 | ␉␉␉␉break;␊ |
343 | ␉␉}␊ |
344 | ␉}␊ |
345 | ␉␊ |
346 | ␉return false;␊ |
347 | }␊ |
348 | ␊ |
349 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
350 | {␊ |
351 | ␉static int idx = -1;␊ |
352 | ␉int␉map;␊ |
353 | ␊ |
354 | ␉if (!bootInfo->memDetect) {␊ |
355 | ␉␉return false;␊ |
356 | ␉}␊ |
357 | ␊ |
358 | ␉idx++;␊ |
359 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
360 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
361 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊ |
362 | ␉␉␉verbose("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
363 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
364 | ␉␉␉return true;␊ |
365 | ␉␉}␊ |
366 | ␉}␊ |
367 | ␊ |
368 | ␉value->byte = 2; // means Unknown␊ |
369 | ␉return true;␊ |
370 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
371 | //␉return true;␊ |
372 | }␊ |
373 | ␊ |
374 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
375 | {␊ |
376 | ␉value->word = 0xFFFF;␊ |
377 | ␉return true;␊ |
378 | }␊ |
379 | ␊ |
380 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
381 | {␊ |
382 | ␉static int idx = -1;␊ |
383 | ␉int␉map;␊ |
384 | ␊ |
385 | ␉if (!bootInfo->memDetect) {␊ |
386 | ␉␉return false;␊ |
387 | ␉}␊ |
388 | ␊ |
389 | ␉idx++;␊ |
390 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
391 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
392 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊ |
393 | ␉␉␉verbose("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
394 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
395 | ␉␉␉return true;␊ |
396 | ␉␉}␊ |
397 | ␉}␊ |
398 | ␊ |
399 | ␉value->dword = 0; // means Unknown␊ |
400 | ␉return true;␊ |
401 | //␉value->dword = 800;␊ |
402 | //␉return true;␊ |
403 | }␊ |
404 | ␊ |
405 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
406 | {␊ |
407 | ␉static int idx = -1;␊ |
408 | ␉int␉map;␊ |
409 | ␊ |
410 | ␉if (!bootInfo->memDetect) {␊ |
411 | ␉␉return false;␊ |
412 | ␉}␊ |
413 | ␊ |
414 | ␉idx++;␊ |
415 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
416 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
417 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊ |
418 | ␉␉␉verbose("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
419 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
420 | ␉␉␉return true;␊ |
421 | ␉␉}␊ |
422 | ␉}␊ |
423 | ␊ |
424 | ␉value->string = NOT_AVAILABLE;␊ |
425 | ␉return true;␊ |
426 | }␊ |
427 | ␊ |
428 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
429 | {␊ |
430 | ␉static int idx = -1;␊ |
431 | ␉int␉map;␊ |
432 | ␊ |
433 | ␉if (!bootInfo->memDetect) {␊ |
434 | ␉␉return false;␊ |
435 | ␉}␊ |
436 | ␊ |
437 | ␉idx++;␊ |
438 | ␊ |
439 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
440 | ␊ |
441 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
442 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
443 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊ |
444 | ␉␉␉verbose("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
445 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
446 | ␉␉␉return true;␊ |
447 | ␉␉}␊ |
448 | ␉}␊ |
449 | ␊ |
450 | ␉value->string = NOT_AVAILABLE;␊ |
451 | ␉return true;␊ |
452 | }␊ |
453 | ␊ |
454 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
455 | {␊ |
456 | ␉static int idx = -1;␊ |
457 | ␉int␉map;␊ |
458 | ␊ |
459 | ␉if (!bootInfo->memDetect) {␊ |
460 | ␉␉return false;␊ |
461 | ␉}␊ |
462 | ␊ |
463 | ␉idx++;␊ |
464 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
465 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
466 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊ |
467 | ␉␉␉verbose("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
468 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
469 | ␉␉␉return true;␊ |
470 | ␉␉}␊ |
471 | ␉}␊ |
472 | ␊ |
473 | ␉value->string = NOT_AVAILABLE;␊ |
474 | ␉return true;␊ |
475 | }␊ |
476 | ␊ |
477 | ␊ |
478 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
479 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
480 | static const char * const SMTAG = "_SM_";␊ |
481 | static const char* const DMITAG = "_DMI_";␊ |
482 | ␊ |
483 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
484 | {␊ |
485 | ␉SMBEntryPoint␉*smbios;␊ |
486 | ␉/*␊ |
487 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
488 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
489 | ␉ */␊ |
490 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
491 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
492 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
493 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
494 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
495 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊ |
496 | ␉␉␉return smbios;␊ |
497 | ␉ }␊ |
498 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
499 | ␉}␊ |
500 | ␉error("ERROR: Unable to find SMBIOS!\n");␊ |
501 | ␉pause("");␊ |
502 | ␉return NULL;␊ |
503 | }␊ |
504 | ␊ |
505 | |