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1/*␊
2 * platform.h␊
3 * AsereBLN: reworked and extended␊
4 *␊
5 */␊
6␊
7#ifndef __LIBSAIO_PLATFORM_H␊
8#define __LIBSAIO_PLATFORM_H␊
9␊
10//#include "libsaio.h"␊
11␊
12extern bool platformCPUFeature(uint32_t);␊
13extern void scan_platform(void);␊
14extern void dumpPhysAddr(const char * title, void * a, int len);␊
15␊
16/* CPUID Vendor */␊
17#define CPUID_VENDOR_INTEL 0x756E6547 // "uneG"␊
18#define CPUID_VENDOR_AMD 0x68747541 // "htuA"␊
19␊
20/* CPUID index into cpuid_raw */␊
21#define CPUID_0␉␉␉␉0␊
22#define CPUID_1␉␉␉␉1␊
23#define CPUID_2␉␉␉␉2␊
24#define CPUID_3␉␉␉␉3␊
25#define CPUID_4␉␉␉␉4␊
26#define CPUID_5␉␉␉␉5␊
27#define CPUID_6␉␉␉␉6␊
28#define CPUID_80␉␉␉7␊
29#define CPUID_81␉␉␉8␊
30#define CPUID_88␉␉␉9␊
31#define CPUID_MAX␉␉␉10␊
32␊
33#define CPUID_MODEL_ANY 0xFF␊
34#define CPUID_MODEL_UNKNOWN 0x00␊
35//#define CPUID_MODEL_PRESCOTT 0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊
36#define CPUID_MODEL_NOCONA 0x03␉␉␉// Celeron D, Pentium 4, Xeon (90nm)␊
37//#define CPUID_MODEL_NOCONA 0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊
38#define CPUID_MODEL_IRWINDALE 0x04␉␉␉// Xeon Paxville, Irwindale (90nm)␊
39#define CPUID_MODEL_PRESLER 0x06␉␉␉// Pentium 4, Pentium D (65nm)␊
40#define CPUID_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊
41#define CPUID_MODEL_DOTHAN 0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊
42#define CPUID_MODEL_YONAH 0x0E␉␉␉// Sossaman, Yonah␊
43#define CPUID_MODEL_MEROM 0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
44//#define CPUID_MODEL_CONROE␉␉0x0F␉␉␉//␊
45#define CPUID_MODEL_CELERON 0x16␉␉␉// Merom, Conroe (65nm), Celeron (45nm)␊
46#define CPUID_MODEL_PENRYN 0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
47//#define CPUID_MODEL_WOLFDALE␉␉0x17␉␉␉// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx␊
48#define CPUID_MODEL_NEHALEM 0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
49#define CPUID_MODEL_ATOM 0x1C␉␉␉// Pineview, Bonnell␊
50#define CPUID_MODEL_XEON_MP 0x1D␉␉␉// MP 7400␊
51#define CPUID_MODEL_FIELDS 0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
52#define CPUID_MODEL_DALES 0x1F␉␉␉// Havendale, Auburndale␊
53#define CPUID_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
54#define CPUID_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
55#define CPUID_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊
56#define CPUID_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
57#define CPUID_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
58#define CPUID_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
59#define CPUID_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
60#define CPUID_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
61//#define CPUID_MODEL_BONNELL_ATOM␉0x35␉␉␉// Atom Family Bonnell␊
62#define CPUID_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊
63#define CPUID_MODEL_SILVERMONT␉␉0x37␉␉␉// Atom E3000, Z3000 Atom Silvermont␊
64#define CPUID_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
65#define CPUID_MODEL_HASWELL 0x3C␉␉␉// Haswell DT␊
66#define CPUID_MODEL_BROADWELL␉␉0x3D␉␉␉// Core M, Broadwell / Core-AVX2␊
67//#define CPUID_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
68#define CPUID_MODEL_IVYBRIDGE_EP␉0x3E␉␉␉// Ivy Bridge Xeon␊
69#define CPUID_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E)␊
70//#define CPUID_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
71#define CPUID_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT, 4th gen Core, Xeon E3-12xx v3␊
72#define CPUID_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Crystal Well, 4th gen Core, Xeon E3-12xx v3␊
73//#define CPUID_MODEL_␉␉␉0x4A␉␉␉// Future Atom E3000, Z3000 silvermont / atom␊
74#define CPUID_MODEL_AVOTON 0x4D␉␉␉// Silvermont/Avoton Atom C2000␊
75//#define CPUID_MODEL_␉␉␉0x4E␉␉␉// Future Core␊
76#define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server␊
77#define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon␊
78//#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊
79//#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊
80␊
81/* CPU Features */␊
82#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
83#define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊
84#define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊
85#define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊
86#define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊
87#define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊
88#define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊
89#define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊
90#define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊
91#define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊
92␊
93/* SMBIOS Memory Types */ ␊
94#define SMB_MEM_TYPE_UNDEFINED␉0␊
95#define SMB_MEM_TYPE_OTHER␉␉1␊
96#define SMB_MEM_TYPE_UNKNOWN␉2␊
97#define SMB_MEM_TYPE_DRAM␉␉3␊
98#define SMB_MEM_TYPE_EDRAM␉␉4␊
99#define SMB_MEM_TYPE_VRAM␉␉5␊
100#define SMB_MEM_TYPE_SRAM␉␉6␊
101#define SMB_MEM_TYPE_RAM␉␉7␊
102#define SMB_MEM_TYPE_ROM␉␉8␊
103#define SMB_MEM_TYPE_FLASH␉␉9␊
104#define SMB_MEM_TYPE_EEPROM␉␉10␊
105#define SMB_MEM_TYPE_FEPROM␉␉11␊
106#define SMB_MEM_TYPE_EPROM␉␉12␊
107#define SMB_MEM_TYPE_CDRAM␉␉13␊
108#define SMB_MEM_TYPE_3DRAM␉␉14␊
109#define SMB_MEM_TYPE_SDRAM␉␉15␊
110#define SMB_MEM_TYPE_SGRAM␉␉16␊
111#define SMB_MEM_TYPE_RDRAM␉␉17␊
112#define SMB_MEM_TYPE_DDR␉␉18␊
113#define SMB_MEM_TYPE_DDR2␉␉19␊
114#define SMB_MEM_TYPE_FBDIMM␉␉20␊
115#define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊
116#define SMB_MEM_TYPE_DDR4␉␉26␊
117␊
118/* Memory Configuration Types */ ␊
119#define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊
120#define SMB_MEM_CHANNEL_SINGLE␉␉1␊
121#define SMB_MEM_CHANNEL_DUAL␉␉2␊
122#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
123␊
124/* Maximum number of ram slots */␊
125#define MAX_RAM_SLOTS␉␉␉8␊
126#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
127␊
128/* Maximum number of SPD bytes */␊
129#define MAX_SPD_SIZE␉␉␉256␊
130␊
131/* Size of SMBIOS UUID in bytes */␊
132#define UUID_LEN␉␉␉16␊
133␊
134typedef struct _RamSlotInfo_t␊
135{␊
136␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
137␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
138␉const char*␉␉Vendor;␊
139␉const char*␉␉PartNo;␊
140␉const char*␉␉SerialNo;␊
141␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
142␉bool␉␉␉InUse;␊
143␉uint8_t␉␉␉Type;␊
144␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
145␉uint8_t␉␉␉BankConnCnt;␊
146} RamSlotInfo_t;␊
147␊
148//==============================================================================␊
149␊
150typedef struct _PlatformInfo_t␊
151{␊
152␉struct CPU {␊
153␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
154␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
155␉␉//uint32_t␉␉CoresPerPackage;␊
156␉␉//uint32_t␉␉LogicalPerPackage;␊
157␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
158␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
159␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊
160␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
161␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
162␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
163␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊
164␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
165␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
166␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
167␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊
168␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
169␉␉uint8_t␉␉␉CurrDiv;␊
170␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
171␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
172␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
173␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
174␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
175␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
176␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
177␉} CPU;␊
178␊
179␉struct RAM {␊
180␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
181␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
182␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
183␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
184␉␉uint8_t␉␉␉TRP;␊
185␉␉uint8_t␉␉␉RAS;␊
186␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
187␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
188␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
189␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
190␉} RAM;␊
191␊
192␉struct DMI {␊
193␉␉int␉␉␉MaxMemorySlots; // number of memory slots populated by SMBIOS␊
194␉␉int␉␉␉CntMemorySlots; // number of memory slots counted␊
195␉␉int␉␉␉MemoryModules; // number of memory modules installed␊
196␉␉int␉␉␉DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot␊
197␉} DMI;␊
198␊
199␉uint8_t␉␉␉␉Type; // system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊
200␉uint8_t␉␉␉␉*UUID; // system-id (SMBIOS Table 1: system uuid)␊
201 uint32_t HWSignature; // machine-signature (FACS: Hardware Signature)␊
202} PlatformInfo_t;␊
203␊
204extern PlatformInfo_t Platform;␊
205␊
206#endif /* !__LIBSAIO_PLATFORM_H */␊
207

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