| 1 | #ifndef __LIBSAIO_ACPI_H␊ |
| 2 | #define __LIBSAIO_ACPI_H␊ |
| 3 | ␊ |
| 4 | #define ACPI_RANGE_START (0x0E0000)␊ |
| 5 | #define ACPI_RANGE_END (0x0FFFFF)␊ |
| 6 | ␊ |
| 7 | #define UINT64_LE_FROM_CHARS(a,b,c,d,e,f,g,h) \␊ |
| 8 | ( ((uint64_t)h << 56) \␊ |
| 9 | | ((uint64_t)g << 48) \␊ |
| 10 | | ((uint64_t)f << 40) \␊ |
| 11 | | ((uint64_t)e << 32) \␊ |
| 12 | | ((uint64_t)d << 24) \␊ |
| 13 | | ((uint64_t)c << 16) \␊ |
| 14 | | ((uint64_t)b << 8) \␊ |
| 15 | | ((uint64_t)a << 0) \␊ |
| 16 | )␊ |
| 17 | ␊ |
| 18 | #define ACPI_SIGNATURE_UINT64_LE UINT64_LE_FROM_CHARS('R','S','D',' ','P','T','R',' ')␊ |
| 19 | ␊ |
| 20 | /* Per ACPI 3.0a spec */␊ |
| 21 | ␊ |
| 22 | // TODO Migrate␊ |
| 23 | struct acpi_2_rsdp␊ |
| 24 | {␊ |
| 25 | ␉// 1.0␊ |
| 26 | ␉char␉␉␉Signature[8];␊ |
| 27 | ␉uint8_t␉␉␉Checksum;␊ |
| 28 | ␉char␉␉␉OEMID[6];␊ |
| 29 | ␉uint8_t␉␉␉Revision;␊ |
| 30 | ␉uint32_t␉␉RsdtAddress;␊ |
| 31 | ␉// 2.0␊ |
| 32 | ␉uint32_t␉␉Length;␊ |
| 33 | ␉uint64_t␉␉XsdtAddress;␊ |
| 34 | ␉uint8_t␉␉␉ExtendedChecksum;␊ |
| 35 | ␉char␉␉␉Reserved[3];␊ |
| 36 | } __attribute__((packed));␊ |
| 37 | ␊ |
| 38 | // TODO Migrate␊ |
| 39 | struct acpi_2_rsdt␊ |
| 40 | {␊ |
| 41 | ␉char␉␉␉Signature[4];␊ |
| 42 | ␉uint32_t␉␉Length;␊ |
| 43 | ␉uint8_t␉␉␉Revision;␊ |
| 44 | ␉uint8_t␉␉␉Checksum;␊ |
| 45 | ␉char␉␉␉OEMID[6];␊ |
| 46 | ␉char␉␉␉OEMTableId[8];␊ |
| 47 | ␉uint32_t␉␉OEMRevision;␊ |
| 48 | ␉uint32_t␉␉CreatorId;␊ |
| 49 | ␉uint32_t␉␉CreatorRevision;␊ |
| 50 | } __attribute__((packed));␊ |
| 51 | ␊ |
| 52 | // TODO Migrate␊ |
| 53 | struct acpi_2_xsdt␊ |
| 54 | {␊ |
| 55 | ␉char␉␉␉Signature[4];␊ |
| 56 | ␉uint32_t␉␉Length;␊ |
| 57 | ␉uint8_t␉␉␉Revision;␊ |
| 58 | ␉uint8_t␉␉␉Checksum;␊ |
| 59 | ␉char␉␉␉OEMID[6];␊ |
| 60 | ␉char␉␉␉OEMTableId[8];␊ |
| 61 | ␉uint32_t␉␉OEMRevision;␊ |
| 62 | ␉uint32_t␉␉CreatorId;␊ |
| 63 | ␉uint32_t␉␉CreatorRevision;␊ |
| 64 | } __attribute__((packed));␊ |
| 65 | ␊ |
| 66 | // TODO Migrate␊ |
| 67 | struct acpi_2_ssdt␊ |
| 68 | {␊ |
| 69 | ␉char␉␉␉Signature[4];␊ |
| 70 | ␉uint32_t␉␉Length;␊ |
| 71 | ␉uint8_t␉␉␉Revision;␊ |
| 72 | ␉uint8_t␉␉␉Checksum;␊ |
| 73 | ␉char␉␉␉OEMID[6];␊ |
| 74 | ␉char␉␉␉OEMTableId[8];␊ |
| 75 | ␉uint32_t␉␉OEMRevision;␊ |
| 76 | ␉uint32_t␉␉CreatorId;␊ |
| 77 | ␉uint32_t␉␉CreatorRevision;␊ |
| 78 | } __attribute__((packed));␊ |
| 79 | ␊ |
| 80 | // TODO Migrate␊ |
| 81 | struct acpi_2_dsdt␊ |
| 82 | {␊ |
| 83 | ␉char␉␉␉Signature[4];␊ |
| 84 | ␉uint32_t␉␉Length;␊ |
| 85 | ␉uint8_t␉␉␉Revision;␊ |
| 86 | ␉uint8_t␉␉␉Checksum;␊ |
| 87 | ␉char␉␉␉OEMID[6];␊ |
| 88 | ␉char␉␉␉OEMTableId[8];␊ |
| 89 | ␉uint32_t␉␉OEMRevision;␊ |
| 90 | ␉uint32_t␉␉CreatorId;␊ |
| 91 | ␉uint32_t␉␉CreatorRevision;␊ |
| 92 | } __attribute__((packed));␊ |
| 93 | ␊ |
| 94 | // TODO Migrate␊ |
| 95 | struct acpi_2_fadt␊ |
| 96 | {␊ |
| 97 | ␉char␉␉␉Signature[4];␊ |
| 98 | ␉uint32_t␉␉Length;␊ |
| 99 | ␉uint8_t␉␉␉Revision;␊ |
| 100 | ␉uint8_t␉␉␉Checksum;␊ |
| 101 | ␉char␉␉␉OEMID[6];␊ |
| 102 | ␉char␉␉␉OEMTableId[8];␊ |
| 103 | ␉uint32_t␉␉OEMRevision;␊ |
| 104 | ␉uint32_t␉␉CreatorId;␊ |
| 105 | ␉uint32_t␉␉CreatorRevision;␊ |
| 106 | ␉uint32_t␉␉FIRMWARE_CTRL;␊ |
| 107 | ␉uint32_t␉␉DSDT;␊ |
| 108 | ␉uint8_t␉␉␉Model;␉␉␉// JrCs␊ |
| 109 | ␉uint8_t␉␉␉PM_Profile;␉␉// JrCs␊ |
| 110 | ␉uint16_t␉␉SCI_Interrupt;␊ |
| 111 | ␉uint32_t␉␉SMI_Command_Port;␊ |
| 112 | ␉uint8_t␉␉␉ACPI_Enable;␊ |
| 113 | ␉uint8_t␉␉␉ACPI_Disable;␊ |
| 114 | ␉uint8_t␉␉␉S4BIOS_Command;␊ |
| 115 | ␉uint8_t␉␉␉PState_Control;␊ |
| 116 | ␉uint32_t␉␉PM1A_Event_Block_Address;␊ |
| 117 | ␉uint32_t␉␉PM1B_Event_Block_Address;␊ |
| 118 | ␉uint32_t␉␉PM1A_Control_Block_Address;␊ |
| 119 | ␉uint32_t␉␉PM1B_Control_Block_Address;␊ |
| 120 | ␉uint32_t␉␉PM2_Control_Block_Address;␊ |
| 121 | ␉uint32_t␉␉PM_Timer_Block_Address;␊ |
| 122 | ␉uint32_t␉␉GPE0_Block_Address;␊ |
| 123 | ␉uint32_t␉␉GPE1_Block_Address;␊ |
| 124 | ␉uint8_t␉␉␉PM1_Event_Block_Length;␊ |
| 125 | ␉uint8_t␉␉␉PM1_Control_Block_Length;␊ |
| 126 | ␉uint8_t␉␉␉PM2_Control_Block_Length;␊ |
| 127 | ␉uint8_t␉␉␉PM_Timer_Block_Length;␊ |
| 128 | ␉uint8_t␉␉␉GPE0_Block_Length;␊ |
| 129 | ␉uint8_t␉␉␉GPE1_Block_Length;␊ |
| 130 | ␉uint8_t␉␉␉GPE1_Base_Offset;␊ |
| 131 | ␉uint8_t␉␉␉CST_Support;␊ |
| 132 | ␉uint16_t␉␉C2_Latency;␊ |
| 133 | ␉uint16_t␉␉C3_Latency;␊ |
| 134 | ␉uint16_t␉␉CPU_Cache_Size;␊ |
| 135 | ␉uint16_t␉␉Cache_Flush_Stride;␊ |
| 136 | ␉uint8_t␉␉␉Duty_Cycle_Offset;␊ |
| 137 | ␉uint8_t␉␉␉Duty_Cycle_Width;␊ |
| 138 | ␉uint8_t␉␉␉RTC_Day_Alarm_Index;␊ |
| 139 | ␉uint8_t␉␉␉RTC_Month_Alarm_Index;␊ |
| 140 | ␉uint8_t␉␉␉RTC_Century_Index;␊ |
| 141 | ␉uint16_t␉␉Boot_Flags;␊ |
| 142 | ␉uint8_t␉␉␉Reserved0;␊ |
| 143 | /* Begin Asere */␊ |
| 144 | ␉//Reset Fix␊ |
| 145 | ␉uint32_t Flags;␊ |
| 146 | ␉// Reset Register␊ |
| 147 | ␉uint8_t Reset_SpaceID;␊ |
| 148 | ␉uint8_t Reset_BitWidth;␊ |
| 149 | ␉uint8_t Reset_BitOffset;␊ |
| 150 | ␉uint8_t Reset_AccessWidth;␊ |
| 151 | ␉uint64_t Reset_Address;␊ |
| 152 | ␉uint8_t Reset_Value;␊ |
| 153 | ␉uint8_t Reserved[3];␊ |
| 154 | ␊ |
| 155 | ␉uint64_t␉ X_FIRMWARE_CTRL;␊ |
| 156 | ␉uint64_t␉ X_DSDT;␊ |
| 157 | /* End Asere */␊ |
| 158 | ␉/*We absolutely don't care about theese fields*/␊ |
| 159 | ␉uint8_t␉␉notimp2[96];␊ |
| 160 | } __attribute__((packed));␊ |
| 161 | ␊ |
| 162 | #endif /* !__LIBSAIO_ACPI_H */␊ |
| 163 | |
