Chameleon

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Root/trunk/i386/libsaio/spd.c

1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5 by netkas␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉/* 09h Undefined */␊
40␉"",␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE,␉␉/* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE,␉␉/* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE,␉␉/* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉␉/* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM,␉␉/* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉␉/* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM,␉␉/* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR,␉␉/* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2,␉␉/* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE,␉␉/* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉␉/* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3␉␉/* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73␊
74unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
75{␊
76␉int l1, h1, l2, h2;␊
77␉unsigned long long t;␊
78␊
79␉outb(base + SMBHSTSTS, 0x1f);␉// reset SMBus Controller␊
80␉outb(base + SMBHSTDAT, 0xff);␊
81␊
82␉rdtsc(l1, h1);␊
83␉while ( inb(base + SMBHSTSTS) & 0x01) // wait until read␊
84␉{␊
85␉␉rdtsc(l2, h2);␊
86␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
87␉␉if (t > 5)␊
88␉␉{␊
89␉␉␉return 0xFF;␉// break␊
90␉␉}␊
91␉}␊
92␊
93␉outb(base + SMBHSTCMD, cmd);␊
94␉outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
95␉outb(base + SMBHSTCNT, 0x48 );␊
96␊
97␉rdtsc(l1, h1);␊
98␊
99␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
100␉{␊
101␉␉rdtsc(l2, h2);␊
102␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
103␉␉if (t > 5)␊
104␉␉{␊
105␉␉␉break;␉// break after 5ms␊
106␉␉}␊
107␉}␊
108␉return inb(base + SMBHSTDAT);␊
109}␊
110␊
111/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
112#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
113␊
114int spd_indexes[] = {␊
115␉SPD_MEMORY_TYPE,␊
116␉SPD_DDR3_MEMORY_BANK,␊
117␉SPD_DDR3_MEMORY_CODE,␊
118␉SPD_NUM_ROWS,␊
119␉SPD_NUM_COLUMNS,␊
120␉SPD_NUM_DIMM_BANKS,␊
121␉SPD_NUM_BANKS_PER_SDRAM,␊
122␉4,7,8,9,12,64, /* TODO: give names to these values */␊
123␉95,96,97,98, 122,123,124,125 /* UIS */␊
124};␊
125#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
126␊
127/** Read from spd *used* values only*/␊
128static void init_spd(char * spd, uint32_t base, int slot)␊
129{␊
130␉int i;␊
131␉for (i = 0; i < SPD_INDEXES_SIZE; i++)␊
132␉{␊
133␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
134␉}␊
135}␊
136␊
137/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
138 have different formats, always return a valid ptr.*/␊
139const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
140{␊
141␉uint8_t bank = 0;␊
142␉uint8_t code = 0;␊
143␉int i = 0;␊
144␉uint8_t * spd = (uint8_t *) slot->spd;␊
145␊
146␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3)␊
147␉{ // DDR3␊
148␉␉bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
149␉␉code = spd[SPD_DDR3_MEMORY_CODE];␊
150␉␉for (i=0; i < VEN_MAP_SIZE; i++) {␊
151␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code) {␊
152␉␉␉␉return vendorMap[i].name;␊
153␉␉␉}␊
154␉␉}␊
155␉} else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) {␊
156␉␉if(spd[64]==0x7f) {␊
157␉␉␉for (i=64; i<72 && spd[i]==0x7f;i++) {␊
158␉␉␉␉bank++;␊
159␉␉␉␉READ_SPD(spd, base, slot_num, (uint8_t)(i+1)); // prefetch next spd byte to read for next loop␊
160␉␉␉}␊
161␉␉␉READ_SPD(spd, base, slot_num,(uint8_t)i);␊
162␉␉␉code = spd[i];␊
163␉␉} else {␊
164␉␉␉code = spd[64]; ␊
165␉␉␉bank = 0;␊
166␉␉}␊
167␉␉for (i=0; i < VEN_MAP_SIZE; i++) {␊
168␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code) {␊
169␉␉␉␉return vendorMap[i].name;␊
170␉␉␉}␊
171␉␉}␊
172␉}␊
173␉/* OK there is no vendor id here lets try to match the partnum if it exists */␊
174␉if (strstr(slot->PartNo,"GU332") == slot->PartNo) { // Unifosa fingerprint␊
175␉␉return "Unifosa";␊
176␉}␊
177␉return "NoName";␊
178}␊
179␊
180/* Get Default Memory Module Speed (no overclocking handled) */␊
181int getDDRspeedMhz(const char * spd)␊
182{␊
183␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
184␉␉switch(spd[12]) {␊
185␉␉␉case 0x0f:␊
186␉␉␉␉return 1066;␊
187␉␉␉case 0x0c:␊
188␉␉␉␉return 1333;␊
189␉␉␉case 0x0a:␊
190␉␉␉␉return 1600;␊
191␉␉␉case 0x14:␊
192␉␉␉default:␊
193␉␉␉␉return 800;␊
194␉␉}␊
195␉} else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) {␊
196␉␉switch(spd[9]) {␊
197␉␉␉case 0x50:␊
198␉␉␉␉return 400;␊
199␉␉␉case 0x3d:␊
200␉␉␉␉return 533;␊
201␉␉␉case 0x30:␊
202␉␉␉␉return 667;␊
203␉␉␉case 0x25:␊
204␉␉␉default:␊
205␉␉␉␉return 800;␊
206␉␉␉case 0x1E:␊
207␉␉␉␉return 1066;␊
208␉␉}␊
209␉}␊
210␉return 800; // default freq for unknown types␊
211}␊
212␊
213#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
214#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
215␊
216/* Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
217const char *getDDRSerial(const char* spd)␊
218{␊
219␉static char asciiSerial[16];␊
220␊
221␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
222␉{␊
223␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
224␉}␊
225␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR) // DDR2 or DDR␊
226␉{␊
227␉␉snprintf(asciiSerial, sizeof(asciiSerial), "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
228␉} else {␊
229␉␉sprintf(asciiSerial, "000000000000000");␊
230␉}␊
231␊
232␉return strdup(asciiSerial);␊
233}␊
234␊
235/* Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
236const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
237{␊
238␉static char asciiPartNo[32];␊
239␉int i, start=0, index = 0;␊
240␊
241␉if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
242␉␉start = 128;␊
243␉}␊
244␉else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2 || spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR)␊
245␉{␊
246␉␉start = 73;␊
247␉}␊
248␉␊
249␉// Check that the spd part name is zero terminated and that it is ascii:␊
250␉bzero(asciiPartNo, sizeof(asciiPartNo));␊
251␉char c;␊
252␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
253␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
254␉␉c = spd[i];␊
255␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) {␊
256␉␉␉// It seems that System Profiler likes only letters and digits...␊
257␉␉␉asciiPartNo[index++] = c;␊
258␉␉} else if (!isascii(c)) {␊
259␉␉␉break;␊
260␉␉}␊
261␉}␊
262␊
263␉return strdup(asciiPartNo);␊
264}␊
265␊
266int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
267␊
268␊
269/* Read from smbus the SPD content and interpret it for detecting memory attributes */␊
270static void read_smb_intel(pci_dt_t *smbus_dev) {␊
271␉int i, speed;␊
272␉uint8_t spd_size, spd_type;␊
273␉uint32_t base, mmio, hostc;␊
274//␉bool dump = false;␊
275␉RamSlotInfo_t* slot;␊
276␊
277␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
278␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
279␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
280␊
281␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
282␉base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
283␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
284␉verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
285␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
286␊
287␉//Azi: no use for this!␊
288␉// getBoolForKey("DumpSPD", &dump, &bootInfo->chameleonConfig);␊
289␉// needed at least for laptops␊
290␉bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
291␊
292␉char spdbuf[MAX_SPD_SIZE];␊
293␉// Search MAX_RAM_SLOTS slots␊
294␉for (i = 0; i < MAX_RAM_SLOTS; i++) {␊
295␉␉slot = &Platform.RAM.DIMM[i];␊
296␉␉spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
297␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
298␉␉// Check spd is present␊
299␉␉if (spd_size && (spd_size != 0xff)) {␊
300␊
301␉␉␉slot->spd = spdbuf;␊
302␉␉␉slot->InUse = true;␊
303␊
304␉␉␉bzero(slot->spd, spd_size);␊
305␊
306␉␉␉// Copy spd data into buffer␊
307␊
308␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
309␉␉␉init_spd(slot->spd, base, i);␊
310␊
311␉␉␉switch (slot->spd[SPD_MEMORY_TYPE]) {␊
312␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR:␊
313␊
314␉␉␉␉slot->ModuleSize = (((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f)␊
315 + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
316 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * ␊
317 slot->spd[SPD_NUM_BANKS_PER_SDRAM])/3)*2;␊
318␉␉␉␉break;␊
319␊
320␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
321␊
322␉␉␉␉␉slot->ModuleSize = ((1 << ((slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17)) *␊
323␉␉␉␉␉␉␉((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
324␉␉␉␉break;␊
325␊
326␉␉␉␉case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
327␊
328␉␉␉␉␉slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
329␉␉␉␉␉slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
330␉␉␉␉␉slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
331␊
332␉␉␉␉break;␊
333␉␉␉}␊
334␊
335␉␉␉spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
336␉␉␉slot->Type = spd_mem_to_smbios[spd_type];␊
337␉␉␉if (slot->Type == UNKNOWN_MEM_TYPE) {␊
338␉␉␉␉continue;␊
339␉␉␉}␊
340␉␉␉slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
341␉␉␉slot->Vendor = getVendorName(slot, base, i);␊
342␉␉␉slot->SerialNo = getDDRSerial(slot->spd);␊
343␊
344␉␉␉// determine spd speed␊
345␉␉␉speed = getDDRspeedMhz(slot->spd);␊
346␉␉␉if (slot->Frequency < speed) {␊
347␉␉␉␉slot->Frequency = speed;␊
348␉␉␉}␊
349␊
350␉␉␉// pci memory controller if available, is more reliable␊
351␉␉␉if (Platform.RAM.Frequency > 0) {␊
352␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
353␉␉␉␉// now round off special cases␊
354␉␉␉␉uint32_t fmod100 = freq %100;␊
355␉␉␉␉switch(fmod100) {␊
356␉␉␉␉␉case 1:␉freq--;␉break;␊
357␉␉␉␉␉case 32:␉freq++;␉break;␊
358␉␉␉␉␉case 65:␉freq++; break;␊
359␉␉␉␉␉case 98:␉freq+=2;break;␊
360␉␉␉␉␉case 99:␉freq++; break;␊
361␉␉␉␉}␊
362␉␉␉␉slot->Frequency = freq;␊
363␉␉␉}␊
364␊
365␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
366 i,␊
367 (int)slot->Type,␊
368 slot->ModuleSize, ␊
369 spd_memory_types[spd_type],␊
370 slot->Frequency,␊
371 slot->Vendor,␊
372 slot->PartNo,␊
373 slot->SerialNo);␊
374 slot->InUse = true;␊
375␉␉}␊
376␊
377␉␉// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
378␉␉Platform.DMI.DIMM[i]= ␊
379 ␉(uint32_t)((i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2) ?␊
380 ␉mapping[i] : i); // for laptops case, mapping setup would need to be more generic than this␊
381␉␉slot->spd = NULL;␊
382␊
383␉} // for␊
384}␊
385␊
386static struct smbus_controllers_t smbus_controllers[] = {␊
387␊
388␉{0x8086, 0x1C22, "P67", read_smb_intel }, // Z68, Q67␊
389␉{0x8086, 0x1D22, "X79", read_smb_intel },␊
390␉{0x8086, 0x1D70, "X79", read_smb_intel },␊
391␉{0x8086, 0x1D71, "X79", read_smb_intel },␊
392␉{0x8086, 0x1D72, "C608", read_smb_intel },␊
393␉{0x8086, 0x1E22, "Z77", read_smb_intel }, // H77, Q77␊
394␉{0x8086, 0x2330, "DH89xxCC", read_smb_intel },␊
395␉{0x8086, 0x2413, "82801AA", read_smb_intel },␊
396␉{0x8086, 0x2423, "BAM", read_smb_intel },␊
397␉{0x8086, 0x2443, "BAM", read_smb_intel },␊
398␉{0x8086, 0x2483, "CAM", read_smb_intel },␊
399␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
400␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
401␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
402␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
403␉{0x8086, 0x269B, "ESB", read_smb_intel },␊
404␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
405␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
406␉{0x8086, 0x2930, "ICH9", read_smb_intel },␊
407␉{0x8086, 0x3A30, "ICH10", read_smb_intel },␊
408␉{0x8086, 0x3A60, "ICH10", read_smb_intel },␊
409␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
410␉{0x8086, 0x5032, "EP80579", read_smb_intel },␊
411␉{0x8086, 0x8119, "US15W", read_smb_intel },␊
412␉{0x8086, 0x8C22, "HSW", read_smb_intel }, // Z87, H87, Q87, H81␊
413␉{0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, // new␊
414␉{0x8086, 0x8D22, "X99", read_smb_intel }, // new␊
415␉{0x8086, 0x9C22, "HSW-ULT", read_smb_intel }␊
416␊
417};␊
418␊
419// initial call : pci_dt = root_pci_dev;␊
420// find_and_read_smbus_controller(root_pci_dev);␊
421bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
422{␊
423␉pci_dt_t␉*current = pci_dt;␊
424␉int i;␊
425␊
426␉while (current) {␊
427#if 0␊
428␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
429␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
430␉␉current->class_id, current->vendor_id, current->device_id, ␊
431␉␉get_pci_dev_path(current));␊
432#endif␊
433␉␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ ) {␊
434␉␉␉if (current->vendor_id == smbus_controllers[i].vendor && current->device_id == smbus_controllers[i].device) {␊
435␉␉␉␉smbus_controllers[i].read_smb(current); // read smb␊
436␉␉␉␉return true;␊
437␉␉␉}␊
438␉␉}␊
439␉␉find_and_read_smbus_controller(current->children);␊
440␉␉current = current->next;␊
441␉}␊
442␉return false; // not found␊
443}␊
444␊
445void scan_spd(PlatformInfo_t *p)␊
446{␊
447␉find_and_read_smbus_controller(root_pci_dev);␊
448}␊
449␊
450

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