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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21#define XEON "Xeon"␊
22#define CORE_I3 "Core(TM) i3"␊
23#define CORE_I5 "Core(TM) i5"␊
24#define CORE_I7 "Core(TM) i7"␊
25␊
26␊
27bool getProcessorInformationExternalClock(returnType *value)␊
28{␊
29␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
30␉{␊
31␉␉switch (Platform.CPU.Family)␊
32␉␉{␊
33␉␉␉case 0x06:␊
34␉␉␉␉switch (Platform.CPU.Model)␊
35␉␉␉␉{␊
36␉␉␉␉␉// set external clock to 0 for SANDY␊
37␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
38␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
39␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
40␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
41␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
42␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
43␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
44␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
45␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
46␊
47␉␉␉␉␉␉value->word = 0;␊
48␉␉␉␉␉␉break;␊
49␉␉␉␉␉default:␊
50␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
51␉␉␉␉␉␉break;␊
52␉␉␉␉}␊
53␉␉␉␉break;␊
54␊
55␉␉␉default:␊
56␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
57␉␉␉␉break;␊
58␉␉}␊
59␉}␊
60␉else␊
61␉{␊
62␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
63␉}␊
64␊
65␉return true;␊
66}␊
67␊
68bool getProcessorInformationMaximumClock(returnType *value)␊
69{␊
70␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
71␉return true;␊
72}␊
73␊
74bool getSMBOemProcessorBusSpeed(returnType *value)␊
75{␊
76␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
77␉{␊
78␉␉switch (Platform.CPU.Family)␊
79␉␉{␊
80␉␉␉case 0x06:␊
81␉␉␉␉switch (Platform.CPU.Model)␊
82␉␉␉␉{␊
83␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
84␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
85␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
86␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
87␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
88␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
89␉␉␉␉␉␉return false;␊
90␊
91␉␉␉␉␉case 0x19:␊
92␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
93␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
94␉␉␉␉␉case CPUID_MODEL_DALES:␊
95␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
96␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
97␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
98␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
99␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
100␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
101␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
102␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
103␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
104␉␉␉␉␉{␊
105␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
106␉␉␉␉␉␉int nhm_bus = 0x3F;␊
107␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
108␉␉␉␉␉␉unsigned long did, vid;␊
109␉␉␉␉␉␉unsigned int i;␊
110␉␉␉␉␉␉␊
111␉␉␉␉␉␉// Nehalem supports Scrubbing␊
112␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
113␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
114␉␉␉␉␉␉{␊
115␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
116␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
117␉␉␉␉␉␉␉vid &= 0xFFFF;␊
118␉␉␉␉␉␉␉did &= 0xFF00;␊
119␉␉␉␉␉␉␉␊
120␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
121␉␉␉␉␉␉␉{␊
122␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
123␉␉␉␉␉␉␉}␊
124␉␉␉␉␉␉}␊
125␊
126␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
127␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
128␉␉␉␉␉␉qpimult &= 0x7F;␊
129␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
130␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
131␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
132␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
133␉␉␉␉␉␉{␊
134␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
135␉␉␉␉␉␉}␊
136␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
137␉␉␉␉␉␉value->word = qpibusspeed;␊
138␉␉␉␉␉␉return true;␊
139␉␉␉␉␉}␊
140␉␉␉␉␉break;␊
141␊
142␉␉␉␉␉default:␊
143␉␉␉␉␉␉break;␊
144␉␉␉␉}␊
145␉␉␉␉break;␊
146␊
147␉␉␉default:␊
148␉␉␉␉break;␊
149␉␉}␊
150␉}␊
151␊
152␉return false; //Unsupported CPU type␊
153}␊
154␊
155uint16_t simpleGetSMBOemProcessorType(void)␊
156{␊
157␉if (Platform.CPU.NoCores >= 4)␊
158␉{␊
159␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊
160␉}␊
161␉else if (Platform.CPU.NoCores == 1)␊
162␉{␊
163␉␉return 0x201;␉// 513 - Core Duo␊
164␉};␊
165␉␊
166␉return 0x301;␉␉// 769 - Core 2 Duo␊
167}␊
168␊
169bool getSMBOemProcessorType(returnType *value)␊
170{␊
171␉static bool done = false;␊
172␊
173␉value->word = simpleGetSMBOemProcessorType();␊
174␊
175␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
176␉{␊
177␉␉if (!done)␊
178␉␉{␊
179␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
180␉␉␉done = true;␊
181␉␉}␊
182␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊
183␉␉switch (Platform.CPU.Family)␊
184␉␉{␊
185␉␉␉case 0x0F:␊
186␉␉␉case 0x06:␊
187␊
188␉␉␉␉switch (Platform.CPU.Model)␊
189␉␉␉␉{␊
190␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
191␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊
192␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
193␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
194␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
195␉␉␉␉␉␉{␊
196␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
197␉␉␉␉␉␉}␊
198␉␉␉␉␉␉return true;␊
199␊
200␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
201␉␉␉␉␉case CPUID_MODEL_CELERON:␊
202␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
203␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
204␉␉␉␉␉␉return true;␊
205␊
206␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
207␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
208␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
209␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
210␉␉␉␉␉␉{␊
211␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
212␉␉␉␉␉␉␉return true;␊
213␉␉␉␉␉␉}␊
214␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
215␉␉␉␉␉␉{␊
216␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊
217␉␉␉␉␉␉}␊
218␉␉␉␉␉␉else␊
219␉␉␉␉␉␉{␊
220␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊
221␉␉␉␉␉␉}␊
222␉␉␉␉␉␉return true;␊
223␊
224␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
225␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
226␉␉␉␉␉␉return true;␊
227␊
228␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
229␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
230␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
231␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
232␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
233␉␉␉␉␉␉{␊
234␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
235␉␉␉␉␉␉␉return true;␊
236␉␉␉␉␉␉}␊
237␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
238␉␉␉␉␉␉{␊
239␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
240␉␉␉␉␉␉␉return true;␊
241␉␉␉␉␉␉}␊
242␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
243␉␉␉␉␉␉{␊
244␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
245␉␉␉␉␉␉␉return true;␊
246␉␉␉␉␉␉}␊
247␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
248␉␉␉␉␉␉{␊
249␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊
250␉␉␉␉␉␉␉return true;␊
251␉␉␉␉␉␉}␊
252␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
253␉␉␉␉␉␉{␊
254␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊
255␉␉␉␉␉␉}␊
256␉␉␉␉␉␉return true;␊
257␊
258␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
259␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
260␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
261␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
262␉␉␉␉␉␉{␊
263␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
264␉␉␉␉␉␉␉return true;␊
265␉␉␉␉␉␉}␊
266␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
267␉␉␉␉␉␉{␊
268␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊
269␉␉␉␉␉␉␉return true;␊
270␉␉␉␉␉␉}␊
271␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
272␉␉␉␉␉␉{␊
273␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊
274␉␉␉␉␉␉␉return true;␊
275␉␉␉␉␉␉}␊
276␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
277␉␉␉␉␉␉{␊
278␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊
279␉␉␉␉␉␉␉return true;␊
280␉␉␉␉␉␉}␊
281␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
282␉␉␉␉␉␉{␊
283␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊
284␉␉␉␉␉␉}␊
285␉␉␉␉␉␉return true;␊
286␊
287␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
288␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
289␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
290␉␉␉␉␉␉{␊
291␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
292␉␉␉␉␉␉␉return true;␊
293␉␉␉␉␉␉}␊
294␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
295␉␉␉␉␉␉{␊
296␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊
297␉␉␉␉␉␉␉return true;␊
298␉␉␉␉␉␉}␊
299␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
300␉␉␉␉␉␉{␊
301␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊
302␉␉␉␉␉␉␉return true;␊
303␉␉␉␉␉␉}␊
304␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
305␉␉␉␉␉␉{␊
306␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊
307␉␉␉␉␉␉␉return true;␊
308␉␉␉␉␉␉}␊
309␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
310␉␉␉␉␉␉{␊
311␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊
312␉␉␉␉␉␉}␊
313␉␉␉␉␉␉return true;␊
314␊
315␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
316␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
317␉␉␉␉␉␉{␊
318␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
319␉␉␉␉␉␉␉return true;␊
320␉␉␉␉␉␉}␊
321␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
322␉␉␉␉␉␉{␊
323␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊
324␉␉␉␉␉␉␉return true;␊
325␉␉␉␉␉␉}␊
326␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
327␉␉␉␉␉␉{␊
328␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊
329␉␉␉␉␉␉␉return true;␊
330␉␉␉␉␉␉}␊
331␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
332␉␉␉␉␉␉{␊
333␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊
334␉␉␉␉␉␉␉return true;␊
335␉␉␉␉␉␉}␊
336␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
337␉␉␉␉␉␉{␊
338␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊
339␉␉␉␉␉␉}␊
340␉␉␉␉␉␉return true;␊
341␊
342␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
343␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
344␉␉␉␉␉␉return true;␊
345␊
346␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊
347␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
348␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
349␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
350␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
351␉␉␉␉␉␉{␊
352␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
353␉␉␉␉␉␉␉return true;␊
354␉␉␉␉␉␉}␊
355␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊
356␉␉␉␉␉␉{␊
357␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊
358␉␉␉␉␉␉␉return true;␊
359␉␉␉␉␉␉}␊
360␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊
361␉␉␉␉␉␉{␊
362␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊
363␉␉␉␉␉␉␉return true;␊
364␉␉␉␉␉␉}␊
365␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊
366␉␉␉␉␉␉{␊
367␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊
368␉␉␉␉␉␉␉return true;␊
369␉␉␉␉␉␉}␊
370␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
371␉␉␉␉␉␉{␊
372␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊
373␉␉␉␉␉␉}␊
374␉␉␉␉␉␉return true;␊
375␊
376␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
377␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊
378␉␉␉␉␉␉return true;␊
379␊
380␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
381␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
382␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊
383␉␉␉␉␉␉return true;␊
384␉␉␉␉␉default:␊
385␉␉␉␉␉␉break; // Unsupported CPU type␊
386␉␉␉␉}␊
387␉␉␉␉break;␊
388␊
389␉␉␉default:␊
390␉␉␉␉break;␊
391␉␉}␊
392␉}␊
393␉␊
394␉return false;␊
395}␊
396␊
397bool getSMBMemoryDeviceMemoryType(returnType *value)␊
398{␊
399␉static int idx = -1;␊
400␉int␉map;␊
401␊
402␉if (!bootInfo->memDetect)␊
403␉{␊
404␉␉return false;␊
405␉}␊
406␊
407␉idx++;␊
408␉if (idx < MAX_RAM_SLOTS)␊
409␉{␊
410␉␉map = Platform.DMI.DIMM[idx];␊
411␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
412␉␉{␊
413␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
414␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
415␉␉␉return true;␊
416␉␉}␊
417␉}␊
418␊
419␉value->byte = 2; // means Unknown␊
420␉return true;␊
421//␉value->byte = SMB_MEM_TYPE_DDR2;␊
422//␉return true;␊
423}␊
424␊
425bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
426{␊
427␉value->word = 0xFFFF;␊
428␉return true;␊
429}␊
430␊
431bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
432{␊
433␉static int idx = -1;␊
434␉int␉map;␊
435␊
436␉if (!bootInfo->memDetect)␊
437␉{␊
438␉␉return false;␊
439␉}␊
440␊
441␉idx++;␊
442␉if (idx < MAX_RAM_SLOTS)␊
443␉{␊
444␉␉map = Platform.DMI.DIMM[idx];␊
445␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
446␉␉{␊
447␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
448␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
449␉␉␉return true;␊
450␉␉}␊
451␉}␊
452␊
453␉value->dword = 0; // means Unknown␊
454␉return true;␊
455//␉value->dword = 800;␊
456//␉return true;␊
457}␊
458␊
459bool getSMBMemoryDeviceManufacturer(returnType *value)␊
460{␊
461␉static int idx = -1;␊
462␉int␉map;␊
463␊
464␉if (!bootInfo->memDetect)␊
465␉{␊
466␉␉return false;␊
467␉}␊
468␊
469␉idx++;␊
470␉if (idx < MAX_RAM_SLOTS)␊
471␉{␊
472␉␉map = Platform.DMI.DIMM[idx];␊
473␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
474␉␉{␊
475␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
476␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
477␉␉␉return true;␊
478␉␉}␊
479␉}␊
480␊
481␉value->string = NOT_AVAILABLE;␊
482␉return true;␊
483}␊
484␊
485bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
486{␊
487␉static int idx = -1;␊
488␉int␉map;␊
489␊
490␉if (!bootInfo->memDetect)␊
491␉{␊
492␉␉return false;␊
493␉}␊
494␊
495␉idx++;␊
496␊
497␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
498␊
499␉if (idx < MAX_RAM_SLOTS)␊
500␉{␊
501␉␉map = Platform.DMI.DIMM[idx];␊
502␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
503␉␉{␊
504␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
505␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
506␉␉␉return true;␊
507␉␉}␊
508␉}␊
509␊
510␉value->string = NOT_AVAILABLE;␊
511␉return true;␊
512}␊
513␊
514bool getSMBMemoryDevicePartNumber(returnType *value)␊
515{␊
516␉static int idx = -1;␊
517␉int␉map;␊
518␊
519␉if (!bootInfo->memDetect)␊
520␉{␊
521␉␉return false;␊
522␉}␊
523␊
524␉idx++;␊
525␉if (idx < MAX_RAM_SLOTS)␊
526␉{␊
527␉␉map = Platform.DMI.DIMM[idx];␊
528␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
529␉␉{␊
530␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
531␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
532␉␉␉return true;␊
533␉␉}␊
534␉}␊
535␊
536␉value->string = NOT_AVAILABLE;␊
537␉return true;␊
538}␊
539␊
540␊
541// getting smbios addr with fast compare ops, late checksum testing ...␊
542#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
543static const char * const SMTAG = "_SM_";␊
544static const char* const DMITAG = "_DMI_";␊
545␊
546SMBEntryPoint *getAddressOfSmbiosTable(void)␊
547{␊
548␉SMBEntryPoint␉*smbios;␊
549␉/*␊
550␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
551␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
552␉ */␊
553␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
554␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊
555␉{␊
556␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
557␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
558␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
559␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
560␉␉{␊
561␉␉␉return smbios;␊
562␉ }␊
563␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
564␉}␊
565␉printf("ERROR: Unable to find SMBIOS!\n");␊
566␉pause();␊
567␉return NULL;␊
568}␊
569␊
570

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