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Root/trunk/i386/libsaio/cpu.c

1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30␉int␉␉attempts = 0;␊
31␉uint64_t latchTime;␊
32␉uint64_t␉saveTime,intermediate;␊
33␉unsigned int timerValue, lastValue;␊
34␉//boolean_t␉int_enabled;␊
35␉/*␊
36␉ * Table of correction factors to account for␊
37␉ *␉ - timer counter quantization errors, and␊
38␉ *␉ - undercounts 0..5␊
39␉ */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45␉uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52␉};␊
53␊
54␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊
55␊
56restart:␊
57␉if (attempts >= 9) // increase to up to 9 attempts.␊
58␉{␊
59␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
60␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
61␉}␊
62␉attempts++;␊
63␉enable_PIT2();␉␉// turn on PIT2␊
64␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
65␉latchTime = rdtsc64();␉// get the time stamp to time ␊
66␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
67␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
68␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
69␉get_PIT2(&lastValue);␊
70␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
71␉do {␊
72␉␉intermediate = get_PIT2(&timerValue);␊
73␉␉if (timerValue > lastValue)␊
74␉␉{␊
75␉␉␉// Timer wrapped␊
76␉␉␉set_PIT2(0);␊
77␉␉␉disable_PIT2();␊
78␉␉␉goto restart;␊
79␉␉}␊
80␉␉lastValue = timerValue;␊
81␉} while (timerValue > 5);␊
82␉printf("timerValue␉ %d\n",timerValue);␊
83␉printf("intermediate 0x%016llX\n",intermediate);␊
84␉printf("saveTime␉ 0x%016llX\n",saveTime);␊
85 ␊
86␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
87␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
88␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
89␉intermediate += latchTime;␉␉// add on our save fudge␊
90␊
91␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
92␉disable_PIT2();␉␉␉// turn off PIT 2␊
93␊
94␉//ml_set_interrupts_enabled(int_enabled);␊
95␉return intermediate;␊
96}␊
97␊
98/*␊
99 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
100 */␊
101static uint64_t measure_tsc_frequency(void)␊
102{␊
103␉uint64_t tscStart;␊
104␉uint64_t tscEnd;␊
105␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
106␉unsigned long pollCount;␊
107␉uint64_t retval = 0;␊
108␉int i;␊
109␊
110␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
111␉ * counter 2. We run this loop 3 times to make sure the cache␊
112␉ * is hot and we take the minimum delta from all of the runs.␊
113␉ * That is to say that we're biased towards measuring the minimum␊
114␉ * number of TSC ticks that occur while waiting for the timer to␊
115␉ * expire. That theoretically helps avoid inconsistencies when␊
116␉ * running under a VM if the TSC is not virtualized and the host␊
117␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
118␉ */␊
119␉for(i = 0; i < 10; ++i)␊
120␉{␊
121␉␉enable_PIT2();␊
122␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
123␉␉tscStart = rdtsc64();␊
124␉␉pollCount = poll_PIT2_gate();␊
125␉␉tscEnd = rdtsc64();␊
126␉␉/* The poll loop must have run at least a few times for accuracy */␊
127␉␉if (pollCount <= 1) {␊
128␉␉␉continue;␊
129␉␉}␊
130␉␉/* The TSC must increment at LEAST once every millisecond.␊
131␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
132␉␉ * be >= 30. Anything less and the processor is way too slow.␊
133␉␉ */␊
134␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {␊
135␉␉␉continue;␊
136␉␉}␊
137␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
138␉␉if ( (tscEnd - tscStart) < tscDelta ) {␊
139␉␉␉tscDelta = tscEnd - tscStart;␊
140␉␉}␊
141␉}␊
142␉/* tscDelta is now the least number of TSC ticks the processor made in␊
143␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
144␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
145␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
146␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
147␉ * dividing by the milliseconds, we simply multiply by 1000.␊
148␉ */␊
149␊
150␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
151␉ * that we're going to multiply by 1000 first so we do need at least some␊
152␉ * arithmetic headroom. For now, 32-bit should be enough.␊
153␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
154␉ */␊
155␉if (tscDelta > (1ULL<<32)) {␊
156␉␉retval = 0;␊
157␉} else {␊
158␉␉retval = tscDelta * 1000 / 30;␊
159␉}␊
160␉disable_PIT2();␊
161␉return retval;␊
162}␊
163␊
164/*␊
165 * Original comment/code:␊
166 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
167 *␊
168 * Measures the Actual Performance Frequency in Hz (64-bit)␊
169 * (just a naming change, mperf --> aperf )␊
170 */␊
171static uint64_t measure_aperf_frequency(void)␊
172{␊
173␉uint64_t aperfStart;␊
174␉uint64_t aperfEnd;␊
175␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
176␉unsigned long pollCount;␊
177␉uint64_t retval = 0;␊
178␉int i;␊
179␊
180␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
181␉ * counter 2. We run this loop 3 times to make sure the cache␊
182␉ * is hot and we take the minimum delta from all of the runs.␊
183␉ * That is to say that we're biased towards measuring the minimum␊
184␉ * number of APERF ticks that occur while waiting for the timer to␊
185␉ * expire.␊
186␉ */␊
187␉for(i = 0; i < 10; ++i)␊
188␉{␊
189␉␉enable_PIT2();␊
190␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
191␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
192␉␉pollCount = poll_PIT2_gate();␊
193␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
194␉␉/* The poll loop must have run at least a few times for accuracy */␊
195␉␉if (pollCount <= 1)␊
196␉␉{␊
197␉␉␉continue;␊
198␉␉}␊
199␉␉/* The TSC must increment at LEAST once every millisecond.␊
200␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
201␉␉ * be >= 30. Anything less and the processor is way too slow.␊
202␉␉ */␊
203␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
204␉␉{␊
205␉␉␉continue;␊
206␉␉}␊
207␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
208␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
209␉␉{␊
210␉␉␉aperfDelta = aperfEnd - aperfStart;␊
211␉␉}␊
212␉}␊
213␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
214␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
215␉ */␊
216␊
217␉if (aperfDelta > (1ULL<<32))␊
218␉{␊
219␉␉retval = 0;␊
220␉}␊
221␉else␊
222␉{␊
223␉␉retval = aperfDelta * 1000 / 30;␊
224␉}␊
225␉disable_PIT2();␊
226␉return retval;␊
227}␊
228␊
229/*␊
230 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
231 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
232 *␉ a max multi. (used to calculate the FSB freq.),␊
233 *␉ and a current multi. (used to calculate the CPU freq.)␊
234 * - fsbFrequency = tscFrequency / multi␊
235 * - cpuFrequency = fsbFrequency * multi␊
236 */␊
237void scan_cpu(PlatformInfo_t *p)␊
238{␊
239␉uint64_t␉tscFrequency␉= 0;␊
240␉uint64_t␉fsbFrequency␉= 0;␊
241␉uint64_t␉cpuFrequency␉= 0;␊
242␉uint64_t␉msr␉␉= 0;␊
243␉uint64_t␉flex_ratio␉= 0;␊
244␊
245␉uint32_t␉max_ratio␉= 0;␊
246␉uint32_t␉min_ratio␉= 0;␊
247␉uint32_t␉reg[4];␊
248␊
249␉uint8_t␉␉bus_ratio_max␉= 0;␊
250␉uint8_t␉␉bus_ratio_min␉= 0;␊
251␉uint8_t␉␉currdiv␉␉= 0;␊
252␉uint8_t␉␉currcoef␉= 0;␊
253␉uint8_t␉␉maxdiv␉␉= 0;␊
254␉uint8_t␉␉maxcoef␉␉= 0;␊
255␊
256␉const char␉*newratio;␊
257␉char␉␉str[128];␊
258␊
259␉int␉␉len = 0;␊
260␉int␉␉myfsb = 0;␊
261␊
262␉/* get cpuid values */␊
263␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
264␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
265␊
266␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
267␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
268␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
269␊
270␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
271␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊
272␉{␊
273␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
274␉}␊
275␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊
276␉{␊
277␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
278␉}␊
279␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
280␉{␊
281␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
282␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
283␉}␊
284␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
285␉{␊
286␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
287␉}␊
288␊
289// #if DEBUG_CPU␊
290␉{␊
291␉␉int␉␉i;␊
292␉␉DBG("CPUID Raw Values:\n");␊
293␉␉for (i = 0; i < CPUID_MAX; i++) {␊
294␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
295␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
296␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
297␉␉}␊
298␉}␊
299// #endif␊
300␊
301/*␊
302 EAX (Intel):␊
303 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
304 +--------+----------------+--------+----+----+--------+--------+--------+␊
305 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
306 +--------+----------------+--------+----+----+--------+--------+--------+␊
307␊
308 EAX (AMD):␊
309 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
310 +--------+----------------+--------+----+----+--------+--------+--------+␊
311 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
312 +--------+----------------+--------+----+----+--------+--------+--------+␊
313*/␊
314␊
315␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
316␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
317␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
318␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
319␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
320␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
321␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
322␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
323␊
324␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
325␊
326␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
327␉␉p->CPU.Family == 0x06 &&␊
328␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
329␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
330␉␉)␊
331␉{␊
332␉␉/*␊
333␉␉ * Find the number of enabled cores and threads␊
334␉␉ * (which determines whether SMT/Hyperthreading is active).␊
335␉␉ */␊
336␉␉switch (p->CPU.Model)␊
337␉␉{␊
338␉␉␉case CPUID_MODEL_NEHALEM:␊
339␉␉␉case CPUID_MODEL_FIELDS:␊
340␉␉␉case CPUID_MODEL_DALES:␊
341␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
342␉␉␉case CPUID_MODEL_JAKETOWN:␊
343␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
344␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
345␉␉␉case CPUID_MODEL_HASWELL:␊
346␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
347␉␉␉//case CPUID_MODEL_HASWELL_H:␊
348␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
349␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
350␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
351␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊
352␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
353␉␉␉␉break;␊
354␊
355␉␉␉case CPUID_MODEL_DALES_32NM:␊
356␉␉␉case CPUID_MODEL_WESTMERE:␊
357␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
358␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
359␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊
360␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
361␉␉␉␉break;␊
362␊
363␉␉␉default:␊
364␉␉␉␉p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
365␉␉␉␉p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊
366␉␉␉␉//workaround for N270. I don't know why it detected wrong␊
367␉␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (p->CPU.Stepping == 2))␊
368␉␉␉␉{␊
369␉␉␉␉␉p->CPU.NoCores = 1;␊
370␉␉␉␉}␊
371␉␉␉␉break;␊
372␊
373␉␉} // end switch␊
374␊
375␉}␊
376␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
377␉{␊
378␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
379␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
380␉}␊
381␉else␊
382␉{␊
383␉␉// Use previous method for Cores and Threads␊
384␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
385␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
386␉}␊
387␊
388␉/* get BrandString (if supported) */␊
389␉/* Copyright: from Apple's XNU cpuid.c */␊
390␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
391␉{␊
392␉␉char␉ *s;␊
393␉␉bzero(str, 128);␊
394␉␉/*␊
395␉␉ * The BrandString 48 bytes (max), guaranteed to␊
396␉␉ * be NULL terminated.␊
397␉␉ */␊
398␉␉do_cpuid(0x80000002, reg);␊
399␉␉memcpy(&str[0], (char *)reg, 16);␊
400␉␉do_cpuid(0x80000003, reg);␊
401␉␉memcpy(&str[16], (char *)reg, 16);␊
402␉␉do_cpuid(0x80000004, reg);␊
403␉␉memcpy(&str[32], (char *)reg, 16);␊
404␉␉for (s = str; *s != '\0'; s++)␊
405␉␉{␊
406␉␉␉if (*s != ' ')␊
407␉␉␉{␊
408␉␉␉␉break;␊
409␉␉␉}␊
410␉␉}␊
411␉␉strlcpy(p->CPU.BrandString, s, 48);␊
412␊
413␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
414␉␉{␊
415␉␉␉/*␊
416␉␉␉ * This string means we have a firmware-programmable brand string,␊
417␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
418␉␉␉ */␊
419␉␉␉p->CPU.BrandString[0] = '\0';␊
420␉␉}␊
421␉␉p->CPU.BrandString[47] = '\0';␊
422//␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊
423␉}␊
424␊
425␉/* setup features */␊
426␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
427␉{␊
428␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
429␉}␊
430␊
431␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
432␉{␊
433␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
434␉}␊
435␊
436␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
437␉{␊
438␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
439␉}␊
440␊
441␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
442␉{␊
443␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
444␉}␊
445␊
446␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
447␉{␊
448␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
449␉}␊
450␊
451␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
452␉{␊
453␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
454␉}␊
455␊
456␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
457␉{␊
458␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
459␉}␊
460␊
461␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
462␉{␊
463␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
464␉}␊
465␊
466␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
467␊
468␉if (p->CPU.NoThreads > p->CPU.NoCores)␊
469␉{␊
470␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
471␉}␊
472␊
473␉tscFrequency = measure_tsc_frequency();␊
474␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊
475␉/* if usual method failed */␊
476␉if ( tscFrequency < 1000 )␉//TEST␊
477␉{␊
478␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊
479␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
480␉}␊
481␉else␊
482␉{␊
483␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊
484␉}␊
485␊
486␉fsbFrequency = 0;␊
487␉cpuFrequency = 0;␊
488␊
489␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
490␉{␊
491␉␉int intelCPU = p->CPU.Model;␊
492␉␉if (p->CPU.Family == 0x06)␊
493␉␉{␊
494␉␉␉/* Nehalem CPU model */␊
495␉␉␉switch (p->CPU.Model)␊
496␉␉␉{␊
497␉␉␉␉case CPUID_MODEL_NEHALEM:␊
498␉␉␉␉case CPUID_MODEL_FIELDS:␊
499␉␉␉␉case CPUID_MODEL_DALES:␊
500␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
501␉␉␉␉case CPUID_MODEL_WESTMERE:␊
502␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
503␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
504/* --------------------------------------------------------- */␊
505␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
506␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
507␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
508␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
509␉␉␉␉case CPUID_MODEL_HASWELL:␊
510␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
511␊
512␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
513␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
514/* --------------------------------------------------------- */␊
515␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
516␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
517␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
518␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
519␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
520␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
521␉␉␉␉␉if (bitfield(msr, 16, 16))␊
522␉␉␉␉␉{␊
523␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
524␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
525␉␉␉␉␉␉ where the cpu multipler can't be changed to␊
526␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
527␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
528␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
529␉␉␉␉␉␉ causing the system to crash since tscGranularity␊
530␉␉␉␉␉␉ is inadvertently set to 0.␊
531␉␉␉␉␉␉ */␊
532␉␉␉␉␉␉if (flex_ratio == 0)␊
533␉␉␉␉␉␉{␊
534␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
535␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
536␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
537␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
538␉␉␉␉␉␉}␊
539␉␉␉␉␉␉else␊
540␉␉␉␉␉␉{␊
541␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
542␉␉␉␉␉␉␉{␊
543␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
544␉␉␉␉␉␉␉}␊
545␉␉␉␉␉␉}␊
546␉␉␉␉␉}␊
547␊
548␉␉␉␉␉if (bus_ratio_max)␊
549␉␉␉␉␉{␊
550␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
551␉␉␉␉␉}␊
552␊
553␉␉␉␉␉//valv: Turbo Ratio Limit␊
554␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
555␉␉␉␉␉{␊
556␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
557␊
558␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
559␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
560␉␉␉␉␉}␊
561␉␉␉␉␉else␊
562␉␉␉␉␉{␊
563␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
564␉␉␉␉␉}␊
565␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
566␉␉␉␉␉{␊
567␉␉␉␉␉␉max_ratio = atoi(newratio);␊
568␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
569␉␉␉␉␉␉if (len >= 3)␊
570␉␉␉␉␉␉{␊
571␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
572␉␉␉␉␉␉}␊
573␊
574␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
575␊
576␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
577␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
578␉␉␉␉␉␉{␊
579␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
580␉␉␉␉␉␉␉if (len >= 3)␊
581␉␉␉␉␉␉␉{␊
582␉␉␉␉␉␉␉␉maxdiv = 1;␊
583␉␉␉␉␉␉␉}␊
584␉␉␉␉␉␉␉else␊
585␉␉␉␉␉␉␉{␊
586␉␉␉␉␉␉␉␉maxdiv = 0;␊
587␉␉␉␉␉␉␉}␊
588␉␉␉␉␉␉}␊
589␉␉␉␉␉␉else␊
590␉␉␉␉␉␉{␊
591␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
592␉␉␉␉␉␉}␊
593␉␉␉␉␉}␊
594␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
595␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
596␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
597␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
598␊
599␉␉␉␉myfsb = fsbFrequency / 1000000;␊
600␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
601␉␉␉␉currcoef = bus_ratio_max;␊
602␊
603␉␉␉␉break;␊
604␊
605␉␉␉default:␊
606␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
607␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
608␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
609␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
610␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
611␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
612␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
613␊
614␉␉␉␉// This will always be model >= 3␊
615␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
616␉␉␉␉{␊
617␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
618␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
619␉␉␉␉}␊
620␉␉␉␉else␊
621␉␉␉␉{␊
622␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
623␉␉␉␉␉/* XXX */␊
624␉␉␉␉␉maxcoef = currcoef;␊
625␉␉␉␉}␊
626␊
627␉␉␉␉if (!currcoef)␊
628␉␉␉␉{␊
629␉␉␉␉␉currcoef = maxcoef;␊
630␉␉␉␉}␊
631␊
632␉␉␉␉if (maxcoef)␊
633␉␉␉␉{␊
634␉␉␉␉␉if (maxdiv)␊
635␉␉␉␉␉{␊
636␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
637␉␉␉␉␉}␊
638␉␉␉␉␉else␊
639␉␉␉␉␉{␊
640␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
641␉␉␉␉␉}␊
642␊
643␉␉␉␉␉if (currdiv)␊
644␉␉␉␉␉{␊
645␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
646␉␉␉␉␉}␊
647␉␉␉␉␉else␊
648␉␉␉␉␉{␊
649␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
650␉␉␉␉␉}␊
651␊
652␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
653␉␉␉␉}␊
654␉␉␉␉break;␊
655␉␉␉}␊
656␉␉}␊
657␉␉// Mobile CPU␊
658␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
659␉␉{␊
660␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
661␉␉}␊
662␉}␊
663␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
664␉{␊
665␉␉switch(p->CPU.ExtFamily)␊
666␉␉{␊
667␉␉␉case 0x00: //* K8 *//␊
668␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
669␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
670␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
671␉␉␉␉break;␊
672␊
673␉␉␉case 0x01: //* K10 *//␊
674␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
675␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
676␉␉␉␉// EffFreq: effective frequency interface␊
677␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
678␉␉␉␉{␊
679␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
680␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
681␉␉␉␉␉cpuFrequency = aperf;␊
682␉␉␉␉}␊
683␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
684␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
685␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
686␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
687␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
688␊
689␉␉␉␉break;␊
690␊
691␉␉␉case 0x05: //* K14 *//␊
692␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
693␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
694␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
695␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
696␊
697␉␉␉␉break;␊
698␊
699␉␉␉case 0x02: //* K11 *//␊
700␉␉␉␉// not implimented␊
701␉␉␉␉break;␊
702␉␉}␊
703␊
704␉␉if (maxcoef)␊
705␉␉{␊
706␉␉␉if (currdiv)␊
707␉␉␉{␊
708␉␉␉␉if (!currcoef)␊
709␉␉␉␉{␊
710␉␉␉␉␉currcoef = maxcoef;␊
711␉␉␉␉}␊
712␊
713␉␉␉␉if (!cpuFrequency)␊
714␉␉␉␉{␊
715␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
716␉␉␉␉}␊
717␉␉␉␉else␊
718␉␉␉␉{␊
719␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
720␉␉␉␉}␊
721␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
722␉␉␉}␊
723␉␉␉else␊
724␉␉␉{␊
725␉␉␉␉if (!cpuFrequency)␊
726␉␉␉␉{␊
727␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
728␉␉␉␉}␊
729␉␉␉␉else␊
730␉␉␉␉{␊
731␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
732␉␉␉␉}␊
733␉␉␉␉DBG("%d\n", currcoef);␊
734␉␉␉}␊
735␉␉}␊
736␉␉else if (currcoef)␊
737␉␉{␊
738␉␉␉if (currdiv)␊
739␉␉␉{␊
740␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
741␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
742␉␉␉}␊
743␉␉␉else␊
744␉␉␉{␊
745␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
746␉␉␉␉DBG("%d\n", currcoef);␊
747␉␉␉}␊
748␉␉}␊
749␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
750␉}␊
751␉␊
752#if 0␊
753␉if (!fsbFrequency)␊
754␉{␊
755␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
756␉␉cpuFrequency = tscFrequency;␊
757␉␉DBG("0 ! using the default value for FSB !\n");␊
758␉}␊
759␊
760␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊
761␊
762#endif␊
763␊
764␉p->CPU.MaxCoef = maxcoef;␊
765␉p->CPU.MaxDiv = maxdiv;␊
766␉p->CPU.CurrCoef = currcoef;␊
767␉p->CPU.CurrDiv = currdiv;␊
768␉p->CPU.TSCFrequency = tscFrequency;␊
769␉p->CPU.FSBFrequency = fsbFrequency;␊
770␉p->CPU.CPUFrequency = cpuFrequency;␊
771␊
772␉// keep formatted with spaces instead of tabs␊
773␉DBG("\n---------------------------------------------\n");␊
774 ␉DBG("------------------ CPU INFO -----------------\n");␊
775␉DBG("---------------------------------------------\n");␊
776␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
777␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
778␉DBG("Family: 0x%x\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
779␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊
780␉DBG("Signature: %x\n",␉␉p->CPU.Signature);␉␉// CPUID signature␊
781␉DBG("Model: 0x%x\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
782␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊
783␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
784␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊
785␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊
786␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊
787␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊
788␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊
789␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊
790␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊
791␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
792␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
793␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊
794␊
795␉DBG("\n---------------------------------------------\n");␊
796#if DEBUG_CPU␊
797␉pause();␊
798#endif␊
799}␊
800

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